From patchwork Tue Dec 3 13:48:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 915 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pg1-f199.google.com (mail-pg1-f199.google.com [209.85.215.199]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id DD4433F0CC for ; Tue, 3 Dec 2019 14:48:36 +0100 (CET) Received: by mail-pg1-f199.google.com with SMTP id u11sf1700573pgm.20 for ; Tue, 03 Dec 2019 05:48:36 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1575380915; cv=pass; d=google.com; s=arc-20160816; b=LS2n32eiR25+8TH8BTG5zW0YqAvn6SPKTPwpXjTqwsGbkDbu3bZg4amgjc74JmmjIs uddgkWtU6XFIYY464S7jd7jlyQdnnn+IcG4Mw7PyZ6rD9ZXlNbHwceWjgcyUF0FWZPFX PgnVnx2qwyqWHjgKbcX10xZhl8AbOEUrrsbA4xJd3Jr5eqNaCoq72P6JI5rkczjJ9YGH AhvR0zowyFwuDVnp8s4Se8f55S+inJLuqoP+jRAe42uzJEvEW7+ofIy1kG2G7w/k2In5 vRV7TndJ6W7PqzfVFhTvwtxItAHi+sqkP+ucpcnXaUHJN9ZHLu8nz0pXYBy4/tHStN8f giRg== ARC-Message-Signature: i=2; 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[209.85.220.65]) by mx.google.com with SMTPS id d34sor2660661pgb.20.2019.12.03.05.48.34 for (Google Transport Security); Tue, 03 Dec 2019 05:48:34 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a63:e94d:: with SMTP id q13mr5361869pgj.209.1575380914518; Tue, 03 Dec 2019 05:48:34 -0800 (PST) Received: from localhost.localdomain ([115.97.190.29]) by smtp.gmail.com with ESMTPSA id y144sm4397892pfb.188.2019.12.03.05.48.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2019 05:48:34 -0800 (PST) From: Jagan Teki To: Maxime Ripard , Chen-Yu Tsai , David Airlie , Daniel Vetter , Rob Herring , Mark Rutland Cc: michael@amarulasolutions.com, Icenowy Zheng , linux-sunxi , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v12 1/7] dt-bindings: sun6i-dsi: Document A64 MIPI-DSI controller Date: Tue, 3 Dec 2019 19:18:10 +0530 Message-Id: <20191203134816.5319-2-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20191203134816.5319-1-jagan@amarulasolutions.com> References: <20191203134816.5319-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=kxVcUwh6; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The MIPI DSI controller in Allwinner A64 is similar to A33. But unlike A33, A64 doesn't have DSI_SCLK gating so it is valid to have separate compatible for A64 on the same driver. DSI_SCLK uses mod clock-names on dt-bindings, so the same is not required for A64. On that note - A64 require minimum of 1 clock like the bus clock - A33 require minimum of 2 clocks like both bus, mod clocks So, update dt-bindings so-that it can document both A33, A64 bindings requirements. Reviewed-by: Rob Herring Signed-off-by: Jagan Teki --- Changes for v12: - Use 'enum' instead of oneOf+const .../display/allwinner,sun6i-a31-mipi-dsi.yaml | 20 +++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml b/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml index dafc0980c4fa..b91446475f35 100644 --- a/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml +++ b/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml @@ -15,7 +15,9 @@ properties: "#size-cells": true compatible: - const: allwinner,sun6i-a31-mipi-dsi + enum: + - allwinner,sun6i-a31-mipi-dsi + - allwinner,sun50i-a64-mipi-dsi reg: maxItems: 1 @@ -24,6 +26,8 @@ properties: maxItems: 1 clocks: + minItems: 1 + maxItems: 2 items: - description: Bus Clock - description: Module Clock @@ -63,13 +67,25 @@ required: - reg - interrupts - clocks - - clock-names - phys - phy-names - resets - vcc-dsi-supply - port +allOf: + - if: + properties: + compatible: + contains: + const: allwinner,sun6i-a31-mipi-dsi + then: + properties: + clocks: + minItems: 2 + required: + - clock-names + additionalProperties: false examples: From patchwork Tue Dec 3 13:48:11 2019 Content-Type: text/plain; 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[209.85.220.65]) by mx.google.com with SMTPS id x200sor3696953pfc.26.2019.12.03.05.48.40 for (Google Transport Security); Tue, 03 Dec 2019 05:48:40 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a62:2686:: with SMTP id m128mr4905220pfm.143.1575380919848; Tue, 03 Dec 2019 05:48:39 -0800 (PST) Received: from localhost.localdomain ([115.97.190.29]) by smtp.gmail.com with ESMTPSA id y144sm4397892pfb.188.2019.12.03.05.48.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2019 05:48:39 -0800 (PST) From: Jagan Teki To: Maxime Ripard , Chen-Yu Tsai , David Airlie , Daniel Vetter , Rob Herring , Mark Rutland Cc: michael@amarulasolutions.com, Icenowy Zheng , linux-sunxi , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v12 2/7] dt-bindings: sun6i-dsi: Add A64 DPHY compatible (w/ A31 fallback) Date: Tue, 3 Dec 2019 19:18:11 +0530 Message-Id: <20191203134816.5319-3-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20191203134816.5319-1-jagan@amarulasolutions.com> References: <20191203134816.5319-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="gO/BVoVs"; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The MIPI DSI PHY controller on Allwinner A64 is similar on the one on A31. Add A64 compatible and append A31 compatible as fallback. Signed-off-by: Jagan Teki Reviewed-by: Rob Herring --- Changes for v12: - none .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml index fa46670de299..8841938050b2 100644 --- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml +++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml @@ -15,7 +15,11 @@ properties: const: 0 compatible: - const: allwinner,sun6i-a31-mipi-dphy + oneOf: + - const: allwinner,sun6i-a31-mipi-dphy + - items: + - const: allwinner,sun50i-a64-mipi-dphy + - const: allwinner,sun6i-a31-mipi-dphy reg: maxItems: 1 From patchwork Tue Dec 3 13:48:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 917 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pj1-f72.google.com (mail-pj1-f72.google.com [209.85.216.72]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 4E4D33F0CC for ; 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[209.85.220.65]) by mx.google.com with SMTPS id k11sor2672679pgr.29.2019.12.03.05.48.45 for (Google Transport Security); Tue, 03 Dec 2019 05:48:45 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a63:c652:: with SMTP id x18mr5478439pgg.211.1575380925537; Tue, 03 Dec 2019 05:48:45 -0800 (PST) Received: from localhost.localdomain ([115.97.190.29]) by smtp.gmail.com with ESMTPSA id y144sm4397892pfb.188.2019.12.03.05.48.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2019 05:48:45 -0800 (PST) From: Jagan Teki To: Maxime Ripard , Chen-Yu Tsai , David Airlie , Daniel Vetter , Rob Herring , Mark Rutland Cc: michael@amarulasolutions.com, Icenowy Zheng , linux-sunxi , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v12 3/7] drm/sun4i: dsi: Add has_mod_clk quirk Date: Tue, 3 Dec 2019 19:18:12 +0530 Message-Id: <20191203134816.5319-4-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20191203134816.5319-1-jagan@amarulasolutions.com> References: <20191203134816.5319-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=bzQVtQsv; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , As per the user manual, look like mod clock is not mandatory for all Allwinner MIPI DSI controllers, it is connected to CLK_DSI_SCLK for A31 and not available in A64. So add has_mod_clk quirk and process the mod clk accordingly. Tested-by: Merlijn Wajer Signed-off-by: Jagan Teki --- Changes for v12: - none drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 38 ++++++++++++++++++-------- drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h | 5 ++++ 2 files changed, 32 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c index c958ca9bae63..8c4c541224dd 100644 --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -1093,6 +1094,7 @@ static int sun6i_dsi_probe(struct platform_device *pdev) dsi->dev = dev; dsi->host.ops = &sun6i_dsi_host_ops; dsi->host.dev = dev; + dsi->variant = of_device_get_match_data(dev); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); base = devm_ioremap_resource(dev, res); @@ -1120,17 +1122,20 @@ static int sun6i_dsi_probe(struct platform_device *pdev) return PTR_ERR(dsi->reset); } - dsi->mod_clk = devm_clk_get(dev, "mod"); - if (IS_ERR(dsi->mod_clk)) { - dev_err(dev, "Couldn't get the DSI mod clock\n"); - return PTR_ERR(dsi->mod_clk); + if (dsi->variant->has_mod_clk) { + dsi->mod_clk = devm_clk_get(dev, "mod"); + if (IS_ERR(dsi->mod_clk)) { + dev_err(dev, "Couldn't get the DSI mod clock\n"); + return PTR_ERR(dsi->mod_clk); + } } /* * In order to operate properly, that clock seems to be always * set to 297MHz. */ - clk_set_rate_exclusive(dsi->mod_clk, 297000000); + if (dsi->variant->has_mod_clk) + clk_set_rate_exclusive(dsi->mod_clk, 297000000); dsi->dphy = devm_phy_get(dev, "dphy"); if (IS_ERR(dsi->dphy)) { @@ -1160,7 +1165,8 @@ static int sun6i_dsi_probe(struct platform_device *pdev) err_pm_disable: pm_runtime_disable(dev); err_unprotect_clk: - clk_rate_exclusive_put(dsi->mod_clk); + if (dsi->variant->has_mod_clk) + clk_rate_exclusive_put(dsi->mod_clk); return ret; } @@ -1172,7 +1178,8 @@ static int sun6i_dsi_remove(struct platform_device *pdev) component_del(&pdev->dev, &sun6i_dsi_ops); mipi_dsi_host_unregister(&dsi->host); pm_runtime_disable(dev); - clk_rate_exclusive_put(dsi->mod_clk); + if (dsi->variant->has_mod_clk) + clk_rate_exclusive_put(dsi->mod_clk); return 0; } @@ -1189,7 +1196,8 @@ static int __maybe_unused sun6i_dsi_runtime_resume(struct device *dev) } reset_control_deassert(dsi->reset); - clk_prepare_enable(dsi->mod_clk); + if (dsi->variant->has_mod_clk) + clk_prepare_enable(dsi->mod_clk); /* * Enable the DSI block. @@ -1217,7 +1225,8 @@ static int __maybe_unused sun6i_dsi_runtime_suspend(struct device *dev) { struct sun6i_dsi *dsi = dev_get_drvdata(dev); - clk_disable_unprepare(dsi->mod_clk); + if (dsi->variant->has_mod_clk) + clk_disable_unprepare(dsi->mod_clk); reset_control_assert(dsi->reset); regulator_disable(dsi->regulator); @@ -1230,9 +1239,16 @@ static const struct dev_pm_ops sun6i_dsi_pm_ops = { NULL) }; +static const struct sun6i_dsi_variant sun6i_a31_mipi_dsi = { + .has_mod_clk = true, +}; + static const struct of_device_id sun6i_dsi_of_table[] = { - { .compatible = "allwinner,sun6i-a31-mipi-dsi" }, - { } + { + .compatible = "allwinner,sun6i-a31-mipi-dsi", + .data = &sun6i_a31_mipi_dsi, + }, + { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, sun6i_dsi_of_table); diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h index 3f4846f581ef..d791c9f6fccf 100644 --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h @@ -15,6 +15,10 @@ #define SUN6I_DSI_TCON_DIV 4 +struct sun6i_dsi_variant { + bool has_mod_clk; +}; + struct sun6i_dsi { struct drm_connector connector; struct drm_encoder encoder; @@ -31,6 +35,7 @@ struct sun6i_dsi { struct sun4i_drv *drv; struct mipi_dsi_device *device; struct drm_panel *panel; + const struct sun6i_dsi_variant *variant; }; static inline struct sun6i_dsi *host_to_sun6i_dsi(struct mipi_dsi_host *host) From patchwork Tue Dec 3 13:48:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 918 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pj1-f69.google.com (mail-pj1-f69.google.com [209.85.216.69]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id A9A393F0CC for ; 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[209.85.220.65]) by mx.google.com with SMTPS id x12sor2629914pgt.80.2019.12.03.05.48.50 for (Google Transport Security); Tue, 03 Dec 2019 05:48:50 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a63:4466:: with SMTP id t38mr5499310pgk.316.1575380930403; Tue, 03 Dec 2019 05:48:50 -0800 (PST) Received: from localhost.localdomain ([115.97.190.29]) by smtp.gmail.com with ESMTPSA id y144sm4397892pfb.188.2019.12.03.05.48.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2019 05:48:49 -0800 (PST) From: Jagan Teki To: Maxime Ripard , Chen-Yu Tsai , David Airlie , Daniel Vetter , Rob Herring , Mark Rutland Cc: michael@amarulasolutions.com, Icenowy Zheng , linux-sunxi , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v12 4/7] drm/sun4i: dsi: Handle bus clock via regmap_mmio_attach_clk Date: Tue, 3 Dec 2019 19:18:13 +0530 Message-Id: <20191203134816.5319-5-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20191203134816.5319-1-jagan@amarulasolutions.com> References: <20191203134816.5319-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=dljMBjZT; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , regmap has special API to enable the controller bus clock while initializing register space, and current driver is using devm_regmap_init_mmio_clk which require to specify bus clk_id argument as "bus" But, the usage of clocks are varies between different Allwinner DSI controllers. Clocking in A33 would need bus and mod clocks where as A64 would need only bus clock. Since A64 support only single bus clock, it is optional to specify the clock-names on the controller device tree node. So using NULL on clk_id would get the attached clock. To support clk_id as "bus" and "NULL" during clock enablement between controllers, this patch add generic code to handle the bus clock using regmap_mmio_attach_clk with associated regmap APIs. Signed-off-by: Jagan Teki --- Changes for v12: - get bus clock only when mod clock present - use regmap_mmio_attach_clk drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 43 +++++++++++++++++++++----- 1 file changed, 35 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c index 8c4c541224dd..6085ad2eafc3 100644 --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c @@ -1082,6 +1082,7 @@ static const struct component_ops sun6i_dsi_ops = { static int sun6i_dsi_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + const char *clk_name = NULL; struct sun6i_dsi *dsi; struct resource *res; void __iomem *base; @@ -1095,6 +1096,8 @@ static int sun6i_dsi_probe(struct platform_device *pdev) dsi->host.ops = &sun6i_dsi_host_ops; dsi->host.dev = dev; dsi->variant = of_device_get_match_data(dev); + if (dsi->variant->has_mod_clk) + clk_name = "bus"; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); base = devm_ioremap_resource(dev, res); @@ -1109,24 +1112,35 @@ static int sun6i_dsi_probe(struct platform_device *pdev) return PTR_ERR(dsi->regulator); } - dsi->regs = devm_regmap_init_mmio_clk(dev, "bus", base, - &sun6i_dsi_regmap_config); - if (IS_ERR(dsi->regs)) { - dev_err(dev, "Couldn't create the DSI encoder regmap\n"); - return PTR_ERR(dsi->regs); - } - dsi->reset = devm_reset_control_get_shared(dev, NULL); if (IS_ERR(dsi->reset)) { dev_err(dev, "Couldn't get our reset line\n"); return PTR_ERR(dsi->reset); } + dsi->regs = devm_regmap_init_mmio(dev, base, &sun6i_dsi_regmap_config); + if (IS_ERR(dsi->regs)) { + dev_err(dev, "Couldn't init regmap\n"); + return PTR_ERR(dsi->regs); + } + + dsi->bus_clk = devm_clk_get(dev, clk_name); + if (IS_ERR(dsi->bus_clk)) { + dev_err(dev, "Couldn't get the DSI bus clock\n"); + ret = PTR_ERR(dsi->bus_clk); + goto err_regmap; + } else { + ret = regmap_mmio_attach_clk(dsi->regs, dsi->bus_clk); + if (ret) + goto err_bus_clk; + } + if (dsi->variant->has_mod_clk) { dsi->mod_clk = devm_clk_get(dev, "mod"); if (IS_ERR(dsi->mod_clk)) { dev_err(dev, "Couldn't get the DSI mod clock\n"); - return PTR_ERR(dsi->mod_clk); + ret = PTR_ERR(dsi->mod_clk); + goto err_attach_clk; } } @@ -1167,6 +1181,14 @@ static int sun6i_dsi_probe(struct platform_device *pdev) err_unprotect_clk: if (dsi->variant->has_mod_clk) clk_rate_exclusive_put(dsi->mod_clk); +err_attach_clk: + if (!IS_ERR(dsi->bus_clk)) + regmap_mmio_detach_clk(dsi->regs); +err_bus_clk: + if (!IS_ERR(dsi->bus_clk)) + clk_put(dsi->bus_clk); +err_regmap: + regmap_exit(dsi->regs); return ret; } @@ -1181,6 +1203,11 @@ static int sun6i_dsi_remove(struct platform_device *pdev) if (dsi->variant->has_mod_clk) clk_rate_exclusive_put(dsi->mod_clk); + if (!IS_ERR(dsi->bus_clk)) + regmap_mmio_detach_clk(dsi->regs); + + regmap_exit(dsi->regs); + return 0; } From patchwork Tue Dec 3 13:48:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 919 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pl1-f198.google.com (mail-pl1-f198.google.com [209.85.214.198]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id C06D83F0CC for ; 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[209.85.220.65]) by mx.google.com with SMTPS id s4sor2698342pgs.13.2019.12.03.05.48.56 for (Google Transport Security); Tue, 03 Dec 2019 05:48:56 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a63:101:: with SMTP id 1mr5341092pgb.336.1575380935648; Tue, 03 Dec 2019 05:48:55 -0800 (PST) Received: from localhost.localdomain ([115.97.190.29]) by smtp.gmail.com with ESMTPSA id y144sm4397892pfb.188.2019.12.03.05.48.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2019 05:48:55 -0800 (PST) From: Jagan Teki To: Maxime Ripard , Chen-Yu Tsai , David Airlie , Daniel Vetter , Rob Herring , Mark Rutland Cc: michael@amarulasolutions.com, Icenowy Zheng , linux-sunxi , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v12 5/7] drm/sun4i: dsi: Add Allwinner A64 MIPI DSI support Date: Tue, 3 Dec 2019 19:18:14 +0530 Message-Id: <20191203134816.5319-6-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20191203134816.5319-1-jagan@amarulasolutions.com> References: <20191203134816.5319-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=P61OjPv9; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The MIPI DSI controller in Allwinner A64 is similar to A33. But unlike A33, A64 doesn't have DSI_SCLK gating so add compatible for Allwinner A64 with uninitialized has_mod_clk driver. Signed-off-by: Jagan Teki Tested-by: Merlijn Wajer --- Changes for v12: - none drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c index 6085ad2eafc3..34a64473dd09 100644 --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c @@ -1270,11 +1270,18 @@ static const struct sun6i_dsi_variant sun6i_a31_mipi_dsi = { .has_mod_clk = true, }; +static const struct sun6i_dsi_variant sun50i_a64_mipi_dsi = { +}; + static const struct of_device_id sun6i_dsi_of_table[] = { { .compatible = "allwinner,sun6i-a31-mipi-dsi", .data = &sun6i_a31_mipi_dsi, }, + { + .compatible = "allwinner,sun50i-a64-mipi-dsi", + .data = &sun50i_a64_mipi_dsi, + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, sun6i_dsi_of_table); From patchwork Tue Dec 3 13:48:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 920 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pj1-f70.google.com (mail-pj1-f70.google.com [209.85.216.70]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 85CDD3F0CC for ; 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[209.85.220.65]) by mx.google.com with SMTPS id v11sor2657929pgr.34.2019.12.03.05.49.00 for (Google Transport Security); Tue, 03 Dec 2019 05:49:00 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a63:c849:: with SMTP id l9mr5543294pgi.330.1575380940429; Tue, 03 Dec 2019 05:49:00 -0800 (PST) Received: from localhost.localdomain ([115.97.190.29]) by smtp.gmail.com with ESMTPSA id y144sm4397892pfb.188.2019.12.03.05.48.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2019 05:48:59 -0800 (PST) From: Jagan Teki To: Maxime Ripard , Chen-Yu Tsai , David Airlie , Daniel Vetter , Rob Herring , Mark Rutland Cc: michael@amarulasolutions.com, Icenowy Zheng , linux-sunxi , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v12 6/7] arm64: dts: allwinner: a64: Add MIPI DSI pipeline Date: Tue, 3 Dec 2019 19:18:15 +0530 Message-Id: <20191203134816.5319-7-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20191203134816.5319-1-jagan@amarulasolutions.com> References: <20191203134816.5319-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=N5hZ67OM; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add MIPI DSI pipeline for Allwinner A64. - dsi node, with A64 compatible since it doesn't support DSI_SCLK gating unlike A33 - dphy node, with A64 compatible with A33 fallback since DPHY on A64 and A33 is similar - finally, attach the dsi_in to tcon0 for complete MIPI DSI Signed-off-by: Jagan Teki Tested-by: Merlijn Wajer --- Changes for v12: - none arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 27e48234f1c2..1db8378f59a4 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -382,6 +382,12 @@ #address-cells = <1>; #size-cells = <0>; reg = <1>; + + tcon0_out_dsi: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi_in_tcon0>; + allwinner,tcon-channel = <1>; + }; }; }; }; @@ -1014,6 +1020,37 @@ status = "disabled"; }; + dsi: dsi@1ca0000 { + compatible = "allwinner,sun50i-a64-mipi-dsi"; + reg = <0x01ca0000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_MIPI_DSI>; + resets = <&ccu RST_BUS_MIPI_DSI>; + phys = <&dphy>; + phy-names = "dphy"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + + port { + dsi_in_tcon0: endpoint { + remote-endpoint = <&tcon0_out_dsi>; + }; + }; + }; + + dphy: d-phy@1ca1000 { + compatible = "allwinner,sun50i-a64-mipi-dphy", + "allwinner,sun6i-a31-mipi-dphy"; + reg = <0x01ca1000 0x1000>; + clocks = <&ccu CLK_BUS_MIPI_DSI>, + <&ccu CLK_DSI_DPHY>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_MIPI_DSI>; + status = "disabled"; + #phy-cells = <0>; + }; + hdmi: hdmi@1ee0000 { compatible = "allwinner,sun50i-a64-dw-hdmi", "allwinner,sun8i-a83t-dw-hdmi"; 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[209.85.220.65]) by mx.google.com with SMTPS id n21sor3561523plp.19.2019.12.03.05.49.06 for (Google Transport Security); Tue, 03 Dec 2019 05:49:06 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:902:760c:: with SMTP id k12mr4928882pll.33.1575380946137; Tue, 03 Dec 2019 05:49:06 -0800 (PST) Received: from localhost.localdomain ([115.97.190.29]) by smtp.gmail.com with ESMTPSA id y144sm4397892pfb.188.2019.12.03.05.49.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2019 05:49:05 -0800 (PST) From: Jagan Teki To: Maxime Ripard , Chen-Yu Tsai , David Airlie , Daniel Vetter , Rob Herring , Mark Rutland Cc: michael@amarulasolutions.com, Icenowy Zheng , linux-sunxi , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [DO NOT MERGE] [PATCH v12 7/7] arm64: dts: allwinner: bananapi-m64: Enable Bananapi S070WV20-CT16 DSI panel Date: Tue, 3 Dec 2019 19:18:16 +0530 Message-Id: <20191203134816.5319-8-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20191203134816.5319-1-jagan@amarulasolutions.com> References: <20191203134816.5319-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=YCejDFsz; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This patch add support for Bananapi S070WV20-CT16 DSI panel to BPI-M64 board. DSI panel connected via board DSI port with, - DLDO1 as VCC-DSI supply - DCDC1 as VDD supply - PD7 gpio for lcd enable pin - PD6 gpio for lcd reset pin - PD5 gpio for backlight enable pin Signed-off-by: Jagan Teki --- Changes for v12: - none .../dts/allwinner/sun50i-a64-bananapi-m64.dts | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts index 208373efee49..6beaecdd802a 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts @@ -45,6 +45,7 @@ #include "sun50i-a64.dtsi" #include +#include / { model = "BananaPi-M64"; @@ -56,6 +57,14 @@ serial1 = &uart1; }; + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&r_pwm 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <1 2 4 8 16 32 64 128 255>; + default-brightness-level = <2>; + enable-gpios = <&pio 3 5 GPIO_ACTIVE_HIGH>; /* LCD-BL-EN: PD5 */ + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -116,6 +125,24 @@ status = "okay"; }; +&dphy { + status = "okay"; +}; + +&dsi { + vcc-dsi-supply = <®_dldo1>; /* VCC3V3-DSI */ + status = "okay"; + + panel@0 { + compatible = "bananapi,s070wv20-ct16-icn6211"; + reg = <0>; + enable-gpios = <&pio 3 7 GPIO_ACTIVE_HIGH>; /* LCD-PWR-EN: PD7 */ + reset-gpios = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* LCD-RST: PD6 */ + vdd-supply = <®_dcdc1>; + backlight = <&backlight>; + }; +}; + &ehci0 { status = "okay"; }; @@ -206,6 +233,10 @@ status = "okay"; }; +&r_pwm { + status = "okay"; +}; + &r_rsb { status = "okay";