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[209.85.220.65]) by mx.google.com with SMTPS id 5sor49265176pfb.67.2019.12.31.05.05.47 for (Google Transport Security); Tue, 31 Dec 2019 05:05:47 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a62:a21e:: with SMTP id m30mr67506229pff.56.1577797546877; Tue, 31 Dec 2019 05:05:46 -0800 (PST) Received: from localhost.localdomain ([49.206.202.115]) by smtp.gmail.com with ESMTPSA id i3sm55204089pfg.94.2019.12.31.05.05.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Dec 2019 05:05:46 -0800 (PST) From: Jagan Teki To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: David Airlie , Daniel Vetter , Mark Rutland , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-sunxi , linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v3 1/9] dt-bindings: display: Add TCON LCD compatible for R40 Date: Tue, 31 Dec 2019 18:35:20 +0530 Message-Id: <20191231130528.20669-2-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20191231130528.20669-1-jagan@amarulasolutions.com> References: <20191231130528.20669-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=Z9lmykbL; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Like TCON TV0, TV1 allwinner R40 has TCON LCD0, LCD1 which are managed via TCON TOP. Add tcon lcd compatible R40, the same compatible can handle TCON LCD0, LCD1. Signed-off-by: Jagan Teki Acked-by: Chen-Yu Tsai Reviewed-by: Rob Herring --- Changes for v3: - none Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt index 31ab72cba3d4..9e9c7f934202 100644 --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt @@ -160,6 +160,7 @@ Required properties: * allwinner,sun8i-a33-tcon * allwinner,sun8i-a83t-tcon-lcd * allwinner,sun8i-a83t-tcon-tv + * allwinner,sun8i-r40-tcon-lcd * allwinner,sun8i-r40-tcon-tv * allwinner,sun8i-v3s-tcon * allwinner,sun9i-a80-tcon-lcd From patchwork Tue Dec 31 13:05:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 987 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pf1-f199.google.com (mail-pf1-f199.google.com [209.85.210.199]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 59D863F077 for ; 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[209.85.220.65]) by mx.google.com with SMTPS id t185sor48410892pfc.54.2019.12.31.05.05.52 for (Google Transport Security); Tue, 31 Dec 2019 05:05:52 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a62:ddd0:: with SMTP id w199mr75715315pff.1.1577797552360; Tue, 31 Dec 2019 05:05:52 -0800 (PST) Received: from localhost.localdomain ([49.206.202.115]) by smtp.gmail.com with ESMTPSA id i3sm55204089pfg.94.2019.12.31.05.05.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Dec 2019 05:05:51 -0800 (PST) From: Jagan Teki To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: David Airlie , Daniel Vetter , Mark Rutland , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-sunxi , linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v3 2/9] drm/sun4i: tcon: Add TCON LCD support for R40 Date: Tue, 31 Dec 2019 18:35:21 +0530 Message-Id: <20191231130528.20669-3-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20191231130528.20669-1-jagan@amarulasolutions.com> References: <20191231130528.20669-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=C1XNMIIr; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , TCON LCD0, LCD1 in allwinner R40, are used for managing LCD interfaces like RGB, LVDS and DSI. Like TCON TV0, TV1 these LCD0, LCD1 are also managed via tcon top. Add support for it, in tcon driver. Signed-off-by: Jagan Teki --- Changes for v3: - none drivers/gpu/drm/sun4i/sun4i_tcon.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c index fad72799b8df..69611d38c844 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -1470,6 +1470,13 @@ static const struct sun4i_tcon_quirks sun8i_a83t_tv_quirks = { .has_channel_1 = true, }; +static const struct sun4i_tcon_quirks sun8i_r40_lcd_quirks = { + .supports_lvds = true, + .has_channel_0 = true, + /* TODO Need to support TCON output muxing via GPIO pins */ + .set_mux = sun8i_r40_tcon_tv_set_mux, +}; + static const struct sun4i_tcon_quirks sun8i_r40_tv_quirks = { .has_channel_1 = true, .set_mux = sun8i_r40_tcon_tv_set_mux, @@ -1500,6 +1507,7 @@ const struct of_device_id sun4i_tcon_of_table[] = { { .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks }, { .compatible = "allwinner,sun8i-a83t-tcon-lcd", .data = &sun8i_a83t_lcd_quirks }, { .compatible = "allwinner,sun8i-a83t-tcon-tv", .data = &sun8i_a83t_tv_quirks }, + { .compatible = "allwinner,sun8i-r40-tcon-lcd", .data = &sun8i_r40_lcd_quirks }, { .compatible = "allwinner,sun8i-r40-tcon-tv", .data = &sun8i_r40_tv_quirks }, { .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks }, { .compatible = "allwinner,sun9i-a80-tcon-lcd", .data = &sun9i_a80_tcon_lcd_quirks }, From patchwork Tue Dec 31 13:05:22 2019 Content-Type: text/plain; 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[209.85.220.65]) by mx.google.com with SMTPS id t21sor48754318plo.57.2019.12.31.05.05.57 for (Google Transport Security); Tue, 31 Dec 2019 05:05:57 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:902:b611:: with SMTP id b17mr74759458pls.210.1577797557554; Tue, 31 Dec 2019 05:05:57 -0800 (PST) Received: from localhost.localdomain ([49.206.202.115]) by smtp.gmail.com with ESMTPSA id i3sm55204089pfg.94.2019.12.31.05.05.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Dec 2019 05:05:57 -0800 (PST) From: Jagan Teki To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: David Airlie , Daniel Vetter , Mark Rutland , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-sunxi , linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v3 3/9] ARM: dts: sun8i: r40: Use tcon top clock index macros Date: Tue, 31 Dec 2019 18:35:22 +0530 Message-Id: <20191231130528.20669-4-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20191231130528.20669-1-jagan@amarulasolutions.com> References: <20191231130528.20669-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=U1gmKyx8; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , tcon_tv0, tcon_tv1 nodes have a clock names of tcon-ch0, tcon-ch1 which are referring tcon_top clocks via index numbers like 0, 1 with CLK_TCON_TV0 and CLK_TCON_TV1 respectively. Use the macro in place of index numbers, for more code readability. Signed-off-by: Jagan Teki Reviewed-by: Chen-Yu Tsai --- Changes for v3: - none arch/arm/boot/dts/sun8i-r40.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index c9c2688db66d..3faa35d43afa 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -44,6 +44,7 @@ #include #include #include +#include #include #include @@ -709,7 +710,7 @@ compatible = "allwinner,sun8i-r40-tcon-tv"; reg = <0x01c73000 0x1000>; interrupts = ; - clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>; + clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top CLK_TCON_TOP_TV0>; clock-names = "ahb", "tcon-ch1"; resets = <&ccu RST_BUS_TCON_TV0>; reset-names = "lcd"; @@ -752,7 +753,7 @@ compatible = "allwinner,sun8i-r40-tcon-tv"; reg = <0x01c74000 0x1000>; interrupts = ; - clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top 1>; + clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top CLK_TCON_TOP_TV1>; clock-names = "ahb", "tcon-ch1"; resets = <&ccu RST_BUS_TCON_TV1>; reset-names = "lcd"; From patchwork Tue Dec 31 13:05:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 989 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pj1-f71.google.com (mail-pj1-f71.google.com [209.85.216.71]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id A66EF3F077 for ; Tue, 31 Dec 2019 14:06:04 +0100 (CET) Received: by mail-pj1-f71.google.com with SMTP id ie20sf1443558pjb.8 for ; Tue, 31 Dec 2019 05:06:04 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1577797563; cv=pass; d=google.com; s=arc-20160816; b=FPk9Ph4jwjvegxbq/g+IiF+Q3Eq2LDFHQDed3H0a2cuLlIOiq3a1pPpP5GUdq72Awe rMkaThryNq96eh3LTcpqheaQYYLUJVvXG2r3hVACzqgCoAx7BkgsDPNTCGWgXLH2+Gas D/AkYRZ85BTwpEelIVboZ94bnj36WJftR+fCgqqe62PtXIKFfD7jtTcD830FC1HQsVWa fl8Z/IOTMD2nQ3hVxQiIsZcD9JLxMDbIFLfQdS39gq0yBVXiFZzk+y5m3rxROMU1drHy ZJGOG8sDW9OkUSmeEGVj/Hw9XXmxt1WyE5jJAqAbvDNJhYjXJ8CTCKFF424FOq9E8JxA tPHA== ARC-Message-Signature: i=2; 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[209.85.220.65]) by mx.google.com with SMTPS id d24sor25036795pls.45.2019.12.31.05.06.02 for (Google Transport Security); Tue, 31 Dec 2019 05:06:02 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:902:b104:: with SMTP id q4mr64632455plr.132.1577797562596; Tue, 31 Dec 2019 05:06:02 -0800 (PST) Received: from localhost.localdomain ([49.206.202.115]) by smtp.gmail.com with ESMTPSA id i3sm55204089pfg.94.2019.12.31.05.05.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Dec 2019 05:06:02 -0800 (PST) From: Jagan Teki To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: David Airlie , Daniel Vetter , Mark Rutland , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-sunxi , linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v3 4/9] drm/sun4i: tcon_top: Use clock name index macros Date: Tue, 31 Dec 2019 18:35:23 +0530 Message-Id: <20191231130528.20669-5-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20191231130528.20669-1-jagan@amarulasolutions.com> References: <20191231130528.20669-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=UH2yrbjY; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , TCON TOP mux blocks in R40 are registering clock using tcon top clock index numbers. Right now the code is using, real numbers start with 0, but we have proper macros that defined these name index numbers. Use the existing macros, instead of real numbers for more code readability. Signed-off-by: Jagan Teki --- Changes for v3: - none drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c index 75d8e60c149d..e0b3c5330b9a 100644 --- a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c +++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c @@ -194,19 +194,22 @@ static int sun8i_tcon_top_bind(struct device *dev, struct device *master, clk_data->hws[CLK_TCON_TOP_TV0] = sun8i_tcon_top_register_gate(dev, "tcon-tv0", regs, &tcon_top->reg_lock, - TCON_TOP_TCON_TV0_GATE, 0); + TCON_TOP_TCON_TV0_GATE, + CLK_TCON_TOP_TV0); if (quirks->has_tcon_tv1) clk_data->hws[CLK_TCON_TOP_TV1] = sun8i_tcon_top_register_gate(dev, "tcon-tv1", regs, &tcon_top->reg_lock, - TCON_TOP_TCON_TV1_GATE, 1); + TCON_TOP_TCON_TV1_GATE, + CLK_TCON_TOP_TV1); if (quirks->has_dsi) clk_data->hws[CLK_TCON_TOP_DSI] = sun8i_tcon_top_register_gate(dev, "dsi", regs, &tcon_top->reg_lock, - TCON_TOP_TCON_DSI_GATE, 2); + TCON_TOP_TCON_DSI_GATE, + CLK_TCON_TOP_DSI); for (i = 0; i < CLK_NUM; i++) if (IS_ERR(clk_data->hws[i])) { From patchwork Tue Dec 31 13:05:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 990 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pf1-f200.google.com (mail-pf1-f200.google.com [209.85.210.200]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 7478E3F077 for ; Tue, 31 Dec 2019 14:06:09 +0100 (CET) Received: by mail-pf1-f200.google.com with SMTP id d127sf17770229pfa.7 for ; Tue, 31 Dec 2019 05:06:09 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1577797568; cv=pass; d=google.com; s=arc-20160816; b=hVt6SJHvgMrPQLT/jXeVluTjvghNnDBphanvLsmi9OeEpAnLP6XNV5aBIZYCt8Q2pm 2PAoMJe+QMS49o0fysgQpS9slIUbrKnhpmTOH3rs3TKCu9TZmfFaR1WTsMRGjsPXdlBO LrQBZSOKOI92WKOv9Rhbjy/yIMqgConD4rFC/qqcCDEGEKsC2OIXKm73g7Jh3vK8Qx8x o87jtXC6JeeoTXCpkZ2RNT2B41UBVMhmvCrqfaHOQH2OwztzeABUCpZ+a3Ovwnmz8xym +u+55+2iMOhCo8PjeshicjE33CIiQZ3qGYdu8SibJdjBZG1wuYLvbIQYsJDMtGeHGc6V vhUQ== ARC-Message-Signature: i=2; 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[209.85.220.65]) by mx.google.com with SMTPS id e28sor49379356pgn.38.2019.12.31.05.06.07 for (Google Transport Security); Tue, 31 Dec 2019 05:06:07 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a63:d00f:: with SMTP id z15mr77454505pgf.143.1577797567531; Tue, 31 Dec 2019 05:06:07 -0800 (PST) Received: from localhost.localdomain ([49.206.202.115]) by smtp.gmail.com with ESMTPSA id i3sm55204089pfg.94.2019.12.31.05.06.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Dec 2019 05:06:06 -0800 (PST) From: Jagan Teki To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: David Airlie , Daniel Vetter , Mark Rutland , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-sunxi , linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v3 5/9] drm/sun4i: tcon_top: Register reset, clock gates in probe Date: Tue, 31 Dec 2019 18:35:24 +0530 Message-Id: <20191231130528.20669-6-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20191231130528.20669-1-jagan@amarulasolutions.com> References: <20191231130528.20669-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=DZP420mW; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , TCON TOP is processing clock gates and reset control for TV0, TV1 and DSI channels during bind and release the same during unbind component ops. The usual DSI initialization would setup all controller clocks along with DPHY clocking during probe. Since the actual clock gates (along with DSI clock gate) are initialized during ton top bind, the DPHY is failed to get the DSI clock during that time. To solve, this circular dependency move the reset control, clock gate registration from bind to probe and release the same from unbind to remove. This eventually give a chance DPHY to initialize the DSI clock gate. Signed-off-by: Jagan Teki --- Changes for v3: - fixed comments from Chen-Yu - move reset control methods into probe drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 41 +++++++++++++------------- 1 file changed, 21 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c index e0b3c5330b9a..732ac19b4371 100644 --- a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c +++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c @@ -124,7 +124,22 @@ static struct clk_hw *sun8i_tcon_top_register_gate(struct device *dev, static int sun8i_tcon_top_bind(struct device *dev, struct device *master, void *data) { - struct platform_device *pdev = to_platform_device(dev); + return 0; +} + +static void sun8i_tcon_top_unbind(struct device *dev, struct device *master, + void *data) +{ +} + +static const struct component_ops sun8i_tcon_top_ops = { + .bind = sun8i_tcon_top_bind, + .unbind = sun8i_tcon_top_unbind, +}; + +static int sun8i_tcon_top_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; struct clk_hw_onecell_data *clk_data; struct sun8i_tcon_top *tcon_top; const struct sun8i_tcon_top_quirks *quirks; @@ -132,7 +147,7 @@ static int sun8i_tcon_top_bind(struct device *dev, struct device *master, void __iomem *regs; int ret, i; - quirks = of_device_get_match_data(&pdev->dev); + quirks = of_device_get_match_data(dev); tcon_top = devm_kzalloc(dev, sizeof(*tcon_top), GFP_KERNEL); if (!tcon_top) @@ -226,22 +241,21 @@ static int sun8i_tcon_top_bind(struct device *dev, struct device *master, dev_set_drvdata(dev, tcon_top); - return 0; + return component_add(dev, &sun8i_tcon_top_ops); err_unregister_gates: for (i = 0; i < CLK_NUM; i++) if (!IS_ERR_OR_NULL(clk_data->hws[i])) clk_hw_unregister_gate(clk_data->hws[i]); - clk_disable_unprepare(tcon_top->bus); err_assert_reset: reset_control_assert(tcon_top->rst); return ret; } -static void sun8i_tcon_top_unbind(struct device *dev, struct device *master, - void *data) +static int sun8i_tcon_top_remove(struct platform_device *pdev) { + struct device *dev = &pdev->dev; struct sun8i_tcon_top *tcon_top = dev_get_drvdata(dev); struct clk_hw_onecell_data *clk_data = tcon_top->clk_data; int i; @@ -253,21 +267,8 @@ static void sun8i_tcon_top_unbind(struct device *dev, struct device *master, clk_disable_unprepare(tcon_top->bus); reset_control_assert(tcon_top->rst); -} - -static const struct component_ops sun8i_tcon_top_ops = { - .bind = sun8i_tcon_top_bind, - .unbind = sun8i_tcon_top_unbind, -}; - -static int sun8i_tcon_top_probe(struct platform_device *pdev) -{ - return component_add(&pdev->dev, &sun8i_tcon_top_ops); -} -static int sun8i_tcon_top_remove(struct platform_device *pdev) -{ - component_del(&pdev->dev, &sun8i_tcon_top_ops); + component_del(dev, &sun8i_tcon_top_ops); return 0; } From patchwork Tue Dec 31 13:05:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 991 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pf1-f199.google.com (mail-pf1-f199.google.com [209.85.210.199]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id ADC683F077 for ; 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[209.85.220.65]) by mx.google.com with SMTPS id u3sor42804217plq.53.2019.12.31.05.06.12 for (Google Transport Security); Tue, 31 Dec 2019 05:06:12 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:902:b68c:: with SMTP id c12mr40694609pls.160.1577797572591; Tue, 31 Dec 2019 05:06:12 -0800 (PST) Received: from localhost.localdomain ([49.206.202.115]) by smtp.gmail.com with ESMTPSA id i3sm55204089pfg.94.2019.12.31.05.06.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Dec 2019 05:06:12 -0800 (PST) From: Jagan Teki To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: David Airlie , Daniel Vetter , Mark Rutland , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-sunxi , linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v3 6/9] dt-bindings: sun6i-dsi: Add R40 DPHY compatible (w/ A31 fallback) Date: Tue, 31 Dec 2019 18:35:25 +0530 Message-Id: <20191231130528.20669-7-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20191231130528.20669-1-jagan@amarulasolutions.com> References: <20191231130528.20669-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=esmTNuuA; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The MIPI DSI PHY controller on Allwinner R40 is similar on the one on A31. Add R40 compatible and append A31 compatible as fallback. Signed-off-by: Jagan Teki --- Changes for v3: - update the binding in new yaml format .../devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml index 8841938050b2..0c283fe79402 100644 --- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml +++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml @@ -18,6 +18,7 @@ properties: oneOf: - const: allwinner,sun6i-a31-mipi-dphy - items: + - const: allwinner,sun8i-r40-mipi-dphy - const: allwinner,sun50i-a64-mipi-dphy - const: allwinner,sun6i-a31-mipi-dphy From patchwork Tue Dec 31 13:05:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 992 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pj1-f72.google.com (mail-pj1-f72.google.com [209.85.216.72]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id C31D83F077 for ; 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[209.85.220.65]) by mx.google.com with SMTPS id v26sor49188523pgl.41.2019.12.31.05.06.18 for (Google Transport Security); Tue, 31 Dec 2019 05:06:18 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a65:4501:: with SMTP id n1mr76072356pgq.336.1577797577740; Tue, 31 Dec 2019 05:06:17 -0800 (PST) Received: from localhost.localdomain ([49.206.202.115]) by smtp.gmail.com with ESMTPSA id i3sm55204089pfg.94.2019.12.31.05.06.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Dec 2019 05:06:17 -0800 (PST) From: Jagan Teki To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: David Airlie , Daniel Vetter , Mark Rutland , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-sunxi , linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v3 7/9] dt-bindings: sun6i-dsi: Document R40 MIPI-DSI controller (w/ A64 fallback) Date: Tue, 31 Dec 2019 18:35:26 +0530 Message-Id: <20191231130528.20669-8-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20191231130528.20669-1-jagan@amarulasolutions.com> References: <20191231130528.20669-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=MdCq41of; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The MIPI DSI controller on Allwinner R40 is similar on the one on A64 like doesn't associate any DSI_SCLK gating. So, add R40 compatible and append A64 compatible as fallback. Signed-off-by: Jagan Teki --- Changes for v3: - update the binding in new yaml format .../bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml b/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml index d41ecb5e7f7c..138ffb6ae403 100644 --- a/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml +++ b/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml @@ -15,9 +15,11 @@ properties: "#size-cells": true compatible: - enum: - - allwinner,sun6i-a31-mipi-dsi - - allwinner,sun50i-a64-mipi-dsi + oneOf: + - const: allwinner,sun6i-a31-mipi-dsi + - const: allwinner,sun50i-a64-mipi-dsi + - items: + - const: allwinner,sun8i-r40-mipi-dsi reg: maxItems: 1 From patchwork Tue Dec 31 13:05:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 993 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pg1-f199.google.com (mail-pg1-f199.google.com [209.85.215.199]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 88A393F077 for ; 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[209.85.220.65]) by mx.google.com with SMTPS id s12sor3015260pji.21.2019.12.31.05.06.22 for (Google Transport Security); Tue, 31 Dec 2019 05:06:22 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:90a:e657:: with SMTP id ep23mr5986713pjb.105.1577797582087; Tue, 31 Dec 2019 05:06:22 -0800 (PST) Received: from localhost.localdomain ([49.206.202.115]) by smtp.gmail.com with ESMTPSA id i3sm55204089pfg.94.2019.12.31.05.06.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Dec 2019 05:06:21 -0800 (PST) From: Jagan Teki To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: David Airlie , Daniel Vetter , Mark Rutland , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-sunxi , linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v3 8/9] ARM: dts: sun8i: r40: Add MIPI DSI pipeline Date: Tue, 31 Dec 2019 18:35:27 +0530 Message-Id: <20191231130528.20669-9-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20191231130528.20669-1-jagan@amarulasolutions.com> References: <20191231130528.20669-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=Xf+YTt7D; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add MIPI DSI pipeline for Allwinner R40. Unlike conventional Display pipeline in allwinner, R40 have TCON TCOP which would interact various block like muxes, tcon lcd, tcon_tv for better pipeline fitting. For MIPI DSI pipeline, we have to configure the tcon_lcd0 block which would interact with tcon_top for upper pipeline connections and dsi block for lower pipeline connections. So, this patch created that pipeline by adding new nodes for tcon_lcd0, dsi, dphy and connet them to make proper pipeline fitting. Signed-off-by: Jagan Teki --- Changes for v3: - drop clock-names in dsi node arch/arm/boot/dts/sun8i-r40.dtsi | 72 ++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index 3faa35d43afa..4c61e93d9a0b 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -628,6 +628,7 @@ tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { reg = <0>; + remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>; }; tcon_top_mixer0_out_tcon_lcd1: endpoint@1 { @@ -706,6 +707,45 @@ }; }; + tcon_lcd0: lcd-controller@1c71000 { + compatible = "allwinner,sun8i-r40-tcon-lcd"; + reg = <0x01c71000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_TCON_LCD0>, <&ccu CLK_TCON_LCD0>; + clock-names = "ahb", "tcon-ch0"; + clock-output-names = "tcon-pixel-clock"; + resets = <&ccu RST_BUS_TCON_LCD0>, <&ccu RST_BUS_LVDS>; + reset-names = "lcd", "lvds"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon_lcd0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon_lcd0_in_tcon_top_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>; + }; + }; + + tcon_lcd0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon_lcd0_out_dsi_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi_in_tcon_lcd0_out>; + }; + }; + }; + }; + tcon_tv0: lcd-controller@1c73000 { compatible = "allwinner,sun8i-r40-tcon-tv"; reg = <0x01c73000 0x1000>; @@ -803,6 +843,38 @@ interrupts = ; }; + dsi: dsi@1ca0000 { + compatible = "allwinner,sun8i-r40-mipi-dsi", + "allwinner,sun50i-a64-mipi-dsi"; + reg = <0x01ca0000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_MIPI_DSI>; + resets = <&ccu RST_BUS_MIPI_DSI>; + phys = <&dphy>; + phy-names = "dphy"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + + port { + dsi_in_tcon_lcd0_out: endpoint { + remote-endpoint = <&tcon_lcd0_out_dsi_out>; + }; + }; + }; + + dphy: d-phy@1ca1000 { + compatible = "allwinner,sun8i-r40-mipi-dphy", + "allwinner,sun6i-a31-mipi-dphy"; + reg = <0x01ca1000 0x1000>; + clocks = <&ccu CLK_BUS_MIPI_DSI>, + <&tcon_top CLK_TCON_TOP_DSI>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_MIPI_DSI>; + status = "disabled"; + #phy-cells = <0>; + }; + hdmi: hdmi@1ee0000 { compatible = "allwinner,sun8i-r40-dw-hdmi", "allwinner,sun8i-a83t-dw-hdmi"; From patchwork Tue Dec 31 13:05:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 994 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pl1-f200.google.com (mail-pl1-f200.google.com [209.85.214.200]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 4BB123F077 for ; Tue, 31 Dec 2019 14:06:29 +0100 (CET) Received: by mail-pl1-f200.google.com with SMTP id t17sf15679947ply.5 for ; Tue, 31 Dec 2019 05:06:29 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1577797588; cv=pass; d=google.com; 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[209.85.220.65]) by mx.google.com with SMTPS id 21sor49517832pgt.49.2019.12.31.05.06.27 for (Google Transport Security); Tue, 31 Dec 2019 05:06:27 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a63:1110:: with SMTP id g16mr56093805pgl.84.1577797587194; Tue, 31 Dec 2019 05:06:27 -0800 (PST) Received: from localhost.localdomain ([49.206.202.115]) by smtp.gmail.com with ESMTPSA id i3sm55204089pfg.94.2019.12.31.05.06.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Dec 2019 05:06:26 -0800 (PST) From: Jagan Teki To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: David Airlie , Daniel Vetter , Mark Rutland , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-sunxi , linux-amarula@amarulasolutions.com, Jagan Teki Subject: [DO NOT MERGE] [PATCH v3 9/9] ARM: dts: sun8i-r40: bananapi-m2-ultra: Enable Bananapi S070WV20-CT16 Date: Tue, 31 Dec 2019 18:35:28 +0530 Message-Id: <20191231130528.20669-10-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20191231130528.20669-1-jagan@amarulasolutions.com> References: <20191231130528.20669-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=rWDBjcTP; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This patch add support for Bananapi S070WV20-CT16 DSI panel to BPI-M2U board. DSI panel connected via board DSI port with, - DCDC1 as VCC-DSI supply - PH18 gpio for lcd enable pin - PD17 gpio for lcd reset pin - PD16 gpio for backlight enable pin Signed-off-by: Jagan Teki --- Changes for v3: - none .../boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts index 42d62d1ba1dc..99f84e6f15ce 100644 --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -45,6 +45,7 @@ #include "sun8i-r40.dtsi" #include +#include / { model = "Banana Pi BPI-M2-Ultra"; @@ -55,6 +56,14 @@ serial0 = &uart0; }; + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <1 2 4 8 16 32 64 128 255>; + default-brightness-level = <2>; + enable-gpios = <&pio 7 16 GPIO_ACTIVE_HIGH>; /* LCD-BL-EN: PH16 */ + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -117,6 +126,24 @@ status = "okay"; }; +&dphy { + status = "okay"; +}; + +&dsi { + vcc-dsi-supply = <®_dcdc1>; /* VCC-DSI */ + status = "okay"; + + panel@0 { + compatible = "bananapi,s070wv20-ct16-icn6211"; + reg = <0>; + enable-gpio = <&pio 7 18 GPIO_ACTIVE_HIGH>; /* LCD-PWR-EN: PH18 */ + reset-gpios = <&pio 7 17 GPIO_ACTIVE_HIGH>; /* LCD-RST: PH17 */ + vdd-supply = <®_dcdc1>; + backlight = <&backlight>; + }; +}; + &ehci1 { status = "okay"; }; @@ -209,6 +236,12 @@ vcc-pg-supply = <®_dldo1>; }; +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + status = "okay"; +}; + ®_aldo2 { regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; @@ -295,6 +328,10 @@ regulator-name = "vdd1v2-sata"; }; +&tcon_lcd0 { + status = "okay"; +}; + &tcon_tv0 { status = "okay"; };