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[93.46.124.24]) by smtp.gmail.com with ESMTPSA id u13sm6108580wmd.36.2020.01.01.08.31.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jan 2020 08:31:39 -0800 (PST) From: Michael Trimarchi To: Shawn Guo Cc: Sascha Hauer , Pengutronix Kernel Team , NXP Linux Team , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Fabio Estevam , Rob Herring , Mark Rutland , linux-amarula@amarulasolutions.com Subject: [PATCH 1/3] soc: imx: gpcv2: add support for i.MX8MM SoC Date: Wed, 1 Jan 2020 17:31:34 +0100 Message-Id: <20200101163136.1586-2-michael@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200101163136.1586-1-michael@amarulasolutions.com> References: <20200101163136.1586-1-michael@amarulasolutions.com> X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=XrhJoKJb; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The GPCv2 on the Freescale i.MX8MM SoC works in the same way as the GPCv2 on the i.MX8MQ, with a slight different mapping. Signed-off-by: Michael Trimarchi Reported-by: kbuild test robot --- .../bindings/power/fsl,imx-gpcv2.txt | 4 +- drivers/soc/imx/gpcv2.c | 110 ++++++++++++++++++ 2 files changed, 113 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt index 61649202f6f5..fde651cd06d0 100644 --- a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt +++ b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt @@ -9,6 +9,7 @@ Required properties: - compatible: Should be one of: - "fsl,imx7d-gpc" - "fsl,imx8mq-gpc" + - "fsl,imx8mm-gpc" - reg: should be register base and length as documented in the datasheet @@ -25,7 +26,8 @@ Required properties: - reg: Power domain index. Valid values are defined in include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc and - include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc + include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc and + include/dt-bindings/power/imx8mm-power.h for fsl,imx8mm-gpc - #power-domain-cells: Should be 0 diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index b0dffb06c05d..d3c012a61c11 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -16,6 +16,7 @@ #include #include #include +#include #define GPC_LPCR_A_CORE_BSC 0x000 @@ -41,6 +42,20 @@ #define IMX8M_PCIE1_A53_DOMAIN BIT(3) #define IMX8M_MIPI_A53_DOMAIN BIT(2) +#define IMX8MM_VPU_H1_A53_DOMAIN BIT(15) +#define IMX8MM_VPU_G2_A53_DOMAIN BIT(14) +#define IMX8MM_VPU_G1_A53_DOMAIN BIT(13) +#define IMX8MM_DISPMIX_A53_DOMAIN BIT(12) +#define IMX8MM_GPU_3D_A53_DOMAIN BIT(11) +#define IMX8MM_VPUMIX_A53_DOMAIN BIT(10) +#define IMX8MM_GPUMIX_A53_DOMAIN BIT(9) +#define IMX8MM_GPU_2D_A53_DOMAIN BIT(8) +#define IMX8MM_DDR1_A53_DOMAIN BIT(7) +#define IMX8MM_OTG2_A53_DOMAIN BIT(5) +#define IMX8MM_OTG1_A53_DOMAIN BIT(4) +#define IMX8MM_PCIE1_A53_DOMAIN BIT(3) +#define IMX8MM_MIPI_A53_DOMAIN BIT(2) + #define GPC_PU_PGC_SW_PUP_REQ 0x0f8 #define GPC_PU_PGC_SW_PDN_REQ 0x104 @@ -64,6 +79,20 @@ #define IMX8M_PCIE1_SW_Pxx_REQ BIT(1) #define IMX8M_MIPI_SW_Pxx_REQ BIT(0) +#define IMX8MM_VPU_H1_SW_Pxx_REQ BIT(13) +#define IMX8MN_VPU_G2_SW_Pxx_REQ BIT(12) +#define IMX8MN_VPU_G1_SW_Pxx_REQ BIT(11) +#define IMX8MM_DISPMIX_SW_Pxx_REQ BIT(10) +#define IMX8MM_GPU_3D_SW_Pxx_REQ BIT(9) +#define IMX8MM_VPUMIX_SW_Pxx_REQ BIT(8) +#define IMX8MM_GPUMIX_SW_Pxx_REQ BIT(7) +#define IMX8MM_GPU_2D_SW_Pxx_REQ BIT(6) +#define IMX8MM_DDR1_SW_Pxx_REQ BIT(5) +#define IMX8MM_OTG2_SW_Pxx_REQ BIT(3) +#define IMX8MM_OTG1_SW_Pxx_REQ BIT(2) +#define IMX8MM_PCIE1_SW_Pxx_REQ BIT(1) +#define IMX8MM_MIPI_SW_Pxx_REQ BIT(0) + #define GPC_M4_PU_PDN_FLG 0x1bc #define GPC_PU_PWRHSK 0x1fc @@ -94,6 +123,20 @@ #define IMX8M_PGC_MIPI_CSI2 28 #define IMX8M_PGC_PCIE2 29 +#define IMX8MM_PGC_MIPI 16 +#define IMX8MM_PGC_PCIE1 17 +#define IMX8MM_PGC_OTG1 18 +#define IMX8MM_PGC_OTG2 19 +#define IMX8MM_PGC_DDR1 21 +#define IMX8MM_PGC_GPU_2D 22 +#define IMX8MM_PGC_GPUMIX 17 +#define IMX8MM_PGC_VPUMIX 18 +#define IMX8MM_PGC_GPU_3D 19 +#define IMX8MM_PGC_DSPMIX 20 +#define IMX8MM_PGC_VPU_G1 21 +#define IMX8MM_PGC_VPU_G2 22 +#define IMX8MM_PGC_VPU_H1 22 + #define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40) #define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc) @@ -442,6 +485,72 @@ static const struct imx_pgc_domain_data imx8m_pgc_domain_data = { .reg_access_table = &imx8m_access_table, }; +static const struct imx_pgc_domain imx8mm_pgc_domains[] = { + [IMX8MM_POWER_DOMAIN_USB_OTG1] = { + .genpd = { + .name = "usb-otg1", + }, + .bits = { + .pxx = IMX8MM_OTG1_SW_Pxx_REQ, + .map = IMX8MM_OTG1_A53_DOMAIN, + }, + .pgc = IMX8MM_PGC_OTG1, + }, + + [IMX8MM_POWER_DOMAIN_USB_OTG2] = { + .genpd = { + .name = "usb-otg2", + }, + .bits = { + .pxx = IMX8MM_OTG2_SW_Pxx_REQ, + .map = IMX8MM_OTG2_A53_DOMAIN, + }, + .pgc = IMX8MM_PGC_OTG2, + }, +}; + +static const struct regmap_range imx8mm_yes_ranges[] = { + regmap_reg_range(GPC_LPCR_A_CORE_BSC, + GPC_PU_PWRHSK), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_MIPI), + GPC_PGC_SR(IMX8MM_PGC_MIPI)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_PCIE1), + GPC_PGC_SR(IMX8MM_PGC_PCIE1)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG1), + GPC_PGC_SR(IMX8MM_PGC_OTG1)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG2), + GPC_PGC_SR(IMX8MM_PGC_OTG2)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_DDR1), + GPC_PGC_SR(IMX8MM_PGC_DDR1)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPU_2D), + GPC_PGC_SR(IMX8MM_PGC_GPU_2D)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPUMIX), + GPC_PGC_SR(IMX8MM_PGC_GPUMIX)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUMIX), + GPC_PGC_SR(IMX8MM_PGC_VPUMIX)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPU_3D), + GPC_PGC_SR(IMX8MM_PGC_GPU_3D)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_DSPMIX), + GPC_PGC_SR(IMX8MM_PGC_DSPMIX)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPU_G1), + GPC_PGC_SR(IMX8MM_PGC_VPU_G1)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPU_G2), + GPC_PGC_SR(IMX8MM_PGC_VPU_G2)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPU_H1), + GPC_PGC_SR(IMX8MM_PGC_VPU_H1)), +}; + +static const struct regmap_access_table imx8mm_access_table = { + .yes_ranges = imx8mm_yes_ranges, + .n_yes_ranges = ARRAY_SIZE(imx8mm_yes_ranges), +}; + +static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = { + .domains = imx8mm_pgc_domains, + .domains_num = ARRAY_SIZE(imx8mm_pgc_domains), + .reg_access_table = &imx8mm_access_table, +}; + static int imx_pgc_get_clocks(struct imx_pgc_domain *domain) { int i, ret; @@ -641,6 +750,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev) static const struct of_device_id imx_gpcv2_dt_ids[] = { { .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, }, { .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, }, + { .compatible = "fsl,imx8mm-gpc", .data = &imx8mm_pgc_domain_data, }, { } }; From patchwork Wed Jan 1 16:31:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Nazzareno Trimarchi X-Patchwork-Id: 1004 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-wm1-f70.google.com (mail-wm1-f70.google.com [209.85.128.70]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id D43373F03F for ; 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[93.46.124.24]) by smtp.gmail.com with ESMTPSA id u13sm6108580wmd.36.2020.01.01.08.31.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jan 2020 08:31:40 -0800 (PST) From: Michael Trimarchi To: Shawn Guo Cc: Sascha Hauer , Pengutronix Kernel Team , NXP Linux Team , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Fabio Estevam , Rob Herring , Mark Rutland , linux-amarula@amarulasolutions.com Subject: [PATCH 2/3] irqchip/irq-imx-gpcv2: Add IRQCHIP_DECLARE for i.MX8MM compatible Date: Wed, 1 Jan 2020 17:31:35 +0100 Message-Id: <20200101163136.1586-3-michael@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200101163136.1586-1-michael@amarulasolutions.com> References: <20200101163136.1586-1-michael@amarulasolutions.com> X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=HTgpjlTE; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The GPC node on i.MX8MM can not claim to be compatible with the i.MX8MQ GPC, as the power gating part has some significant differences. Thus we can not rely on the irqchip being probed with the old compatible. Signed-off-by: Michael Trimarchi --- drivers/irqchip/irq-imx-gpcv2.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-imx-gpcv2.c index 4f74c15c4755..80855f15539c 100644 --- a/drivers/irqchip/irq-imx-gpcv2.c +++ b/drivers/irqchip/irq-imx-gpcv2.c @@ -196,6 +196,7 @@ static const struct irq_domain_ops gpcv2_irqchip_data_domain_ops = { static const struct of_device_id gpcv2_of_match[] = { { .compatible = "fsl,imx7d-gpc", .data = (const void *) 2 }, { .compatible = "fsl,imx8mq-gpc", .data = (const void *) 4 }, + { .compatible = "fsl,imx8mm-gpc", .data = (const void *) 4 }, { /* END */ } }; @@ -290,3 +291,4 @@ static int __init imx_gpcv2_irqchip_init(struct device_node *node, IRQCHIP_DECLARE(imx_gpcv2_imx7d, "fsl,imx7d-gpc", imx_gpcv2_irqchip_init); IRQCHIP_DECLARE(imx_gpcv2_imx8mq, "fsl,imx8mq-gpc", imx_gpcv2_irqchip_init); +IRQCHIP_DECLARE(imx_gpcv2_imx8mm, "fsl,imx8mm-gpc", imx_gpcv2_irqchip_init); From patchwork Wed Jan 1 16:31:36 2020 Content-Type: text/plain; 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[93.46.124.24]) by smtp.gmail.com with ESMTPSA id u13sm6108580wmd.36.2020.01.01.08.31.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jan 2020 08:31:41 -0800 (PST) From: Michael Trimarchi To: Shawn Guo Cc: Sascha Hauer , Pengutronix Kernel Team , NXP Linux Team , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Fabio Estevam , Rob Herring , Mark Rutland , linux-amarula@amarulasolutions.com Subject: [PATCH 3/3] arm64: dts: imx8mm: properly describe IRQ hierarchy Date: Wed, 1 Jan 2020 17:31:36 +0100 Message-Id: <20200101163136.1586-4-michael@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200101163136.1586-1-michael@amarulasolutions.com> References: <20200101163136.1586-1-michael@amarulasolutions.com> X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=hp+dQqpa; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The GPCv2 sits between most of the peripherals and the GIC and functions as a wakeup controller for the CPU cores. Add already two power domains. Those domains was tested on imx8mm board Signed-off-by: Michael Trimarchi Reported-by: kbuild test robot --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 31 ++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 6edbdfe2d0d7..7360dc0685eb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -12,7 +13,7 @@ #include "imx8mm-pinfunc.h" / { - interrupt-parent = <&gic>; + interrupt-parent = <&gpc>; #address-cells = <2>; #size-cells = <2>; @@ -197,6 +198,7 @@ interrupts = ; interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; + interrupt-parent = <&gic>; }; timer { @@ -206,6 +208,7 @@ , /* Virtual */ ; /* Hypervisor */ clock-frequency = <8000000>; + interrupt-parent = <&gic>; arm,no-tick-in-suspend; }; @@ -498,6 +501,29 @@ interrupts = ; #reset-cells = <1>; }; + + gpc: gpc@303a0000 { + compatible = "fsl,imx8mm-gpc"; + reg = <0x303a0000 0x10000>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <3>; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + pgc_otg1: power-domain@2 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_otg2: power-domain@3 { + #power-domain-cells = <0>; + reg = ; + }; + }; + }; }; aips2: bus@30400000 { @@ -790,6 +816,7 @@ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; fsl,usbphy = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>; + power-domains = <&pgc_otg1>; status = "disabled"; }; @@ -809,6 +836,7 @@ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; fsl,usbphy = <&usbphynop2>; fsl,usbmisc = <&usbmisc2 0>; + power-domains = <&pgc_otg2>; status = "disabled"; }; @@ -856,6 +884,7 @@ #interrupt-cells = <3>; interrupt-controller; interrupts = ; + interrupt-parent = <&gic>; }; ddr-pmu@3d800000 {