From patchwork Thu Jan 9 08:52:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1018 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pl1-f199.google.com (mail-pl1-f199.google.com [209.85.214.199]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id ADE2A3F042 for ; Thu, 9 Jan 2020 09:52:41 +0100 (CET) Received: by mail-pl1-f199.google.com with SMTP id bd7sf3132663plb.0 for ; Thu, 09 Jan 2020 00:52:41 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1578559960; cv=pass; d=google.com; s=arc-20160816; b=E5Z0twOF/j6Woh2y7bEixhQyFN9b8LG2hK04zG61yG1YByT6fDOVXF2WkIcuo1S1cn fvc4AHn4V0PU6lc8VcMcJqAgt1oX3uPgq/KapvhWfTc6w6ipqrLZARPye6O3zkO1RpWG 8OIOOv34xx7cfVUVlObDI6DGsl4/k9p+ZoBRYDKIltmIBQx/D96wlYejVECColSd6VEW mOTXuJCuBwI7RRRWQoRDtePlpkZV343qYZELukB1O5fl4UlFz2u9kSBEKJVvhDEovw+e 7Er+haxF5WoQs1sBoE10niDlwFv3LTG6gWYYdxA9AniR3v22K7R0nKuNu1Vn3ljlH+4/ cqvw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=csLN6L3otYoblqlcn2QU9+Ckw9zdH42ICDhqVGU8acw=; b=kS8mU9GJiGuX4HSK1vre2mu5MF7MrasG6Qu5JXuqxS7GoDRMCeLS07YbXQ+1EQ/e5u 82hB7xAo/2g5WkdOxxT97JKT+i0TSXY1fGhRsI6HEkOsEG2uHsmg0bXZ1emAiklKjy5q D5n2DBfDqecBUZEvp20cmWQJhreTVq7QkPesJqncUGijwvvECAVJSNbcPRZqf+8I0vb6 ekbpg5Rqhfc4798LGPnUv9AM5szdXTq2kBO5lvD9YCxFaqjQJO8LCt0ZQqe00CIzVYgb VKvQka4KheC6u1FR/6ZvHjm1vCAClt47VG3aLeFp1K49NdDwZD9+a3La6Hb1W58kOGzQ Ze6g== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=SmE1zTHi; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=csLN6L3otYoblqlcn2QU9+Ckw9zdH42ICDhqVGU8acw=; b=rLR/P4YTLceVK500OnR15GAs4CQHKUsyfrChGJruA3NolThCN7mODsGKmIuxJU6I4a zEfNpMWp3c9Ev7tpTBP7lhuSrqdYjr9Ovq0cq8lPc7aeiDX4l/s5NhPn2X6P8gnG12PD zJH39lkaVdzyhixyyz3FwcKNMbCkucJOTvtB8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=csLN6L3otYoblqlcn2QU9+Ckw9zdH42ICDhqVGU8acw=; b=X53SMhZowCKKQ+f/9u69xLHFvsfJCU0PlyoRR2bpRsAL3jRM5ISm6D1oDomwuZ+d2b RoC3lBCwF9aZfWYNl1djdFscc6c0EfN3YTbhriC1qQsKcPSOT4SKXOCnVf+h2LO7kUMw /lOn9804+Gzcnnt/oBoNwPApnEC/SrAvTD5uNxZVnOoADTG92uB7Az5CtIedvTI5cQIX 1jR1NmkZ1noYLauBRWvksx8WxSXsjOPKhQnwNmr77MTd+UPUR3vetq0wIeganR8l75BP DyvKjlDMGKfv38ELYa5vTtsphhsS9H/oZXam5yB6EgGh3kLqV1XLT0TSUqdXVy3jj6PQ jSNA== X-Gm-Message-State: APjAAAV/l3Z6UdlCSDdFp7IETS3rAy/ytUWTpEsHGtxOn9iUZb4OtYRA fNiL2Pv/LMV30GTQLV6hozUT5JJR X-Google-Smtp-Source: APXvYqzxwgkHYYgGSqxRLczAgeTb+TFMp145LMw6iGApVculk4wi68uEe/n+lWqVNk4fInQd69aISQ== X-Received: by 2002:a17:902:8f96:: with SMTP id z22mr10182722plo.11.1578559959863; Thu, 09 Jan 2020 00:52:39 -0800 (PST) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:90a:f8d:: with SMTP id 13ls462516pjz.0.gmail; Thu, 09 Jan 2020 00:52:39 -0800 (PST) X-Received: by 2002:a17:90a:cb87:: with SMTP id a7mr3946580pju.135.1578559959396; Thu, 09 Jan 2020 00:52:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1578559959; cv=none; d=google.com; s=arc-20160816; b=gLuvUV0XmlWN+pORvzi7HU3jlDbIWjCg7aWA2EEFyEresfpZvQMgOEx47od3WPsCif vQVcnAs4W2z069IyLOwg03qy9s1stKnAc+5BnRrmx4Y9mOEQ9Sxl+7VHzEbjiRIpKe0C XZdr2JF3jkYjZFHkSn1rA4soVHFIwI3AmG4DeUB5IkCnRv7SPjp3qoHDnOxLMD4xbfaS tuB3icUgOFXyxI2AhfoM39zj7QU9VRiUGGEGRMsGtbcXMKkzFiVdoJ70Efsw3Vbrg1TC gi+BE5y4+YOOxGDysThbDAARKipAodit0sCouM2iNcsXf9xEtlktiX/QMXXVTgL45QMN mS6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=30ccU2NBOUtSV7DOUopHwnFzt1mfF8Y1Cu5jsAQdzIY=; b=EPMoiDO9G83cE73fWeKKk5Dx7WddkSqabTPR5zlyjhcwthvfZFANtdslHVEKZRQYqm 0wZBPprQ9rp0oaLa1NCqdvxn5WpKXiim5yUHKwwiomDhH2MFJtPAuX1TI+MtOywU9hpL aH3YHleMgjs+jcm1UGi1YULoZwbGyZ/WQdSaJd6qaG5A0LrW/+6PTOcliXODZ/yBIfZU IjtriPHecoc+3VWsXhJHiav0zl2W1p1txtGaUmBKpf5VV0hGuyKGHdGrDaoIGg1b9mzO LSsBuf9gKLBiYRthk+g8g6fWfRpi6bgd5NaHz4SiuguQS9vWfUERzUZKRZ1x2qAXKiaB eOBw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=SmE1zTHi; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id 69sor6551758plc.8.2020.01.09.00.52.39 for (Google Transport Security); Thu, 09 Jan 2020 00:52:39 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:902:16a:: with SMTP id 97mr10266010plb.163.1578559959005; Thu, 09 Jan 2020 00:52:39 -0800 (PST) Received: from localhost.localdomain ([2405:201:c809:c7d5:d888:9871:544a:b516]) by smtp.gmail.com with ESMTPSA id o17sm2139121pjq.1.2020.01.09.00.52.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jan 2020 00:52:38 -0800 (PST) From: Jagan Teki To: Kever Yang , Simon Glass , Philipp Tomsich Cc: u-boot@lists.denx.de, linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v4 1/8] rockchip: Add cpu-info Date: Thu, 9 Jan 2020 14:22:15 +0530 Message-Id: <20200109085222.22670-2-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20200109085222.22670-1-jagan@amarulasolutions.com> References: <20200109085222.22670-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=SmE1zTHi; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add cpu information for rockchip soc. This would help to print the SoC family number, with associated temparature, clock and reason for reset etc. Reviewed-by: Kever Yang Signed-off-by: Jagan Teki --- arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/cpu-info.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+) create mode 100644 arch/arm/mach-rockchip/cpu-info.c diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index a728acda24..5b38526fe0 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -22,6 +22,7 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) # we can have the preprocessor correctly recognise both 0x0 and 0 # meaning "turn it off". obj-y += boot_mode.o +obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o obj-$(CONFIG_MISC_INIT_R) += misc.o endif diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c new file mode 100644 index 0000000000..9bccbd4f68 --- /dev/null +++ b/arch/arm/mach-rockchip/cpu-info.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * (C) Copyright 2019 Amarula Solutions(India) + * Author: Jagan Teki + */ + +#include + +int print_cpuinfo(void) +{ + printf("SoC: Rockchip %s\n", CONFIG_SYS_SOC); + + /* TODO print operating temparature and clock */ + + return 0; +} From patchwork Thu Jan 9 08:52:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1019 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pf1-f198.google.com (mail-pf1-f198.google.com [209.85.210.198]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id D08A93F042 for ; Thu, 9 Jan 2020 09:52:45 +0100 (CET) Received: by mail-pf1-f198.google.com with SMTP id 8sf3599923pfb.22 for ; Thu, 09 Jan 2020 00:52:45 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1578559964; cv=pass; d=google.com; s=arc-20160816; b=gdY+6wvFT8X1IwSyg8vsvuENCcl/Uw77MErQa/S98EDdENgSe0DBrcsjYNVQ1PeAws SPrggwA/v2wGdF3s+42DfLRQlnjldCq/DLZTDUAEBfrSdEPXl83iTZaiK/lzP19GAyzb Y9zWe+gRfDHhKUiiHnYNExaFO1lpEnl/EZInkV08F48sK4KB8vZtCQ6+T3i8j+MOZF/r xDi/VHx3R2ReaaGd5fE8WLpJ7fo4jUklhj8YcAl7i5Za2dMS+TorIJpSbY7OwgTOlY08 TQuXxM+NxVTNeNafCAh9ocX8sJalmwwL3UpGOdxbOpb0r8PYzznGjGCQJ+32LGU8mYmc ir4A== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=d4NpkkJrrMTybzNNnres4VI0Mtc0XFOkCriNgGpQ91U=; b=irdAHXAPqHGMO2jRL3ZCoS3aNFw9AyeJlNyCdFwYpQqsCgtR1Wjo6OhahsOT8vau/4 F7FkY4PiLGTtxgls8XMdVz/oqvMiLYStN5muWZAGzBOoUtUDfwq/GCpIZrdJuExUYrFp F5W/w2a8luQ5/GhvhGkJJXALriywq2badpV3TuQ5z29kn9/StkebEzt6QPnpbx4meKWz XX7zoHULzKP3jagXG4LEg9Rv8rxjIQ7SpXLIvIigDk65x4TF5dln/bqHGlQL5X7eym9s cVroIFLb+m0BIXGaNm2mPhA8rGGQGd8QEcHvNXHUSCZSIoWEd9tT/LeDX7w0134Ab+AH k/KA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=SzDhk85i; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=d4NpkkJrrMTybzNNnres4VI0Mtc0XFOkCriNgGpQ91U=; b=fTb2Q2Ydl+Dwp8i5eG6n+8PzIIAMq2O35jfDSWw1Gr2nGYR07Go9+Pw/rgo5z1nbiF GvCdbN/59u82jj2FIK7SAj80vVNw7m0c4fQmj6lMLrxeaXBm1kCBnM1cSupqCTdM8Jx+ FfthPbqaNWc2MAs1eZb2ESWMsTPrxUheQrljM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=d4NpkkJrrMTybzNNnres4VI0Mtc0XFOkCriNgGpQ91U=; b=q04iKO5vHSGsbRmIFUZLp1F2zGmWpPe1N0Io5KDVvcaFt3QBvIu5K5M4TMY/Ajs19/ W6RlpZMzts7z3bHODyH4HMc2sVG/rSXr11YuVeTO8Fur8w9fFDJG4njurVzdc715VL3H sm9M4arp1pQjV3mcieSIHZpLJFgY6ajc+BoaHQOUjUONfvbV5OqOKnqV9R1UCKDLetJN JfGhy8bXt2SNu+Uku042UstIKrilBXQ+ZvtSIDIyPgPtlQmG1tJMecI7m4hlJjap5dr6 Aen32uFhA2r41rW8yAPvmh032NpaD1p6xJYbbrKSa8P71Vn8hM8I9TdCNPvJCXHlgFUG NpXA== X-Gm-Message-State: APjAAAWwaUmdRA1cCA7ZyyIKag5PD/8MJqtJyglZPEJxcVr8cgV3ID1G 0tmjQx1e0kIjKIqS5FovqLDPD+5q X-Google-Smtp-Source: APXvYqzh1/dR/iQjyZjHtTk++7GTptW8VgifWkJV7lQp33xUy8BsPpT9teYdFzsHCcArnVh/Gx03AA== X-Received: by 2002:a63:3104:: with SMTP id x4mr9796384pgx.369.1578559964000; Thu, 09 Jan 2020 00:52:44 -0800 (PST) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a62:6483:: with SMTP id y125ls391650pfb.9.gmail; Thu, 09 Jan 2020 00:52:43 -0800 (PST) X-Received: by 2002:a62:e509:: with SMTP id n9mr9872324pff.159.1578559963508; Thu, 09 Jan 2020 00:52:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1578559963; cv=none; d=google.com; s=arc-20160816; b=PN/JhlAWwW0flDlQYaR11g3HNQpWofw7R/FxDCKsqZQ+QOUTdaR5ppG7AJ8jiCj4c/ P+JZCnvD+JyL9gU8nn8mr+VqhDBi2U7OyvcYzqc8R8l6sTqyQ4pQtkM3aeDBdpuqUO1z OvwyTN1eIKa438FI/bXhcmZjW6ySKBwj+yc/kYJObQ3l3twyacmwqs16CCU/emPyIN+i kgGJOXX9NRjsotIkdoGMMjjRiceEpMfaKiZLsdu11bgbJria5gFTQUPZHBOLTOM6R5Xx YS+b/BYl+VLl2epIWtTmFbHG3eyek7j+yWrMvukEU5fqfan4vPBHiGZ5b3yMn9gH14Qh PC+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=9fV8777BLo+lJicpi0tY+CBRa+K3xOz1i3eD6Aao/so=; b=kkvqXpjBGEhEoeEjUWXu68NzLIhYsrnf/FH0iaBC776Rpsa84PTJMz82ZUiydIhjuV kT1Sgl9f71i+WDH7MaFqneKbyoOlVaX6i8RXfyK4MjYtmXq4ylypL9gDeeIADUFwI/mV hCv9kqo0BXbAeLBq0hrCfcTfYMD4bkZF9WZhiHANByx7Hen+fZxflcePXCqo9TvOOFfk pLtBICRd5gQhm3pTcr4jZhQWVjcTRgFilc4i/uNllr8glMvD8jNkJv20Gk2LtYSX8up6 aQOxdsXwS5C0Oo7NYPRQ0zulqi/AIG9TruqqoY+/ERcE89uV+0jKG4vPyktyiF6PrQLB 2tog== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=SzDhk85i; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id q12sor6632984pgp.83.2020.01.09.00.52.43 for (Google Transport Security); Thu, 09 Jan 2020 00:52:43 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a63:941:: with SMTP id 62mr10402561pgj.203.1578559963025; Thu, 09 Jan 2020 00:52:43 -0800 (PST) Received: from localhost.localdomain ([2405:201:c809:c7d5:d888:9871:544a:b516]) by smtp.gmail.com with ESMTPSA id o17sm2139121pjq.1.2020.01.09.00.52.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jan 2020 00:52:42 -0800 (PST) From: Jagan Teki To: Kever Yang , Simon Glass , Philipp Tomsich Cc: u-boot@lists.denx.de, linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v4 2/8] rockchip: rk3399: Enable DISPLAY_CPUINFO Date: Thu, 9 Jan 2020 14:22:16 +0530 Message-Id: <20200109085222.22670-3-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20200109085222.22670-1-jagan@amarulasolutions.com> References: <20200109085222.22670-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=SzDhk85i; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , RK3288, RK3399 are now support cpu-info, so enable DISPLAY_CPUINFO by default. Reviewed-by: Kever Yang Signed-off-by: Jagan Teki --- configs/evb-rk3288_defconfig | 1 - configs/evb-rk3399_defconfig | 1 - configs/ficus-rk3399_defconfig | 1 - configs/firefly-rk3288_defconfig | 1 - configs/firefly-rk3399_defconfig | 1 - configs/khadas-edge-captain-rk3399_defconfig | 1 - configs/khadas-edge-rk3399_defconfig | 1 - configs/khadas-edge-v-rk3399_defconfig | 1 - configs/leez-rk3399_defconfig | 1 - configs/miqi-rk3288_defconfig | 1 - configs/nanopc-t4-rk3399_defconfig | 1 - configs/nanopi-m4-rk3399_defconfig | 1 - configs/nanopi-neo4-rk3399_defconfig | 1 - configs/orangepi-rk3399_defconfig | 1 - configs/phycore-rk3288_defconfig | 1 - configs/popmetal-rk3288_defconfig | 1 - configs/puma-rk3399_defconfig | 1 - configs/roc-pc-rk3399_defconfig | 1 - configs/rock-pi-4-rk3399_defconfig | 1 - configs/rock960-rk3399_defconfig | 1 - configs/rockpro64-rk3399_defconfig | 1 - configs/tinker-rk3288_defconfig | 1 - configs/tinker-s-rk3288_defconfig | 1 - configs/vyasa-rk3288_defconfig | 1 - 24 files changed, 24 deletions(-) diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index 1fa4054f5d..59c909e10d 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -14,7 +14,6 @@ CONFIG_DEBUG_UART=y CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_DEFAULT_FDT_FILE="rk3288-evb-rk808.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 8b8cdc5109..896a6050eb 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index 6bb030acc1..5b49fe0b7b 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_SPL_TEXT_BASE=0xff8c2000 -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 0c0a51c54f..41a6fc3edd 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -14,7 +14,6 @@ CONFIG_DEBUG_UART=y CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_DEFAULT_FDT_FILE="rk3288-firefly.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index b84d7b9ff0..5d197f5f8a 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig index c408a1a59b..379e21e28d 100644 --- a/configs/khadas-edge-captain-rk3399_defconfig +++ b/configs/khadas-edge-captain-rk3399_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-captain.dtbi" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig index 796f94f8d7..9086018cd0 100644 --- a/configs/khadas-edge-rk3399_defconfig +++ b/configs/khadas-edge-rk3399_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig index e70e1ec2e6..261d75526b 100644 --- a/configs/khadas-edge-v-rk3399_defconfig +++ b/configs/khadas-edge-v-rk3399_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-v.dtbi" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig index 3758d79a1e..1d621fc9ce 100644 --- a/configs/leez-rk3399_defconfig +++ b/configs/leez-rk3399_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-leez-p710.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index cec8e42c5e..25a808eb89 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -15,7 +15,6 @@ CONFIG_SPL_TEXT_BASE=0xff704000 CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_DEFAULT_FDT_FILE="rk3288-miqi.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig index 504346eb99..bd6d60ff6c 100644 --- a/configs/nanopc-t4-rk3399_defconfig +++ b/configs/nanopc-t4-rk3399_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopc-t4.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig index 24c8aa401b..74ede13c23 100644 --- a/configs/nanopi-m4-rk3399_defconfig +++ b/configs/nanopi-m4-rk3399_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig index 986739f16e..a44124aac0 100644 --- a/configs/nanopi-neo4-rk3399_defconfig +++ b/configs/nanopi-neo4-rk3399_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-neo4.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index bed634b699..4c464de8a6 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig index 4c48d42299..2f10c7a3b3 100644 --- a/configs/phycore-rk3288_defconfig +++ b/configs/phycore-rk3288_defconfig @@ -16,7 +16,6 @@ CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_CONSOLE_MUX=y CONFIG_DEFAULT_FDT_FILE="rk3288-phycore-rdk.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig index f732f6b209..512efee1a9 100644 --- a/configs/popmetal-rk3288_defconfig +++ b/configs/popmetal-rk3288_defconfig @@ -16,7 +16,6 @@ CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_CONSOLE_MUX=y CONFIG_DEFAULT_FDT_FILE="rk3288-popmetal.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 55255bf6af..30c7ab2751 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -16,7 +16,6 @@ CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_SPL_FIT_GENERATOR="board/theobroma-systems/puma_rk3399/fit_spl_atf.sh" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb" CONFIG_MISC_INIT_R=y -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index 305baa712c..bf83b25dbc 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index 2c01bf1f87..4429f58fde 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4.dtb" CONFIG_MISC_INIT_R=y -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index ec32e6cf05..7b6dc3f83c 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -9,7 +9,6 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 49e27c91cb..955b717131 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -10,7 +10,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb" CONFIG_MISC_INIT_R=y -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index 83c3450839..894e7d1e12 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -16,7 +16,6 @@ CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_CONSOLE_MUX=y CONFIG_DEFAULT_FDT_FILE="rk3288-tinker.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig index 4925b14821..6215aa2d61 100644 --- a/configs/tinker-s-rk3288_defconfig +++ b/configs/tinker-s-rk3288_defconfig @@ -15,7 +15,6 @@ CONFIG_DEBUG_UART=y CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_DEFAULT_FDT_FILE="rk3288-tinker-s.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x300000 diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig index 9497f0dd0f..6cb7f13e49 100644 --- a/configs/vyasa-rk3288_defconfig +++ b/configs/vyasa-rk3288_defconfig @@ -14,7 +14,6 @@ CONFIG_DEBUG_UART=y CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y CONFIG_DEFAULT_FDT_FILE="rk3288-vyasa.dtb" -# CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 From patchwork Thu Jan 9 08:52:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1020 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pj1-f72.google.com (mail-pj1-f72.google.com [209.85.216.72]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id ADFC63F042 for ; Thu, 9 Jan 2020 09:52:49 +0100 (CET) Received: by mail-pj1-f72.google.com with SMTP id u91sf1079804pjb.0 for ; Thu, 09 Jan 2020 00:52:49 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1578559968; cv=pass; d=google.com; s=arc-20160816; b=Ga95VBh/TK48y7FGI14ZDQ0fKppNyWQnXaLNj3tS1VEa3P/kLNFO/PnRb6FOG3XZBU 8tk759FTB0Uy8Ljz9RskArXNwLiPtHEdmPFb6tTtaJ3Kqav5N6sEYJpm7KAsv2xz6go8 KDQiwK+8eEz39R374jroSvZjRz9M2Orm1ikYmjNtlNXxN9XZciFTrS+2dK9Fz5ekp1Jc gqLfg/Rzg67t1vUW2Ec4e/wpkH7J46yAlH6k1eFGqYNpAOVWAbuVRkJXi7R9uYf40aFp V/UPbo9Ct9Bml9CDOOK/nf6q2BC9Rk0BScoMYNAcPnYmwIZpoN2ziXv65QQo5Og0Atyg M0WA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=JYnmgGfMYx75YqnmYq82ktsy62ykSknfWE7AHWGcJXE=; b=0jbZcOzDRRWckuExwBqXVXtQ/KS18VZrs31Svytl/daszl3V+YjBKOfI8no0C6Di63 PQ9nEM2QHBEtmLh+uyCh0oLaC9n6DqNeTPa83YTOIRiqGPApvRf2QYSH6gFLHUu4m69D ALotwRTPmTBsfiYkzd2jVMWLAzzhEWVwOf3eCnXuloTD0jrPMwLr+7kTk3CiCg5MoTIk Wg/jlbhm3dk6dMRaAOhjYHB+TGUlsGAmN0Mj7E7isAagmoymFiSoda70iSoDWkj/SDRo usYar+a2/X54iJmfC8HFnCoGdYHR8e2KzfGcjEz7HQV+7Axx4K/aFnuBG+5i5yjRGKf7 3vHg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=ZOP1wzlS; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=JYnmgGfMYx75YqnmYq82ktsy62ykSknfWE7AHWGcJXE=; b=iM8qHPZMCOv8/XR+FNr60fJ73FByq+PBzOvwIjDvrdbSuTXA2R08fr804RRzaDKqsE qZly4r18Dp7CeCqn66BdR24CeN4wDI9FtoG2jrGuUfqq+4/EETQZD4+ppkUsTttCoIPT rGuV07aQ1ia/6Ax3Vl68PqU2WC0M+nFUs9fi8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=JYnmgGfMYx75YqnmYq82ktsy62ykSknfWE7AHWGcJXE=; b=XbgUzKdD4XUhO8Hi1jjEKdsS8XVXAyQjfJf0YW4e2Pyme7EeXfVzkBWE/mSzLIjb5+ lk5fshlUlJMGoNxQh7lNQ6qnNO8Wml92Pz2ODpKV2Z+TDy0maTKuw+ZL9NymPXpuJ+GA hx2UzpYqJZ2WiBGdMamqaRQaswM9lgb83UrYd9EAXxNFH/56kK9T+X2PjDcZ03gKDZBB XhBwdvMg6nvGYWgepGZQXIX3hlSFXbZHNU7C523YdTILk/nAOCi9Bje/cnDcAkCvoRaq mazGBy/CdZyS3Wg6+1uDhJpOoN2ui4OMeD8WvAPAPXOzkdvLRDM7wvFIZqBZPadEaVje Dnkg== X-Gm-Message-State: APjAAAXBpSCjUXU5M8J5sSkrxwvB9nxbxJPKqMBq7BxagzKUHLLbvWZJ fWFdi5xvyFZqHtm5rYJI+/gikqp6 X-Google-Smtp-Source: APXvYqwT7Y979yvbPe8MBKua9pNEPvx3lpR1J/Kdhl/1YInrnAT6aANoCZ/eWKaMnsU1U7CmuD91PA== X-Received: by 2002:aa7:8f33:: with SMTP id y19mr9707155pfr.47.1578559968370; Thu, 09 Jan 2020 00:52:48 -0800 (PST) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:902:8214:: with SMTP id x20ls385902pln.15.gmail; Thu, 09 Jan 2020 00:52:48 -0800 (PST) X-Received: by 2002:a17:90a:26e1:: with SMTP id m88mr4006629pje.101.1578559967801; Thu, 09 Jan 2020 00:52:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1578559967; cv=none; d=google.com; s=arc-20160816; b=AqS+7KU72nL91xXDLIOHolD+/YfjBrE5WfYXXD81/BIABxR2VZQzznpXI3dxrs7jqC EzB6dgI7fQpBPjvd6/NEFEQ/eKmhaJNDWsI7ysiz7f1UEJ560rkLrJtYsEcg3CYb3t9l 3GjnQfl1rraxIqTeYn4Qlp1VELhQAlSNkXdxAGAZ08n4JavkLL3lMeFT0U/3N3VzdseC gv91Dtb37m+rvEUbYdGVxb94r6ERsyjwd4CP/ZH7dWwscX3A/B9y6o7429mN364ILJ4o gbBiD+B0LXwZBfh75ReVqQ7WJPHUC4Dsl3er+pTN5W40dDrKIRWOAeMC2dBL7V8QeSWl JtfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=znv8QwcHGQcOGdRNQ+C4z5hHSfQT5ovpaHPF1scKIhs=; b=gCPbmiOIAt5El+nDkP4WLXyJzxQnGfCwdNv0bGsZ7N8GKNApBxRiKJE3q6UxneBgIa rgP9qDLYkK+S0HjumlFTR0UB5gWhGPq7mPvwPYG97zrCt79WvPo+vwitmvqnHh09zT7X labE0X8kGW1+pIw5BtBxisVkUX4FzWD22TRtTnm18g1Tjvnl8FOR3Kmx+NcKwKPr+Kbb o6k5+zNqkHJzndUbnLr6Q4jsUqxdpx9xtKqtBlB4+3ZLecWXT/nb/w/9QA2snYvNQwvk 4qODiaPIIf+3xB2zWfkBRjCHk8vp5EC8jJ9XPUxG7Ygd/FeZB/f2mVSP0SueIP0iGOIH dkdg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=ZOP1wzlS; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id e28sor6709367pgn.38.2020.01.09.00.52.47 for (Google Transport Security); Thu, 09 Jan 2020 00:52:47 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a63:465b:: with SMTP id v27mr10232129pgk.257.1578559967134; Thu, 09 Jan 2020 00:52:47 -0800 (PST) Received: from localhost.localdomain ([2405:201:c809:c7d5:d888:9871:544a:b516]) by smtp.gmail.com with ESMTPSA id o17sm2139121pjq.1.2020.01.09.00.52.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jan 2020 00:52:46 -0800 (PST) From: Jagan Teki To: Kever Yang , Simon Glass , Philipp Tomsich Cc: u-boot@lists.denx.de, linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v4 3/8] arm: rockchip: Add common cru.h Date: Thu, 9 Jan 2020 14:22:17 +0530 Message-Id: <20200109085222.22670-4-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20200109085222.22670-1-jagan@amarulasolutions.com> References: <20200109085222.22670-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=ZOP1wzlS; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Few of the rockchip family SoC atleast rk3288, rk3399 are sharing some cru register bits so adding common code between these SoC families would require to include both cru include files that indeed resulting function declarations error. So, create a common cru include as cru.h then include the rk3399 arch cru include file and move the common cru register bit definitions into it. The rest of rockchip cru files will add it in future. Reviewed-by: Kever Yang Signed-off-by: Jagan Teki --- arch/arm/include/asm/arch-rockchip/clock.h | 4 +- arch/arm/include/asm/arch-rockchip/cru.h | 18 ++++++++ .../include/asm/arch-rockchip/cru_rk3288.h | 6 +-- .../include/asm/arch-rockchip/cru_rk3399.h | 11 +++-- arch/arm/mach-rockchip/rk3288/clk_rk3288.c | 2 +- arch/arm/mach-rockchip/rk3288/rk3288.c | 4 +- arch/arm/mach-rockchip/rk3399/clk_rk3399.c | 2 +- arch/arm/mach-rockchip/rk3399/rk3399.c | 2 +- drivers/clk/rockchip/clk_rk3288.c | 42 +++++++++---------- drivers/clk/rockchip/clk_rk3399.c | 36 ++++++++-------- drivers/ram/rockchip/sdram_rk3288.c | 10 ++--- drivers/ram/rockchip/sdram_rk3399.c | 10 ++--- drivers/video/rockchip/rk3288_mipi.c | 2 +- drivers/video/rockchip/rk3399_mipi.c | 2 +- drivers/video/rockchip/rk_mipi.c | 2 +- 15 files changed, 85 insertions(+), 68 deletions(-) create mode 100644 arch/arm/include/asm/arch-rockchip/cru.h diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h index 8f7fc86a9e..22de0aef8d 100644 --- a/arch/arm/include/asm/arch-rockchip/clock.h +++ b/arch/arm/include/asm/arch-rockchip/clock.h @@ -153,10 +153,10 @@ void *rockchip_get_cru(void); */ void *rockchip_get_pmucru(void); -struct rk3288_cru; +struct rockchip_cru; struct rk3288_grf; -void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf); +void rk3288_clk_configure_cpu(struct rockchip_cru *cru, struct rk3288_grf *grf); int rockchip_get_clk(struct udevice **devp); diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h new file mode 100644 index 0000000000..475d772fb6 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * (C) Copyright 2019 Amarula Solutions. + * Author: Jagan Teki + */ + +#ifndef _ROCKCHIP_CLOCK_H +#define _ROCKCHIP_CLOCK_H + +#if defined(CONFIG_ROCKCHIP_RK3288) +# include +#elif defined(CONFIG_ROCKCHIP_RK3399) +# include +#endif + +#define MHz 1000000 + +#endif /* _ROCKCHIP_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h index e891f20b37..7aa6efe46c 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h @@ -27,11 +27,11 @@ /* Private data for the clock driver - used by rockchip_get_cru() */ struct rk3288_clk_priv { struct rk3288_grf *grf; - struct rk3288_cru *cru; + struct rockchip_cru *cru; ulong rate; }; -struct rk3288_cru { +struct rockchip_cru { struct rk3288_pll { u32 con0; u32 con1; @@ -58,7 +58,7 @@ struct rk3288_cru { u32 cru_sdio1_con[2]; u32 cru_emmc_con[2]; }; -check_member(rk3288_cru, cru_emmc_con[1], 0x021c); +check_member(rockchip_cru, cru_emmc_con[1], 0x021c); /* CRU_CLKSEL11_CON */ enum { diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h index 15eeb9c440..789ca6aa28 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h @@ -10,7 +10,7 @@ /* Private data for the clock driver - used by rockchip_get_cru() */ struct rk3399_clk_priv { - struct rk3399_cru *cru; + struct rockchip_cru *cru; }; struct rk3399_pmuclk_priv { @@ -33,7 +33,7 @@ struct rk3399_pmucru { }; check_member(rk3399_pmucru, pmucru_gatedis_con[1], 0x134); -struct rk3399_cru { +struct rockchip_cru { u32 apll_l_con[6]; u32 reserved[2]; u32 apll_b_con[6]; @@ -65,8 +65,7 @@ struct rk3399_cru { u32 sdio0_con[2]; u32 sdio1_con[2]; }; -check_member(rk3399_cru, sdio1_con[1], 0x594); -#define MHz 1000000 +check_member(rockchip_cru, sdio1_con[1], 0x594); #define KHz 1000 #define OSC_HZ (24*MHz) #define LPLL_HZ (600*MHz) @@ -107,9 +106,9 @@ enum apll_b_frequencies { APLL_B_600_MHZ, }; -void rk3399_configure_cpu_l(struct rk3399_cru *cru, +void rk3399_configure_cpu_l(struct rockchip_cru *cru, enum apll_l_frequencies apll_l_freq); -void rk3399_configure_cpu_b(struct rk3399_cru *cru, +void rk3399_configure_cpu_b(struct rockchip_cru *cru, enum apll_b_frequencies apll_b_freq); #endif /* __ASM_ARCH_CRU_RK3399_H_ */ diff --git a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c index e64ee86f08..1730f12443 100644 --- a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include int rockchip_get_clk(struct udevice **devp) { diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c index 9572f7ea9c..47ee5d440b 100644 --- a/arch/arm/mach-rockchip/rk3288/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include #include @@ -104,7 +104,7 @@ void board_debug_uart_init(void) static void rk3288_detect_reset_reason(void) { - struct rk3288_cru *cru = rockchip_get_cru(); + struct rockchip_cru *cru = rockchip_get_cru(); const char *reason; if (IS_ERR(cru)) diff --git a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c index f0411c0a21..a80a46f1db 100644 --- a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include static int rockchip_get_cruclk(struct udevice **devp) { diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index 863024d071..dafa142824 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -240,7 +240,7 @@ static void rk3399_force_power_on_reset(void) void spl_board_init(void) { #if defined(SPL_GPIO_SUPPORT) - struct rk3399_cru *cru = rockchip_get_cru(); + struct rockchip_cru *cru = rockchip_get_cru(); /* * The RK3399 resets only 'almost all logic' (see also in the TRM diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index 85d1b67e43..cc1c1e81e9 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include @@ -141,7 +141,7 @@ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1); static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); -static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id, +static int rkclk_set_pll(struct rockchip_cru *cru, enum rk_clk_id clk_id, const struct pll_div *div) { int pll_id = rk_pll_id(clk_id); @@ -172,7 +172,7 @@ static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id, return 0; } -static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf, +static int rkclk_configure_ddr(struct rockchip_cru *cru, struct rk3288_grf *grf, unsigned int hz) { static const struct pll_div dpll_cfg[] = { @@ -295,7 +295,7 @@ static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div) return 0; } -static int rockchip_mac_set_clk(struct rk3288_cru *cru, uint freq) +static int rockchip_mac_set_clk(struct rockchip_cru *cru, uint freq) { ulong ret; @@ -333,7 +333,7 @@ static int rockchip_mac_set_clk(struct rk3288_cru *cru, uint freq) return ret; } -static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf, +static int rockchip_vop_set_clk(struct rockchip_cru *cru, struct rk3288_grf *grf, int periph, unsigned int rate_hz) { struct pll_div npll_config = {0}; @@ -384,7 +384,7 @@ static u32 rockchip_clk_gcd(u32 a, u32 b) return a; } -static ulong rockchip_i2s_get_clk(struct rk3288_cru *cru, uint gclk_rate) +static ulong rockchip_i2s_get_clk(struct rockchip_cru *cru, uint gclk_rate) { unsigned long long rate; uint val; @@ -400,7 +400,7 @@ static ulong rockchip_i2s_get_clk(struct rk3288_cru *cru, uint gclk_rate) return (ulong)rate; } -static ulong rockchip_i2s_set_clk(struct rk3288_cru *cru, uint gclk_rate, +static ulong rockchip_i2s_set_clk(struct rockchip_cru *cru, uint gclk_rate, uint freq) { int n, d; @@ -418,7 +418,7 @@ static ulong rockchip_i2s_set_clk(struct rk3288_cru *cru, uint gclk_rate, } #endif /* CONFIG_SPL_BUILD */ -static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) +static void rkclk_init(struct rockchip_cru *cru, struct rk3288_grf *grf) { u32 aclk_div; u32 hclk_div; @@ -492,7 +492,7 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) CPLL_MODE_NORMAL << CPLL_MODE_SHIFT); } -void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf) +void rk3288_clk_configure_cpu(struct rockchip_cru *cru, struct rk3288_grf *grf) { /* pll enter slow-mode */ rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, @@ -534,7 +534,7 @@ void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf) } /* Get pll rate by id */ -static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru, +static uint32_t rkclk_pll_get_rate(struct rockchip_cru *cru, enum rk_clk_id clk_id) { uint32_t nr, no, nf; @@ -567,7 +567,7 @@ static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru, } } -static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate, +static ulong rockchip_mmc_get_clk(struct rockchip_cru *cru, uint gclk_rate, int periph) { uint src_rate; @@ -601,7 +601,7 @@ static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate, return DIV_TO_RATE(src_rate, div); } -static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate, +static ulong rockchip_mmc_set_clk(struct rockchip_cru *cru, uint gclk_rate, int periph, uint freq) { int src_clk_div; @@ -651,7 +651,7 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate, return rockchip_mmc_get_clk(cru, gclk_rate, periph); } -static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate, +static ulong rockchip_spi_get_clk(struct rockchip_cru *cru, uint gclk_rate, int periph) { uint div, mux; @@ -681,7 +681,7 @@ static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate, return DIV_TO_RATE(gclk_rate, div); } -static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate, +static ulong rockchip_spi_set_clk(struct rockchip_cru *cru, uint gclk_rate, int periph, uint freq) { int src_clk_div; @@ -715,7 +715,7 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate, return rockchip_spi_get_clk(cru, gclk_rate, periph); } -static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru) +static ulong rockchip_saradc_get_clk(struct rockchip_cru *cru) { u32 div, val; @@ -726,7 +726,7 @@ static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru) return DIV_TO_RATE(OSC_HZ, div); } -static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz) +static ulong rockchip_saradc_set_clk(struct rockchip_cru *cru, uint hz) { int src_clk_div; @@ -785,7 +785,7 @@ static ulong rk3288_clk_get_rate(struct clk *clk) static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate) { struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); - struct rk3288_cru *cru = priv->cru; + struct rockchip_cru *cru = priv->cru; ulong new_rate, gclk_rate; gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); @@ -892,7 +892,7 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate) static int __maybe_unused rk3288_gmac_set_parent(struct clk *clk, struct clk *parent) { struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); - struct rk3288_cru *cru = priv->cru; + struct rockchip_cru *cru = priv->cru; const char *clock_output_name; int ret; @@ -1008,15 +1008,15 @@ static int rk3288_clk_bind(struct udevice *dev) debug("Warning: No sysreset driver: ret=%d\n", ret); } else { priv = malloc(sizeof(struct sysreset_reg)); - priv->glb_srst_fst_value = offsetof(struct rk3288_cru, + priv->glb_srst_fst_value = offsetof(struct rockchip_cru, cru_glb_srst_fst_value); - priv->glb_srst_snd_value = offsetof(struct rk3288_cru, + priv->glb_srst_snd_value = offsetof(struct rockchip_cru, cru_glb_srst_snd_value); sys_child->priv = priv; } #if CONFIG_IS_ENABLED(RESET_ROCKCHIP) - ret = offsetof(struct rk3288_cru, cru_softrst_con[0]); + ret = offsetof(struct rockchip_cru, cru_softrst_con[0]); ret = rockchip_reset_bind(dev, ret, 12); if (ret) debug("Warning: software reset driver bind faile\n"); diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 9020a9f202..37fc142a7a 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include @@ -418,7 +418,7 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div) return 0; } -void rk3399_configure_cpu_l(struct rk3399_cru *cru, +void rk3399_configure_cpu_l(struct rockchip_cru *cru, enum apll_l_frequencies apll_l_freq) { u32 aclkm_div; @@ -453,7 +453,7 @@ void rk3399_configure_cpu_l(struct rk3399_cru *cru, atclk_div << ATCLK_CORE_L_DIV_SHIFT); } -void rk3399_configure_cpu_b(struct rk3399_cru *cru, +void rk3399_configure_cpu_b(struct rockchip_cru *cru, enum apll_b_frequencies apll_b_freq) { u32 aclkm_div; @@ -505,7 +505,7 @@ void rk3399_configure_cpu_b(struct rk3399_cru *cru, #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \ ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT) -static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id) +static ulong rk3399_i2c_get_clk(struct rockchip_cru *cru, ulong clk_id) { u32 div, con; @@ -542,7 +542,7 @@ static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id) return DIV_TO_RATE(GPLL_HZ, div); } -static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) +static ulong rk3399_i2c_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz) { int src_clk_div; @@ -619,7 +619,7 @@ static const struct spi_clkreg spi_clkregs[] = { .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, }, }; -static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id) +static ulong rk3399_spi_get_clk(struct rockchip_cru *cru, ulong clk_id) { const struct spi_clkreg *spiclk = NULL; u32 div, val; @@ -641,7 +641,7 @@ static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id) return DIV_TO_RATE(GPLL_HZ, div); } -static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) +static ulong rk3399_spi_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz) { const struct spi_clkreg *spiclk = NULL; int src_clk_div; @@ -668,7 +668,7 @@ static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) return rk3399_spi_get_clk(cru, clk_id); } -static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz) +static ulong rk3399_vop_set_clk(struct rockchip_cru *cru, ulong clk_id, u32 hz) { struct pll_div vpll_config = {0}; int aclk_vop = 198 * MHz; @@ -712,7 +712,7 @@ static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz) return hz; } -static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id) +static ulong rk3399_mmc_get_clk(struct rockchip_cru *cru, uint clk_id) { u32 div, con; @@ -739,7 +739,7 @@ static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id) return DIV_TO_RATE(GPLL_HZ, div); } -static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru, +static ulong rk3399_mmc_set_clk(struct rockchip_cru *cru, ulong clk_id, ulong set_rate) { int src_clk_div; @@ -792,7 +792,7 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru, return rk3399_mmc_get_clk(cru, clk_id); } -static ulong rk3399_gmac_set_clk(struct rk3399_cru *cru, ulong rate) +static ulong rk3399_gmac_set_clk(struct rockchip_cru *cru, ulong rate) { ulong ret; @@ -817,7 +817,7 @@ static ulong rk3399_gmac_set_clk(struct rk3399_cru *cru, ulong rate) } #define PMUSGRF_DDR_RGN_CON16 0xff330040 -static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru, +static ulong rk3399_ddr_set_clk(struct rockchip_cru *cru, ulong set_rate) { struct pll_div dpll_cfg; @@ -863,7 +863,7 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru, return set_rate; } -static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru) +static ulong rk3399_saradc_get_clk(struct rockchip_cru *cru) { u32 div, val; @@ -874,7 +874,7 @@ static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru) return DIV_TO_RATE(OSC_HZ, div); } -static ulong rk3399_saradc_set_clk(struct rk3399_cru *cru, uint hz) +static ulong rk3399_saradc_set_clk(struct rockchip_cru *cru, uint hz) { int src_clk_div; @@ -1071,7 +1071,7 @@ static struct clk_ops rk3399_clk_ops = { }; #ifdef CONFIG_SPL_BUILD -static void rkclk_init(struct rk3399_cru *cru) +static void rkclk_init(struct rockchip_cru *cru) { u32 aclk_div; u32 hclk_div; @@ -1188,15 +1188,15 @@ static int rk3399_clk_bind(struct udevice *dev) debug("Warning: No sysreset driver: ret=%d\n", ret); } else { priv = malloc(sizeof(struct sysreset_reg)); - priv->glb_srst_fst_value = offsetof(struct rk3399_cru, + priv->glb_srst_fst_value = offsetof(struct rockchip_cru, glb_srst_fst_value); - priv->glb_srst_snd_value = offsetof(struct rk3399_cru, + priv->glb_srst_snd_value = offsetof(struct rockchip_cru, glb_srst_snd_value); sys_child->priv = priv; } #if CONFIG_IS_ENABLED(RESET_ROCKCHIP) - ret = offsetof(struct rk3399_cru, softrst_con[0]); + ret = offsetof(struct rockchip_cru, softrst_con[0]); ret = rockchip_reset_bind(dev, ret, 21); if (ret) debug("Warning: software reset driver bind faile\n"); diff --git a/drivers/ram/rockchip/sdram_rk3288.c b/drivers/ram/rockchip/sdram_rk3288.c index 690751d074..fd5b204e1f 100644 --- a/drivers/ram/rockchip/sdram_rk3288.c +++ b/drivers/ram/rockchip/sdram_rk3288.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #include #include @@ -36,7 +36,7 @@ struct dram_info { struct chan_info chan[2]; struct ram_info info; struct clk ddr_clk; - struct rk3288_cru *cru; + struct rockchip_cru *cru; struct rk3288_grf *grf; struct rk3288_sgrf *sgrf; struct rk3288_pmu *pmu; @@ -92,7 +92,7 @@ static void copy_to_reg(u32 *dest, const u32 *src, u32 n) } } -static void ddr_reset(struct rk3288_cru *cru, u32 ch, u32 ctl, u32 phy) +static void ddr_reset(struct rockchip_cru *cru, u32 ch, u32 ctl, u32 phy) { u32 phy_ctl_srstn_shift = 4 + 5 * ch; u32 ctl_psrstn_shift = 3 + 5 * ch; @@ -109,7 +109,7 @@ static void ddr_reset(struct rk3288_cru *cru, u32 ch, u32 ctl, u32 phy) phy << phy_srstn_shift); } -static void ddr_phy_ctl_reset(struct rk3288_cru *cru, u32 ch, u32 n) +static void ddr_phy_ctl_reset(struct rockchip_cru *cru, u32 ch, u32 n) { u32 phy_ctl_srstn_shift = 4 + 5 * ch; @@ -117,7 +117,7 @@ static void ddr_phy_ctl_reset(struct rk3288_cru *cru, u32 ch, u32 n) 1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift); } -static void phy_pctrl_reset(struct rk3288_cru *cru, +static void phy_pctrl_reset(struct rockchip_cru *cru, struct rk3288_ddr_publ *publ, int channel) { diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 7b2bba03fe..08bf0393a7 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include @@ -66,7 +66,7 @@ struct dram_info { u32 pwrup_srefresh_exit[2]; struct chan_info chan[2]; struct clk ddr_clk; - struct rk3399_cru *cru; + struct rockchip_cru *cru; struct rk3399_grf_regs *grf; struct rk3399_pmu_regs *pmu; struct rk3399_pmucru *pmucru; @@ -228,7 +228,7 @@ static void *get_ddrc0_con(struct dram_info *dram, u8 channel) return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc1_con0; } -static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl, +static void rkclk_ddr_reset(struct rockchip_cru *cru, u32 channel, u32 ctl, u32 phy) { channel &= 0x1; @@ -239,7 +239,7 @@ static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl, &cru->softrst_con[4]); } -static void phy_pctrl_reset(struct rk3399_cru *cru, u32 channel) +static void phy_pctrl_reset(struct rockchip_cru *cru, u32 channel) { rkclk_ddr_reset(cru, channel, 1, 1); udelay(10); @@ -2945,7 +2945,7 @@ static int sdram_init(struct dram_info *dram, for (channel = 0; channel < 2; channel++) { const struct chan_info *chan = &dram->chan[channel]; - struct rk3399_cru *cru = dram->cru; + struct rockchip_cru *cru = dram->cru; struct rk3399_ddr_publ_regs *publ = chan->publ; phy_pctrl_reset(cru, channel); diff --git a/drivers/video/rockchip/rk3288_mipi.c b/drivers/video/rockchip/rk3288_mipi.c index 7c4a4cc53b..65891ce45c 100644 --- a/drivers/video/rockchip/rk3288_mipi.c +++ b/drivers/video/rockchip/rk3288_mipi.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/video/rockchip/rk3399_mipi.c b/drivers/video/rockchip/rk3399_mipi.c index a93b73400b..a5b7ba69a8 100644 --- a/drivers/video/rockchip/rk3399_mipi.c +++ b/drivers/video/rockchip/rk3399_mipi.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c index bcd039b7bc..f9280e8607 100644 --- a/drivers/video/rockchip/rk_mipi.c +++ b/drivers/video/rockchip/rk_mipi.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include From patchwork Thu Jan 9 08:52:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1021 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pg1-f197.google.com (mail-pg1-f197.google.com [209.85.215.197]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 12A673F042 for ; Thu, 9 Jan 2020 09:52:54 +0100 (CET) Received: by mail-pg1-f197.google.com with SMTP id r30sf3287072pgm.8 for ; Thu, 09 Jan 2020 00:52:53 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1578559972; cv=pass; d=google.com; s=arc-20160816; b=uDI73H7ZeZktX9LimxbByVlA8wds7yDTPgnPKPoGBGkMDfybFGVTI7OCwk2Z4Bei9r aI5wD9UkjFiESPxe7GfHeiODGN4eJlB7WhneW4+XJlgHgI/+QtO2Qo1ksaVwyd61le6F CcX2k/uLyE2eBqtJtWHc/jOk6sa3kGceRBTReqBEScTyfCwS4cM0UqlQHTM7F+0sv0C8 YKAGJ0aGgvn8/kk81dtIXvfrF5M7FVSaEXP7NQj2PqxejRzCq84efV6v0JhSylaqRs+l 6gjfxQZ+zLY7rQqMcbqM4vcdoEAOAwtkk5YU8dBpoW//RPs6XYGUiKBLH7zN6fiDYvXy QAYw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=rNmCzCPsMdpwMDqDd+Fc5/tcGfwiTMPbs1hpoePZ6Ag=; b=lLdZgVfSjNXJDu/Gm2VBP2i6pr+k6lGCbXBXB1qi3Ot1ozJ/GpLlSeyLHFfGw8fgPN i4XurfdURY6YOqx14qIMbWeUp2Vcz5uZldD+gdku1kyJtdvNmbCyc2GM/DjpMBb9DJLN tRDik3IKhcbHwvB+Vf2TRB+hWtsnVANPKaTPj7MKpPLaTMZknlxnvjjKeKskHnhbXVSd vQa3e0x16EUWkr0YK1MOQaqkfncFcWH5eAfnfo2ndk3nR2kR3Azig+AIKZ9l6X3hxiDy 0tSkH0Mu5xo3uLcprDRCcm4uZiQ6qACLV1v3C3jNtM+QzD+JFzxYfwQ3/pdct7dJDC/0 vlVw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=RzIwIlRD; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=rNmCzCPsMdpwMDqDd+Fc5/tcGfwiTMPbs1hpoePZ6Ag=; b=rf76k1wcIEeS2g7yqw+cOkTpWaZxiR4G3zbiMoIhE9faNNq4IcfKU0sSY6+TfV3nEw 7VnZ+sXuJUNK36NDjJM+pCyncRt5W81t1uF4YDF4gy6xEMUf+2xiGnhyjWvIshotMU8X liVVzSZiJnZAJDIOSIITALKOrB8s3sLl04lBE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=rNmCzCPsMdpwMDqDd+Fc5/tcGfwiTMPbs1hpoePZ6Ag=; b=bM+t7NRzR3UmcTyZOjCVqCEQGvFV0UatDWMw1bdbE5W6laI0LAolxrUuBzAG24YFLY 4+0gEKMFNInxrAKK8watQ2f5JM6sw0V4/0H7+5RMLGcH2aZLRSlERUch8VfPJ4mkpOlf BNdycMW7/lbXXvgrW468K1g01HaWSP7kxSlelOBmcLLWBLXIM6B/96+YnqQOvy7SA0tV W1xIlHaogyTRx70SuEL0gpSI5SoB1ninzBp02hlqXK55vIs4h+rztXjPpCQWTkOG/hjO XuNc1k2+nSSRxpBhxxvjvF3xo63eGYiJDLCbh3vpfacj2xYBjZcbIEcZ14UlwKxVPC7e CmPw== X-Gm-Message-State: APjAAAUojA2qcphwO9MmKKL8qaZhXtVW0EccMvWUeSQJbY4PeW3YGTKD eYYBlhYmGcLDKUOuF5QnAUiqaxCN X-Google-Smtp-Source: APXvYqyDaL14xIvN+erzWY5ew6DoHeHLxy+nnfgiGPE5jRVxg2tfSc+xlhrjlkhPFfuE3TTCm+NzuA== X-Received: by 2002:a63:4416:: with SMTP id r22mr9954635pga.254.1578559972273; Thu, 09 Jan 2020 00:52:52 -0800 (PST) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:902:567:: with SMTP id 94ls387144plf.8.gmail; Thu, 09 Jan 2020 00:52:52 -0800 (PST) X-Received: by 2002:a17:902:b40e:: with SMTP id x14mr10719184plr.242.1578559971724; Thu, 09 Jan 2020 00:52:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1578559971; cv=none; d=google.com; s=arc-20160816; b=nP6sq8Ka2E3pGjpfLF/KT/ACKTEEUwloBVbbxSyYLwfz4GZRyX8b1vByGL4I71RLHx 9tAGEr7niwkUpE6Qu+3PCHOk4OhrOzVd9eLD0J/aoSFLh5RDa/OQY6nUxLgQGBgfJRJL dQc89WagLamSCRpmtBj5MeG6gzWlD6nRUfc0Z3Bb6j6IXoNw+584op/hLliRzssjZkeo I8T4aqV+xr9bEJ/MATJO0mu0SB6rVQg0zVCfk+8exSLPx413eyMukwsOpOmxfYsBkXoH 5s4Df1UWkpJ1qTZkiN4IADELk+kV7WIorJ46xpkuXZA99rKF1BD4W/N/J8LWUgLmZCWq XvUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=20owJ56ZMVW9WaAfTMGTpTd1hkqe5DN6/beUbHwtw88=; b=CLfZSKs/hLkx0NLdPuMhyorAfruKPV87oGzlaberwmqcUS2svMr2eknVB6mb7e9HQh cDxMVY2jyqyUbXwi+XRTC9b8lm9BBHqfNIgjoLluxjPbcqPHvrkaowrl+wfc61TC22zn 4oktbhfenSP5U5A8ha0Fh0HxMkiER4n5QCF8lzSb2UtjVqDjBx8KecTOqnUfoTwvOxhk Sn140Da5zYdTPvGAI2dsLMoPv+xW5JlGrHt46oU7VERyZosIwqYMzN9WjSC7RbAmDdun z3z8Q6Ba2lM9G4AcRy+q3nEgOIUu99wdZlLlXwJP5cW2ZFsfQKR7CqytgAKg1WHweo4s lrGw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=RzIwIlRD; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id w17sor6595212plq.36.2020.01.09.00.52.51 for (Google Transport Security); Thu, 09 Jan 2020 00:52:51 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:902:8497:: with SMTP id c23mr11000845plo.59.1578559971367; Thu, 09 Jan 2020 00:52:51 -0800 (PST) Received: from localhost.localdomain ([2405:201:c809:c7d5:d888:9871:544a:b516]) by smtp.gmail.com with ESMTPSA id o17sm2139121pjq.1.2020.01.09.00.52.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jan 2020 00:52:50 -0800 (PST) From: Jagan Teki To: Kever Yang , Simon Glass , Philipp Tomsich Cc: u-boot@lists.denx.de, linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v4 4/8] rockchip: Add common reset cause Date: Thu, 9 Jan 2020 14:22:18 +0530 Message-Id: <20200109085222.22670-5-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20200109085222.22670-1-jagan@amarulasolutions.com> References: <20200109085222.22670-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=RzIwIlRD; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add cpu reset cause in common cpu-info file. This would help to print the reset cause for various resets. Right now it support rk3288, rk3399. rest of rockchip platforms doesn't have reset cause support ye but this code is more feasible to extend the same. Reviewed-by: Kever Yang Signed-off-by: Jagan Teki --- arch/arm/include/asm/arch-rockchip/cru.h | 12 +++++ .../include/asm/arch-rockchip/cru_rk3288.h | 14 +----- arch/arm/mach-rockchip/cpu-info.c | 49 +++++++++++++++++++ arch/arm/mach-rockchip/rk3288/rk3288.c | 39 --------------- 4 files changed, 62 insertions(+), 52 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h index 475d772fb6..5cf2aec11a 100644 --- a/arch/arm/include/asm/arch-rockchip/cru.h +++ b/arch/arm/include/asm/arch-rockchip/cru.h @@ -13,6 +13,18 @@ # include #endif +/* CRU_GLB_RST_ST */ +enum { + GLB_POR_RST, + FST_GLB_RST_ST = BIT(0), + SND_GLB_RST_ST = BIT(1), + FST_GLB_TSADC_RST_ST = BIT(2), + SND_GLB_TSADC_RST_ST = BIT(3), + FST_GLB_WDT_RST_ST = BIT(4), + SND_GLB_WDT_RST_ST = BIT(5), + GLB_RST_ST_MASK = GENMASK(5, 0), +}; + #define MHz 1000000 #endif /* _ROCKCHIP_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h index 7aa6efe46c..412b73e55f 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h @@ -51,7 +51,7 @@ struct rockchip_cru { u32 cru_glb_cnt_th; u32 cru_glb_rst_con; u32 reserved3; - u32 cru_glb_rst_st; + u32 glb_rst_st; u32 reserved4; u32 cru_sdmmc_con[2]; u32 cru_sdio0_con[2]; @@ -227,16 +227,4 @@ enum { CLKF_MASK = 0x1fff << CLKF_SHIFT, }; -/* CRU_GLB_RST_ST */ -enum { - GLB_POR_RST, - FST_GLB_RST_ST = BIT(0), - SND_GLB_RST_ST = BIT(1), - FST_GLB_TSADC_RST_ST = BIT(2), - SND_GLB_TSADC_RST_ST = BIT(3), - FST_GLB_WDT_RST_ST = BIT(4), - SND_GLB_WDT_RST_ST = BIT(5), - GLB_RST_ST_MASK = GENMASK(5, 0), -}; - #endif diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c index 9bccbd4f68..4b0e99299a 100644 --- a/arch/arm/mach-rockchip/cpu-info.c +++ b/arch/arm/mach-rockchip/cpu-info.c @@ -5,10 +5,59 @@ */ #include +#include +#include +#include +#include +#include + +static char *get_reset_cause(void) +{ + struct rockchip_cru *cru = rockchip_get_cru(); + char *cause = NULL; + + if (IS_ERR(cru)) + return cause; + + switch (cru->glb_rst_st) { + case GLB_POR_RST: + cause = "POR"; + break; + case FST_GLB_RST_ST: + case SND_GLB_RST_ST: + cause = "RST"; + break; + case FST_GLB_TSADC_RST_ST: + case SND_GLB_TSADC_RST_ST: + cause = "THERMAL"; + break; + case FST_GLB_WDT_RST_ST: + case SND_GLB_WDT_RST_ST: + cause = "WDOG"; + break; + default: + cause = "unknown reset"; + } + + /** + * reset_reason env is used by rk3288, due to special use case + * to figure it the boot behavior. so keep this as it is. + */ + env_set("reset_reason", cause); + + /* + * Clear glb_rst_st, so we can determine the last reset cause + * for following resets. + */ + rk_clrreg(&cru->glb_rst_st, GLB_RST_ST_MASK); + + return cause; +} int print_cpuinfo(void) { printf("SoC: Rockchip %s\n", CONFIG_SYS_SOC); + printf("Reset cause: %s\n", get_reset_cause()); /* TODO print operating temparature and clock */ diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c index 47ee5d440b..18ea7f35fb 100644 --- a/arch/arm/mach-rockchip/rk3288/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -102,43 +102,6 @@ void board_debug_uart_init(void) } #endif -static void rk3288_detect_reset_reason(void) -{ - struct rockchip_cru *cru = rockchip_get_cru(); - const char *reason; - - if (IS_ERR(cru)) - return; - - switch (cru->cru_glb_rst_st) { - case GLB_POR_RST: - reason = "POR"; - break; - case FST_GLB_RST_ST: - case SND_GLB_RST_ST: - reason = "RST"; - break; - case FST_GLB_TSADC_RST_ST: - case SND_GLB_TSADC_RST_ST: - reason = "THERMAL"; - break; - case FST_GLB_WDT_RST_ST: - case SND_GLB_WDT_RST_ST: - reason = "WDOG"; - break; - default: - reason = "unknown reset"; - } - - env_set("reset_reason", reason); - - /* - * Clear cru_glb_rst_st, so we can determine the last reset cause - * for following resets. - */ - rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK); -} - __weak int rk3288_board_late_init(void) { return 0; @@ -146,8 +109,6 @@ __weak int rk3288_board_late_init(void) int rk_board_late_init(void) { - rk3288_detect_reset_reason(); - return rk3288_board_late_init(); } From patchwork Thu Jan 9 08:52:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1022 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pf1-f200.google.com (mail-pf1-f200.google.com [209.85.210.200]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 65A733F042 for ; Thu, 9 Jan 2020 09:52:57 +0100 (CET) Received: by mail-pf1-f200.google.com with SMTP id c72sf3616261pfc.0 for ; Thu, 09 Jan 2020 00:52:57 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1578559976; cv=pass; d=google.com; s=arc-20160816; b=M9nXFBuOOgvy7FKuSjOFOfUEz1ccg6OTFv6unda0CaGV9IIkGQ0MiyUEm9Fm7jDDC+ NdGvT47Qm/4QekWUu1YzItk0LxX543MoGb0MIeJi7xDLuzAbg8kKKYkFCVjW8E3yWjR3 gsmil1f+kPgrtQ4EOQSs5RzmrbbRXv9CJHx1grGUqreFhNdrE2qHfTBomJJ64A/oC7dE NeqqtdKoIiH/NY/tvODfzhNnpTWLOvc2xfnOZVhTJnxql6++pRKlkbu+F/I/1Kk42m3B yexF5BY/OfQydJIqxld3fNhf+VbIycHqqdqaLNW+qnZVN60NZSQftSsXp3TWLdk+apBd oPOA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=fd5LfJDaC4ojsM2uAN9WxL2hk0xpgTt7jhr8zv8j+pY=; b=h4tM1rb1MfdHXGI/aQ8pjsm+7txvePUPblNBI10K9XZ+IMH8qDAbrL9wY3KnP6VDuJ VpZ2aydx0B4xW7lzVwejz4RnPR7M/OBBXnlLZaiHYye4qWj3aFwwB3PaGRkmqrmxAVG0 w86otUQ4oavf7haNc8LVTK8UDt4JzgmHeqPujPb6aTBxIHl67rxwAGM+gaTWk/zmMAt/ yeAshkpQeuYUV8MaG3P3Jw89XID8/W+/Fa1sD36+/xZbBHzVozG0JEiO8284LNp4/fko MX6Vyzwg903Xuf3PC6hYaLJMaZyIwlRtAhv5Lz6d7BFqYtI5Y58zuNPmxNxxYCVe7yTM DGeg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=iywMJA+Q; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=fd5LfJDaC4ojsM2uAN9WxL2hk0xpgTt7jhr8zv8j+pY=; b=HXoGRQZtwJ+wzRJdLpKslS7Y1Wx10MvfHEyBC8wPAiW8r73QPzqcKKRaI/awXgk++w 8m5f/s9OPkvG9ueZII4VhTFgpdJKQEiGrP8cx7MHJ7kflZuJeNX5zLGGyA6px4gfUXg4 M4rXve4YGtGnQ7jrL4vrL001h49E9wF5fv6ok= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=fd5LfJDaC4ojsM2uAN9WxL2hk0xpgTt7jhr8zv8j+pY=; b=Ot8Rz+f8ckn4gwzzHYf3IUA9sAorOtDcF1F3Bg0Hp28ZEeZt8ENsm+FbCgW5ZOB9N/ NW1vxghwXyFxw/9jUssYWCWu6wsptApoNMmcZU/qp/xk+QJIl5KqcPixcfvCUwBwzcl0 /S2JK5pfnWy3/E+kyk8vF7TgOm7zlXQ7QetlVVqnR/4ayB9JedjJaXQj4H+l3jKZhrm9 BaC2P2e9QmYcPZ5oBV3fTu1cJhdk6N6cXZQkJqjUddCWLz+iq78VZ3w2kYxIwxBiu/PH n91M58s0zlfphqQyVFjfyqlCp3FMW6ef6hDrUTFwH8GENPKwLbqSN/4rbes/g/AgzXSE 2B+w== X-Gm-Message-State: APjAAAVl3f4Di2ZuX1WsAN4m5L4asCifvVxLBeKNSM9P09FX/s36DnKp ShWVb6KISnyS2FwVqYdJ3/UnrkNq X-Google-Smtp-Source: APXvYqyWatp+T3zQIvmd4kKH7AGvc9r+yblYQ4cPxOuNpbqz/5zGM14Wzbh2744Q/2JQxaxUh/2QEQ== X-Received: by 2002:a17:90a:c385:: with SMTP id h5mr3974354pjt.122.1578559976143; Thu, 09 Jan 2020 00:52:56 -0800 (PST) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a62:6483:: with SMTP id y125ls391833pfb.9.gmail; Thu, 09 Jan 2020 00:52:55 -0800 (PST) X-Received: by 2002:a63:364f:: with SMTP id d76mr10260612pga.215.1578559975666; Thu, 09 Jan 2020 00:52:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1578559975; cv=none; d=google.com; s=arc-20160816; b=Y+ZGVj7+LQHtlvDjYxsNZ46qqcNBCZw0ty7jrYbue/P6Pz4vvrKJGl5Hd7yEYX9WNw /wnYZJiK563W8Lej5hh/QD72qWGjleD8X3824fDHtGQTvGB8+wVh/Ug/xepRToNW6mGE ovDxHghVuOtAlEluNpYhWh++CdZCnJDxB64SjXLhamC2LVKKPm2Mv3ZvtsuSeZ9bbWpq C1O/spDYifT1zRb3gh5bfW2Nd7zHTSLqLuyhl4r2l3VRYFCErJdHUVfOqn5sSTvoFlE2 6QS6B9R2zu8olbE6imW+2GYZqEpo71FxX0pFbJx5Ugn60Zi/7RPjXFq61FrebZcgDGdM svgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=oRKgs2PetZDvzDu1FBC+Mjjc1xHu28pIwI8pYrZq3es=; b=Tf0sS0DS6QioIj/jnInMOTphzn0kuyGMe4UZGmRLooiu+Z3Rai5vUfHiWO+uprvhcl EomnD8A0TSsWEmHTy4D80DaipjQ0ECcleVbWaPhxpsO65p+FfHFBsqj4qs98J2TyjZd3 MNaHS2x/JJgWMnDZIZpucq1MTn3soDHdBbEUif2cXO5cLL6C1C7z9Q72RPGXtEeXJLrH snpnVtfqvWIEF6VMWR7/2El1KpYIoz9/nA0/2+EY9+MtJvkeEeXCvzMy2JWoeLLzxkYR PuXIDsJcJ/kMKubqEQe4YkJ0dNW86YCJNC/lKjWH/2lSqjYfGRsKeYq3ozD5R+pRESPd g6cw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=iywMJA+Q; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id g22sor6612802pgl.73.2020.01.09.00.52.55 for (Google Transport Security); Thu, 09 Jan 2020 00:52:55 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a63:2949:: with SMTP id p70mr10177435pgp.191.1578559975335; Thu, 09 Jan 2020 00:52:55 -0800 (PST) Received: from localhost.localdomain ([2405:201:c809:c7d5:d888:9871:544a:b516]) by smtp.gmail.com with ESMTPSA id o17sm2139121pjq.1.2020.01.09.00.52.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jan 2020 00:52:54 -0800 (PST) From: Jagan Teki To: Kever Yang , Simon Glass , Philipp Tomsich Cc: u-boot@lists.denx.de, linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v4 5/8] rockchip: rk3399: Add bootcount support Date: Thu, 9 Jan 2020 14:22:19 +0530 Message-Id: <20200109085222.22670-6-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20200109085222.22670-1-jagan@amarulasolutions.com> References: <20200109085222.22670-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=iywMJA+Q; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add bootcount support for Rockchip rk3399. The bootcount value is preserved in PMU_SYS_REG0 register, this would help to support redundent boot. Once the redundant boot triggers, the altboot command will look for extlinux-rollback.conf on particular bootable partition which supposed to be a recovery partition where redundant boot required. Reviewed-by: Kever Yang Signed-off-by: Jagan Teki --- arch/arm/mach-rockchip/Kconfig | 2 ++ arch/arm/mach-rockchip/rk3399/Kconfig | 10 ++++++++++ include/configs/rk3399_common.h | 5 ++++- 3 files changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index d8d68ba447..9a3c65ec58 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -244,6 +244,8 @@ config ROCKCHIP_RK3399 imply TPL_CLK imply TPL_TINY_MEMSET imply TPL_ROCKCHIP_COMMON_BOARD + imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT + imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT help The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 and quad-core Cortex-A53. diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 868e85fc2a..f994152803 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -113,6 +113,16 @@ config TPL_TEXT_BASE config SPL_STACK_R_ADDR default 0x04000000 +if BOOTCOUNT_LIMIT + +config BOOTCOUNT_BOOTLIMIT + default 3 + +config SYS_BOOTCOUNT_ADDR + default 0xff3100f0 # PMU_SYS_REG0 + +endif # BOOTCOUNT_LIMIT + source "board/rockchip/evb_rk3399/Kconfig" source "board/theobroma-systems/puma_rk3399/Kconfig" source "board/vamrs/rock960_rk3399/Kconfig" diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 127ca1f09c..89a8a44bbe 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -63,7 +63,10 @@ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "partitions=" PARTS_DEFAULT \ ROCKCHIP_DEVICE_SETTINGS \ - BOOTENV + BOOTENV \ + "altbootcmd=" \ + "setenv boot_syslinux_conf extlinux/extlinux-rollback.conf;" \ + "run distro_bootcmd\0" #endif From patchwork Thu Jan 9 08:52:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1023 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pj1-f72.google.com (mail-pj1-f72.google.com [209.85.216.72]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 3EF613F042 for ; Thu, 9 Jan 2020 09:53:02 +0100 (CET) Received: by mail-pj1-f72.google.com with SMTP id dw15sf1228957pjb.2 for ; Thu, 09 Jan 2020 00:53:02 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1578559981; cv=pass; d=google.com; s=arc-20160816; b=hkZFmksqTyaPqfORynu5GvSMZyJB25UHEwDlAN3kyChtvZkng/x928s3y30DvtTAwN hGlZGNursSYCrZImZLG3q0plQynD52xYrb9nlqOvvvdneFsVEaw4EU5p5rJf3gjV0WDd qME2w6KBap8RdTt4+CKRSRFDX3r12Nxo7heno6jG7sIxqZV3HDQu3JIFGnJBlVixN0pm YIfYj+guPhu8Ch6/MUF3Fu3RNqPktPz4nPzkFiTUbQ7w4cJyl3hnv8+AclW5dlQnIUaV +4UsdN3GWjyMq83IdUDYfGS2xW2K4jPOGoifIRSySLfq798NSRS/ZiHtBBMDbA+jV0kO COPw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=HoavuawRC7C2bcm21CISuhaHN7LfIjYAEkcTWVntDck=; b=yd0Wb+kEFCYESkP4I10XGYbUVSzD9u0QulL/UjA3NQ3/cEMG9MljAhbM3gxPECNRlo Wh8mVumMc4FuWQ2+8/xr2B8g/B2j6w2S2Lx09lF9k035V41Qs/OQs//rKkunnEg7QrZi u99H0x7G7V/LSMagyYi+Kd8lq+ZptxI0NnsPL+dNzZxFtjNhgNZ5Cu6XnRE3bEdtqqzX 821uAtugGFR5z5NFZX5PRYjYGyyANqq+srx/vFqeyLTzXoMm35NXLDtNW82CuT5Sr/5t jQEI9Y1zHC938l7uEDg3jHWA540QuIhxAPjWsM++ETQT9ZsjPJxpjQqNPfb9cbLwQgpL gq8g== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=pqjl7SOg; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=HoavuawRC7C2bcm21CISuhaHN7LfIjYAEkcTWVntDck=; b=ZqVkS+dDWsWrTeVMuSZ9j8TMXCSB/y5Jc1RDud/o7d3FDPgRfvbLGIFjr4rOlzAdur EOHR0GVhb7xWf8+STwGhlrDXRKEJGGgEX50ULBt07VdnCO8QIz57YTM9VtHh1SX7gk2c oEWUDm4uTbkQ93Jweh6FL8PS8JboWB21lB6EQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=HoavuawRC7C2bcm21CISuhaHN7LfIjYAEkcTWVntDck=; b=EoO1XfNUCDhW812xfPZDDLFQeg6LsO+Jqb345WuD1xoh1uvFyIQgvsSJTilvyUeTay 1fK8R4qKb2szfP/Qx0SJrZpyjBRJCHpkVG/VLsavGX2ox7IaywLySanzGsIFR8AYmk9Q 142oUKOc/nCJOramOe6qoyaVKFFvqtuTQnBrvk7OPk2w3Rq1jvwTqk6pNjZUJNVMNKNk Rx/cZzadG0Zgp7CtXfGljhTuUhZUOX6SEVVRIBQVg1mI+5XgfYYSbY8EjEebApkp3bKD f1yCiRCZALKJuNpIiyz3reD3rRofwOWyCTkQMAS3gH3KfpcW6DoHkg9mIZHgx2q3MQSn EkOA== X-Gm-Message-State: APjAAAW+aGW1sYghBZh0e5jSASMXCwvZZ8pxigxVvnDWU0f2bMqj+kyk jSvGyO++FTUQepL0T3HbvoNH/kqw X-Google-Smtp-Source: APXvYqwuHOWTudEgN224BIIUlP/yXkqaQH5NGxZXWWebaUQKUWorGDUBpgL9P6LomUaRdlIAAqnkjw== X-Received: by 2002:a17:90a:3244:: with SMTP id k62mr4076066pjb.43.1578559981014; Thu, 09 Jan 2020 00:53:01 -0800 (PST) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:902:b491:: with SMTP id y17ls384367plr.16.gmail; Thu, 09 Jan 2020 00:53:00 -0800 (PST) X-Received: by 2002:a17:90a:21a7:: with SMTP id q36mr3956372pjc.140.1578559980589; Thu, 09 Jan 2020 00:53:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1578559980; cv=none; d=google.com; s=arc-20160816; b=r6eNYS7xzS3dyGzagoQOTB/+3RtFx+i0als0rjdEbFTjcoTSzQgykbk9vaEHb/7gbL 370N8gVU7UKQMPM4Bji8PUFnr60LVklNMztMBz2W+RJuCeMVxj8z0nXhCpyDmE1z4enr LSNmY7gcBSsOiiRTD4KAOaKXGxpoB17IlgEUXCzAPRetzFfpNi3pKMDBU9hQ7OHfuMjR fbJ+Odu/zU2XKgUldk23AhVpvRUA0KKnLWGKwYCBtZie0P2029Ifxafh0teo9ESoAnOW MA2c018NO1kS2IbKL0L6TZ/vyuSUTlgVKx7VTs/IkqzNoDvNg4UBClEBCsCzAN4uBKXQ ZYig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=8cmgO4h/IT9+TadX/gfjKX3N9uvs8I+qHAmIxhEKZPw=; b=bvfxWFu72zSLSzK0/33Es+6lQMJJcsQncxdbk6FxPDEb455yJ8SnZBVQ5SbSwe9GBH 9wjbY0r+PisLYiUVsufimByu3l8crEdnkdws+2cF8jdur+vLZeybm7UMzZXICrjnczi+ dFEfiitHiThtwDzP4Q48rr04zDuhQD+zfnHOSBOAncr3msXhse+NUBupe/DAemlJqtwy jIRPA6Z1g+zr8xia0Yn73+cHs+TfnWHtQrw/NDTtEFZsBryvZDiTd665etuwCzMkRa/u SZCRODXoxA4FQzv4tw4z5FXwbOvjjPV3kti1hx7+iZRk5A+g3byWpwn3Xqhl1ScuL//F BRmw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=pqjl7SOg; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id n16sor2202313pjc.27.2020.01.09.00.53.00 for (Google Transport Security); Thu, 09 Jan 2020 00:53:00 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:90a:dc82:: with SMTP id j2mr4112628pjv.70.1578559980334; Thu, 09 Jan 2020 00:53:00 -0800 (PST) Received: from localhost.localdomain ([2405:201:c809:c7d5:d888:9871:544a:b516]) by smtp.gmail.com with ESMTPSA id o17sm2139121pjq.1.2020.01.09.00.52.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jan 2020 00:52:59 -0800 (PST) From: Jagan Teki To: Kever Yang , Simon Glass , Philipp Tomsich Cc: u-boot@lists.denx.de, linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, Jagan Teki , Marek Vasut Subject: [PATCH v4 6/8] watchdog: kconfig: Enable designware for rk3399 Date: Thu, 9 Jan 2020 14:22:20 +0530 Message-Id: <20200109085222.22670-7-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20200109085222.22670-1-jagan@amarulasolutions.com> References: <20200109085222.22670-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=pqjl7SOg; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Enable designware watchdog driver for rk3399 if WDT defined. Cc: Marek Vasut Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- Changes for v4: - This change on top of below series https://patchwork.ozlabs.org/project/uboot/list/?series=151431 drivers/watchdog/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index bf5612a811..ceefee3a6b 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -48,6 +48,7 @@ config ULP_WATCHDOG config DESIGNWARE_WATCHDOG bool "Designware watchdog timer support" select HW_WATCHDOG if !WDT + default y if WDT && ROCKCHIP_RK3399 help Enable this to support Designware Watchdog Timer IP, present e.g. on Altera SoCFPGA SoCs. From patchwork Thu Jan 9 08:52:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1024 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pj1-f72.google.com (mail-pj1-f72.google.com [209.85.216.72]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id C3F5B3F042 for ; Thu, 9 Jan 2020 09:53:05 +0100 (CET) Received: by mail-pj1-f72.google.com with SMTP id dw15sf1229059pjb.2 for ; Thu, 09 Jan 2020 00:53:05 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1578559984; cv=pass; d=google.com; s=arc-20160816; b=hLBTCA80gAA6Gz5a5pG6MIOrlYmDW2r0WM4RdGcJx52iLBO8Fua82eFa4G0y3p8zSo A58du2r+SWil+Eku35rY5iL1447IXTPbJsi3CBRPQ1ntOzwY8mWMe1WKi8mC8evkLe3v Y6P9iKQiqTNIZZTr/GlZv8/IlIdpmBfzLk5LE8ESluS6IupVODXJ9e6etNS7g2wAqxY1 /exfXf3QZGim3M/SR4rElVZYbZJ5g5q6prC2ol2+wfzQgmMMRafw/ATh05WfSPJhRrXH DITymyIAaWaqQ+Cnt5sTUDd/WkMoR/tyzv+K3PyjaTwTj3eVAWa+CDYXgG/ejVKl5/3S rT4A== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=+nGMm/ZM5T1+C3kickpmNvqKWKjco1tNYX8R3oSOSKo=; b=aW0m+M44u1Wi4A8DquiBaiGXu1fFaHBr3fJsUzw965BeAnResKoVI3LSWNpBpPZRuW Bn9TeVb3dA/2BY7YYtHhdJ3x1x0oEyFjNBfeJXQTasiY/kLZb0tFXVNxKtX/tv7x/3Xy yjQw+DABha9Xq0G1DybjhyhUxq8Thi1WxokDfqvQR3K5keA7HDt0F61nqg8V6VjK5kbw tzFBYX9PBit0JBPeeN5LECQWTlzl0ZpY35qde88QdOxnKWWYfa9GGAR0W+FNtMp9fsAo nfh+lPZOm4NBsRKiSJS0YFt3pOnpWcPxzpi9LBN0BJnAW6kvVCX83v+1cgSi6c2KXyd1 VLYQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="DMR5la/v"; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=+nGMm/ZM5T1+C3kickpmNvqKWKjco1tNYX8R3oSOSKo=; b=k/e7V+QDlbW3MiPr9tuv+n3Wof3B2qXp4yXRreCqP3hfs1UuLJGOha7c7/kaniB959 O0ZZZw5Pl4LZueyWit6Ss0whPEwtdwshP672neHGob7TiPayI3w1HYvUevHLsZXg3WOg ePgE+zKVWb76cnvwB6PawqQLvmf3Lv/hxTjPo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=+nGMm/ZM5T1+C3kickpmNvqKWKjco1tNYX8R3oSOSKo=; b=g889jk3ypPcmviVo+VdlKWpXtv13b/K4v66VltPcQvx35LY6D2ntoIM54IDayzZ+XB lqHS3A2D/p/J8d9JvEcxlAYJA7oV/0yKVq6z9ExYl0RqiBKZc9eAUtxuMsbL+zDsaL23 3BCFZVyP9TbfOo7DbsD3nensh/2/ZCdcE2zjmi/c7YO43wnQBRTISCdtPL+FR+kVCPMa DjQwwGq9K8zNy69qfIZBFa3NsIwA+clQP/uy5EJhGWMZKmLMU7OGXsH5Y/EemxAaReXy On2jFaeseCauRYGTpbgtEBzrnPub02hlIdb/x+PGmA4Y1ebxSkJPigr3V/7R5YYdds8F jlAw== X-Gm-Message-State: APjAAAWfZFzEm5U0mL08wsyUAU/3s38+2IxS3p8kB1r/hncK3SREQnUk nVyjBdkEmRKzW8M8RJGKlnszuVW8 X-Google-Smtp-Source: APXvYqzV1kk2IZYQSO7lk82gf2qlUVW8XWTgeyHYXRbZTRnElXO5LmWNVLBUa+v7gaHwP2i6nzxcJA== X-Received: by 2002:a63:a53:: with SMTP id z19mr9954660pgk.267.1578559984546; Thu, 09 Jan 2020 00:53:04 -0800 (PST) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a62:e107:: with SMTP id q7ls389349pfh.15.gmail; Thu, 09 Jan 2020 00:53:04 -0800 (PST) X-Received: by 2002:a63:4b24:: with SMTP id y36mr9926141pga.176.1578559984029; Thu, 09 Jan 2020 00:53:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1578559984; cv=none; d=google.com; s=arc-20160816; b=fj4b17l2W1LZYUymj+QcgHMIyC8wQz1QJxR9Y+b0Vd0GelgY0eN3X8KQaZdKTa4KLJ rFb37WSl6owcU/amicKXusIOL2ehIrj7ButtoQXro7TcRXkljRSgnZzjC1HAFZbpDrg9 3gp8R9if3vkdHbbKBIQXH7Rb5DjOEOK1s9Ys/FCNCjG/g/DWolpDrg+noaRA2oal6iNo kFTkU9NIHV9tAyqkwwbCjhI5SovxKOlYgixM1BQGCD31+KC9Q10VBa8ZFmkVJZG2KpF2 ayRCL46VaqiMyTcaE6L0RNhTNWafqLPkG3ywV4qUA+9FwHcpYUdnkDZrGJmfvMkxpsop qExQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=wU89ZzkCdHruUB3Gwr5/4Tn4Jy9OV6GxNn11DpZfCms=; b=C2BGUus+p0ZwLWHgGHkdrt1I0vtqONaZgb4NvNtTU/sTssl6i2SEPZdKv5izcohbeO NTTt30asFCV53FgiCYTWqTq+jCq3RET+ACyGfPiv7SHxmxAYWWmuamZkRW5ZTcUfdieL nDw8zxJ55UsuZBgp/n1zOdfw62vz0U3dXm6ipIkgNhO81jW6LiMVtfHJNa8MRdyirArS uyMHT2xOf8rZ4V+BFawqKing1StojapqHKHV/Y3HXgYs3tbqYL3ZlOi3CRJKgKCL0/9c rsN/OpSYI1a8qwDvWDX3bF/PKMLURB69QN9ZWXtpJA54fHPFoMDu0+wf1/wT95CywLUr VK+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="DMR5la/v"; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id z14sor6700172pgj.63.2020.01.09.00.53.04 for (Google Transport Security); Thu, 09 Jan 2020 00:53:04 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a63:1344:: with SMTP id 4mr10371705pgt.0.1578559983723; Thu, 09 Jan 2020 00:53:03 -0800 (PST) Received: from localhost.localdomain ([2405:201:c809:c7d5:d888:9871:544a:b516]) by smtp.gmail.com with ESMTPSA id o17sm2139121pjq.1.2020.01.09.00.53.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jan 2020 00:53:03 -0800 (PST) From: Jagan Teki To: Kever Yang , Simon Glass , Philipp Tomsich Cc: u-boot@lists.denx.de, linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [DO NOT MERGE] [PATCH v4 7/8] roc-rk3399-pc: Enable watchdog Date: Thu, 9 Jan 2020 14:22:21 +0530 Message-Id: <20200109085222.22670-8-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20200109085222.22670-1-jagan@amarulasolutions.com> References: <20200109085222.22670-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="DMR5la/v"; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Enable watchdog suport for ROC-RK3399-PC board. Signed-off-by: Jagan Teki --- configs/roc-pc-rk3399_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index bf83b25dbc..b30ca55107 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -54,3 +54,4 @@ CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y +CONFIG_WDT=y From patchwork Thu Jan 9 08:52:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1025 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pf1-f198.google.com (mail-pf1-f198.google.com [209.85.210.198]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 58BAE3F042 for ; Thu, 9 Jan 2020 09:53:09 +0100 (CET) Received: by mail-pf1-f198.google.com with SMTP id d127sf3601485pfa.7 for ; Thu, 09 Jan 2020 00:53:09 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1578559988; cv=pass; d=google.com; s=arc-20160816; b=taS6reL3sJrnAmRj8UWedsPcSSNXUgQJu7IH0qLQ/UFyzBV5nKroOuWJ3d+Bq/CC/m 7w/jlX37nYeVurGM0pNRvt6inQPI9fvOfPsnMR9NYawVeVaZ6HvGgJNU+knUs9MLqUGc k3kPPdVnX2wNAJMbF7Iv/Klm38UTZEYPTl50uv3DuhCkeixpQwJaFPp2QjMs3V2EX94N Y0PYMMQq6ZEZE/OHIKRjLcVv3RJ2c0wncRxicCi0Rc58sGrnBKr1XQYwPranLLpzFGCk noNyC09uBOykaG9jq+zi+V7smOd4NkMaBY9Y9CoXDH+or4t2MFc/2Rumh092MiXdWQhv lqhA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=YwPTJRKBtGgNecPS44olL6IQAJFBvMwelpN6ktXrOYc=; b=nbETCNRy3FHetdGJT5Exl5DH3AS/SuFGhY664h+HuKvhUy8a8BsLMMvXzLXxVqNVP2 rGfnamjXJC52EVgLB4psh0hu0WIZ54Bn8T4ZDtaMkia+pk4UFrtns/KY0VlCorwXi5Z+ Nhgr+kkM848gJYR7mrM12lV4yDs2z2mirWoPRbuIsSr3+WSPwhkoQWT7inJIaVxFiapW HW1MKkCumawkEGUo4dqenfb6Y/MvJ84lvZavOl3KgD6NL3h1FFtpK2/Fx3NmdLluzq6l 8/HQ0n+GcKaCX4unvVsiJ6LVGeG+OmTLHk5mV2IRnryr62wAL9YdMGP4cdCHjxk7XIkR 3beA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=BQzQsQeq; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=YwPTJRKBtGgNecPS44olL6IQAJFBvMwelpN6ktXrOYc=; b=f/YDcxnW62cScaTA4COps7v282GOfBJ2YRdzlfs0yVdFCsVy7w684MiEIaKQbtc4Vt hwYr0nM6+2eB74mu3dOqHDB0RR6ktHGtHzcqgXG8m48nBmEvDw0b1D5zA0LEKFZJJWOz a03ZrJadq7fAynhBnAs8vpJ4EqdTpkQzeyQ/8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=YwPTJRKBtGgNecPS44olL6IQAJFBvMwelpN6ktXrOYc=; b=AZlWWDdMN73NI1wxNh2z3PTCyPH+JK0UziMWrBDTVHFrDMtE3vmatlAYO59jvpQpuX BWulacA+DjxIyQXiq9wta8Tlv03xa7REqcXyPGJC+z2m4o8DER/2P5hxMBYSULGxV7us qUeRhrNiSbV0iYvvZWqf5mSnGXWp+hb1Xpf8c6/+akicUpOjgRsXUgFDVtGBv7i0UTmv LB2vzmL+gWHGeqbgFeiWthQohWG2RLBlN/Ae1u3DqolQozpCkcsVjPeobVtaIpwokicD J+ivys5nR4GncxA0BnEMTlUa9uJvubCUVgXVuqe348jV0QSn+zOcz2UBU6YYR0IzGP09 AIFA== X-Gm-Message-State: APjAAAVgiGtMLvQyCK+hiEDR1EazrfnEih2WoKCgx8vd4EpIa+4T2r0R NrRFCPmgTFnRB2QFZF7DYmOyiyYZ X-Google-Smtp-Source: APXvYqzIWmEE/cDsW4Ij+FgtemzaeNSWSpb77+N4JxX9AC632Em9f5CVqq34XMDNDL8w2rZtgjnz8A== X-Received: by 2002:a62:e30f:: with SMTP id g15mr9928244pfh.124.1578559988093; Thu, 09 Jan 2020 00:53:08 -0800 (PST) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a63:9142:: with SMTP id l63ls382110pge.6.gmail; Thu, 09 Jan 2020 00:53:07 -0800 (PST) X-Received: by 2002:a62:e512:: with SMTP id n18mr10064425pff.50.1578559987570; Thu, 09 Jan 2020 00:53:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1578559987; cv=none; d=google.com; s=arc-20160816; b=VzjOTnci/3/qOSdIh0KIo7fUx03WcYREBTimMtGytmlrLvmb191ElfZI5mFNdo6xT8 rw/m1q87nr+vyYtn1a7h9uQi149XEQ9WR3Ig8APhP2lnKT1a6QHZ0i+Y/CZEPTyUvnnP PXhu487nKVfLFr2m0FaZuvokDzpriVaWGZGCCnMiOWP1T1x7eocPaMUSZ1akXelaUVQs UowCASEKW2AIpbS2U6wCELAAPFMvaYZh11vS66exYZoQK2M3qSaxkfO2nKHhGWzhgzg+ 3iKqLVED/xNKh8UaLolRFbVgSCr9YYm9w40YTLQggEqSJktKzM5LvCmMGRBSTUQu46vX gmQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=6xGEGff8OdpIdn4cmrOvltKOrUfcqxXjukkBhY/H/R8=; b=HeoZDPtGm8Uz8mWXiwPE3gTxN0fqu4uEROS0B9bJYQ252kqZ+KHgL7pjv/wlTHRm7C Kkvzw+PWpO36TmxZ7gaJ6Wm+jVM6uKcud+8DRhnwLLcHsvcpRKcBrDTSDVozOUteq5SZ b4aYng7t8D3OXFdxR95z17rZTsYboiKns67exrx+KWCitRdptYPxFyUGNiLOj+Nwr7hR iBEeid0n0QGdnxfKiHnnR9IgMPq0I3X5yPecT2LOHth9HjgkUso2YU72gVzAUKcOHVBl eoKVKNiIm1BMkFlMqClMKFgJyLljNCKOeTHk6Z6k9k8mqoZa9mWPNiZPfKzQ3v6s37TQ IRfA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=BQzQsQeq; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id az2sor6548232plb.61.2020.01.09.00.53.07 for (Google Transport Security); Thu, 09 Jan 2020 00:53:07 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:902:b087:: with SMTP id p7mr10902033plr.10.1578559987266; Thu, 09 Jan 2020 00:53:07 -0800 (PST) Received: from localhost.localdomain ([2405:201:c809:c7d5:d888:9871:544a:b516]) by smtp.gmail.com with ESMTPSA id o17sm2139121pjq.1.2020.01.09.00.53.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jan 2020 00:53:06 -0800 (PST) From: Jagan Teki To: Kever Yang , Simon Glass , Philipp Tomsich Cc: u-boot@lists.denx.de, linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [DO NOT MERGE] [PATCH v4 8/8] roc-rk3399-pc: Enable bootcount Date: Thu, 9 Jan 2020 14:22:22 +0530 Message-Id: <20200109085222.22670-9-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20200109085222.22670-1-jagan@amarulasolutions.com> References: <20200109085222.22670-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=BQzQsQeq; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Enable bootcount suport for ROC-RK3399-PC board. Signed-off-by: Jagan Teki --- configs/roc-pc-rk3399_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index b30ca55107..e4b26b037b 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -55,3 +55,4 @@ CONFIG_USB_ETHER_SMSC95XX=y CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y CONFIG_WDT=y +CONFIG_BOOTCOUNT_LIMIT=y