From patchwork Mon Dec 10 11:52:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 66 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-wr1-f72.google.com (cartago.priv [10.11.12.1]) by cassiopea (Postfix) with ESMTPS id 399822E549C for ; Mon, 10 Dec 2018 12:53:31 +0100 (CET) Received: by mail-wr1-f72.google.com with SMTP id x3sf3296097wru.22 for ; Mon, 10 Dec 2018 03:53:31 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1544442811; cv=pass; d=google.com; s=arc-20160816; b=rcs3BOwjqCog3GaXG5G+hFUhiBVqgvGLnuE10cdHrFEjx8SfqGS2FqnqxPKeqTKgbe YJX+obVSJ1eYTukfJzTqChFKQj6vaWdDxTcpnYksCFzRhMRIPA4AUqVbR/wlt8PasFqf qYGB48DBL+ZUWKK6fx7bab4ZRa63eS0IeAHTLVcFwGL0w50+9kRTfrwQ7k5OKueNx4k5 rcOlc4+wQcUU+4MSCDkSp716apP0R/6Lk2yJND60vltiJ00TKgoIfujYaV5UTbNDMpND D6m4cJFDFufkbunc8Wx63EnLvNOfx3BmmDigABPGyR2UU/5lzt9IyuPrnoxuiaaEWlNC vamg== ARC-Message-Signature: i=2; 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[213.198.162.59]) by smtp.gmail.com with ESMTPSA id b16sm7869243wrm.41.2018.12.10.03.53.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 10 Dec 2018 03:53:29 -0800 (PST) From: Jagan Teki To: Yong Deng , Mauro Carvalho Chehab , Maxime Ripard , Rob Herring , Mark Rutland , Chen-Yu Tsai , linux-media@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi , linux-amarula@amarulasolutions.com, Michael Trimarchi Cc: Jagan Teki Subject: [PATCH v3 1/6] dt-bindings: media: sun6i: Add A64 CSI compatible Date: Mon, 10 Dec 2018 17:22:41 +0530 Message-Id: <20181210115246.8188-2-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20181210115246.8188-1-jagan@amarulasolutions.com> References: <20181210115246.8188-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="F3RJywn/"; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Allwinner A64 CSI has single channel time-multiplexed BT.656 CMOS sensor interface like H3 but work by lowering clock than default mod clock. Add a compatible string for it. Signed-off-by: Jagan Teki Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/media/sun6i-csi.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/media/sun6i-csi.txt b/Documentation/devicetree/bindings/media/sun6i-csi.txt index cc37cf7fd051..376aade669a1 100644 --- a/Documentation/devicetree/bindings/media/sun6i-csi.txt +++ b/Documentation/devicetree/bindings/media/sun6i-csi.txt @@ -7,6 +7,7 @@ Required properties: - compatible: value must be one of: * "allwinner,sun6i-a31-csi" * "allwinner,sun8i-h3-csi" + * "allwinner,sun50i-a64-csi" * "allwinner,sun8i-v3s-csi" - reg: base address and size of the memory-mapped region. - interrupts: interrupt associated to this IP From patchwork Mon Dec 10 11:52:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 67 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-wr1-f69.google.com (cartago.priv [10.11.12.1]) by cassiopea (Postfix) with ESMTPS id F04972E540B for ; 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[213.198.162.59]) by smtp.gmail.com with ESMTPSA id b16sm7869243wrm.41.2018.12.10.03.53.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 10 Dec 2018 03:53:31 -0800 (PST) From: Jagan Teki To: Yong Deng , Mauro Carvalho Chehab , Maxime Ripard , Rob Herring , Mark Rutland , Chen-Yu Tsai , linux-media@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi , linux-amarula@amarulasolutions.com, Michael Trimarchi Cc: Jagan Teki Subject: [PATCH v3 2/6] media: sun6i: Add A64 compatible support Date: Mon, 10 Dec 2018 17:22:42 +0530 Message-Id: <20181210115246.8188-3-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20181210115246.8188-1-jagan@amarulasolutions.com> References: <20181210115246.8188-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=RtODiqXU; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Allwinner A64 CSI has single channel time-multiplexed BT.656 CMOS sensor interface like H3 but work by lowering clock than default mod clock. So use separate compatibe to support it. Signed-off-by: Jagan Teki --- drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c index ee882b66a5ea..bbe45e893722 100644 --- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c +++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c @@ -892,6 +892,7 @@ static int sun6i_csi_remove(struct platform_device *pdev) } static const struct of_device_id sun6i_csi_of_match[] = { + { .compatible = "allwinner,sun50i-a64-csi", }, { .compatible = "allwinner,sun6i-a31-csi", }, { .compatible = "allwinner,sun8i-h3-csi", }, { .compatible = "allwinner,sun8i-v3s-csi", }, From patchwork Mon Dec 10 11:52:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 68 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-wr1-f69.google.com (cartago.priv [10.11.12.1]) by cassiopea (Postfix) with ESMTPS id CE3C92E549C for ; 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[213.198.162.59]) by smtp.gmail.com with ESMTPSA id b16sm7869243wrm.41.2018.12.10.03.53.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 10 Dec 2018 03:53:33 -0800 (PST) From: Jagan Teki To: Yong Deng , Mauro Carvalho Chehab , Maxime Ripard , Rob Herring , Mark Rutland , Chen-Yu Tsai , linux-media@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi , linux-amarula@amarulasolutions.com, Michael Trimarchi Cc: Jagan Teki Subject: [PATCH v3 3/6] media: sun6i: Set 300MHz mod clock for A64 Date: Mon, 10 Dec 2018 17:22:43 +0530 Message-Id: <20181210115246.8188-4-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20181210115246.8188-1-jagan@amarulasolutions.com> References: <20181210115246.8188-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=YjpI9uyv; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The default CSI_SCLK seems unable to drive the sensor to capture the image, so update it to working clock rate 300MHz for A64. Signed-off-by: Jagan Teki --- drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c index bbe45e893722..4b872800b244 100644 --- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c +++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c @@ -822,6 +822,11 @@ static int sun6i_csi_resource_request(struct sun6i_csi_dev *sdev, return PTR_ERR(sdev->clk_mod); } + /* A64 need 300MHz mod clock to operate properly */ + if (of_device_is_compatible(pdev->dev.of_node, + "allwinner,sun50i-a64-csi")) + clk_set_rate_exclusive(sdev->clk_mod, 300000000); + sdev->clk_ram = devm_clk_get(&pdev->dev, "ram"); if (IS_ERR(sdev->clk_ram)) { dev_err(&pdev->dev, "Unable to acquire dram-csi clock\n"); From patchwork Mon Dec 10 11:52:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 69 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-wr1-f69.google.com (cartago.priv [10.11.12.1]) by cassiopea (Postfix) with ESMTPS id 998BD2E540B for ; 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[209.85.220.65]) by mx.google.com with SMTPS id o8sor3466293wmh.14.2018.12.10.03.53.35 for (Google Transport Security); Mon, 10 Dec 2018 03:53:35 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a7b:c142:: with SMTP id z2mr11014121wmi.102.1544442815538; Mon, 10 Dec 2018 03:53:35 -0800 (PST) Received: from localhost.localdomain (ip-162-59.sn-213-198.clouditalia.com. [213.198.162.59]) by smtp.gmail.com with ESMTPSA id b16sm7869243wrm.41.2018.12.10.03.53.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 10 Dec 2018 03:53:34 -0800 (PST) From: Jagan Teki To: Yong Deng , Mauro Carvalho Chehab , Maxime Ripard , Rob Herring , Mark Rutland , Chen-Yu Tsai , linux-media@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi , linux-amarula@amarulasolutions.com, Michael Trimarchi Cc: Jagan Teki Subject: [PATCH v3 4/6] arm64: dts: allwinner: a64: Add A64 CSI controller Date: Mon, 10 Dec 2018 17:22:44 +0530 Message-Id: <20181210115246.8188-5-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20181210115246.8188-1-jagan@amarulasolutions.com> References: <20181210115246.8188-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="n/al2t3N"; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Allwinner A64 CSI controller has similar features as like in H3, but work by lowering clock than default mod clock. Signed-off-by: Jagan Teki --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 384c417cb7a2..89a0deb3fe6a 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -532,6 +532,12 @@ interrupt-controller; #interrupt-cells = <3>; + csi_pins: csi-pins { + pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", + "PE7", "PE8", "PE9", "PE10", "PE11"; + function = "csi0"; + }; + i2c0_pins: i2c0_pins { pins = "PH0", "PH1"; function = "i2c0"; @@ -899,6 +905,20 @@ status = "disabled"; }; + csi: csi@1cb0000 { + compatible = "allwinner,sun50i-a64-csi"; + reg = <0x01cb0000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI_SCLK>, + <&ccu CLK_DRAM_CSI>; + clock-names = "bus", "mod", "ram"; + resets = <&ccu RST_BUS_CSI>; + pinctrl-names = "default"; + pinctrl-0 = <&csi_pins>; + status = "disabled"; + }; + hdmi: hdmi@1ee0000 { compatible = "allwinner,sun50i-a64-dw-hdmi", "allwinner,sun8i-a83t-dw-hdmi"; From patchwork Mon Dec 10 11:52:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 70 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-wm1-f72.google.com (cartago.priv [10.11.12.1]) by cassiopea (Postfix) with ESMTPS id 81EA02E549C for ; Mon, 10 Dec 2018 12:53:38 +0100 (CET) Received: by mail-wm1-f72.google.com with SMTP id w17sf1658264wmc.6 for ; Mon, 10 Dec 2018 03:53:38 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1544442818; cv=pass; d=google.com; s=arc-20160816; b=fAosh21ksu9xy6sTmy9h1vKeOHpNDurLrS8sP7gf65udvj2to+NEBKGXW5APwoVdcZ YDkPWzsFG6fgtPvEbKJ6RAc/fEBhv3viOmkWrsEkBzqfV2I67dQVOnG2Zfy7J1JJYdsu tNyP1OjmZTfPfp0ZuDzesMBrMhr+DENI/EOtfhqyPiZeX9xEWyY8YMBKOhBYHcNDgfzc YXe2vXuNdpUzF/V8aF4mtYG5Sz+VJedTxMnOxq2njUiI/YFWzhYDamaRN6ZXBCrF0vLs 9Eh4A/TQmjYBoIP2jLUc6uYL49+PpoJ1Is5vDL3+A69uIyrTmRpxWxhjgsfvqbJhmcP/ +8tA== ARC-Message-Signature: i=2; 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[213.198.162.59]) by smtp.gmail.com with ESMTPSA id b16sm7869243wrm.41.2018.12.10.03.53.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 10 Dec 2018 03:53:36 -0800 (PST) From: Jagan Teki To: Yong Deng , Mauro Carvalho Chehab , Maxime Ripard , Rob Herring , Mark Rutland , Chen-Yu Tsai , linux-media@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi , linux-amarula@amarulasolutions.com, Michael Trimarchi Cc: Jagan Teki Subject: [PATCH v3 5/6] arm64: dts: allwinner: a64: Add pinmux setting for CSI MCLK on PE1 Date: Mon, 10 Dec 2018 17:22:45 +0530 Message-Id: <20181210115246.8188-6-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20181210115246.8188-1-jagan@amarulasolutions.com> References: <20181210115246.8188-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=rmKhqxus; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Some camera modules have the SoC feeding a master clock to the sensor instead of having a standalone crystal. This clock signal is generated from the clock control unit and output from the CSI MCLK function of pin PE1. Add a pinmux setting for it for camera sensors to reference. Signed-off-by: Jagan Teki --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 89a0deb3fe6a..dd5740bc3fc9 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -538,6 +538,11 @@ function = "csi0"; }; + csi_mclk_pin: csi-mclk { + pins = "PE1"; + function = "csi0"; + }; + i2c0_pins: i2c0_pins { pins = "PH0", "PH1"; function = "i2c0"; From patchwork Mon Dec 10 11:52:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 71 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-wr1-f69.google.com (cartago.priv [10.11.12.1]) by cassiopea (Postfix) with ESMTPS id E4FEB2E540B for ; Mon, 10 Dec 2018 12:53:40 +0100 (CET) Received: by mail-wr1-f69.google.com with SMTP id l1sf3420054wrn.3 for ; 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[209.85.220.41]) by mx.google.com with SMTPS id 140sor7508961wme.14.2018.12.10.03.53.40 for (Google Transport Security); Mon, 10 Dec 2018 03:53:40 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a1c:d912:: with SMTP id q18mr10093519wmg.122.1544442819830; Mon, 10 Dec 2018 03:53:39 -0800 (PST) Received: from localhost.localdomain (ip-162-59.sn-213-198.clouditalia.com. [213.198.162.59]) by smtp.gmail.com with ESMTPSA id b16sm7869243wrm.41.2018.12.10.03.53.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 10 Dec 2018 03:53:38 -0800 (PST) From: Jagan Teki To: Yong Deng , Mauro Carvalho Chehab , Maxime Ripard , Rob Herring , Mark Rutland , Chen-Yu Tsai , linux-media@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi , linux-amarula@amarulasolutions.com, Michael Trimarchi Cc: Jagan Teki Subject: [PATCH v3 6/6] arm64: dts: allwinner: a64-amarula-relic: Add OV5640 camera node Date: Mon, 10 Dec 2018 17:22:46 +0530 Message-Id: <20181210115246.8188-7-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20181210115246.8188-1-jagan@amarulasolutions.com> References: <20181210115246.8188-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=n0lVMIhf; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Amarula A64-Relic board by default bound with OV5640 camera, so add support for it with below pin information. - PE13, PE12 via i2c-gpio bitbanging - CLK_CSI_MCLK as external clock - PE1 as external clock pin muxing - ALDO1 as AVDD supply - DLDO3 as DOVDD supply - ELDO3 as DVDD supply - PE14 gpio for reset pin - PE15 gpio for powerdown pin Signed-off-by: Jagan Teki --- .../allwinner/sun50i-a64-amarula-relic.dts | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts index 6cb2b7f0c817..ea6286ce5de3 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts @@ -22,6 +22,41 @@ stdout-path = "serial0:115200n8"; }; + i2c-csi { + compatible = "i2c-gpio"; + sda-gpios = <&pio 4 13 GPIO_ACTIVE_HIGH>; /* CSI-SDA: PE13 */ + scl-gpios = <&pio 4 12 GPIO_ACTIVE_HIGH>; /* CSI-SCK: PE12 */ + i2c-gpio,delay-us = <5>; + #address-cells = <1>; + #size-cells = <0>; + + ov5640: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&csi_mclk_pin>; + clocks = <&ccu CLK_CSI_MCLK>; + clock-names = "xclk"; + + AVDD-supply = <®_aldo1>; + DOVDD-supply = <®_dldo3>; + DVDD-supply = <®_eldo3>; + reset-gpios = <&pio 4 14 GPIO_ACTIVE_LOW>; /* CSI-RST-R: PE14 */ + powerdown-gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>; /* CSI-STBY-R: PE15 */ + + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi_ep>; + bus-width = <8>; + hsync-active = <1>; /* Active high */ + vsync-active = <0>; /* Active low */ + data-active = <1>; /* Active high */ + pclk-sample = <1>; /* Rising */ + }; + }; + }; + }; + wifi_pwrseq: wifi-pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <&rtc 1>; @@ -30,6 +65,24 @@ }; }; +&csi { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + csi_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + bus-width = <8>; + hsync-active = <1>; /* Active high */ + vsync-active = <0>; /* Active low */ + data-active = <1>; /* Active high */ + pclk-sample = <1>; /* Rising */ + }; + }; +}; + &ehci0 { status = "okay"; };