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[209.85.220.65]) by mx.google.com with SMTPS id l1sor11498868plb.41.2020.06.08.11.32.00 for (Google Transport Security); Mon, 08 Jun 2020 11:32:00 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:902:9047:: with SMTP id w7mr86571plz.275.1591641119986; Mon, 08 Jun 2020 11:31:59 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:9043:af95:b7b4:3ade]) by smtp.gmail.com with ESMTPSA id k29sm6680961pgf.77.2020.06.08.11.31.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jun 2020 11:31:59 -0700 (PDT) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: Suniel Mahesh , U-Boot-Denx , linux-rockchip@lists.infradead.org, linux-amarula , Jagan Teki Subject: [PATCH v3 1/5] rk3399: spl: Add rk_spl_board_init as __weak Date: Mon, 8 Jun 2020 14:31:40 -0400 Message-Id: <20200608183144.26809-2-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200608183144.26809-1-jagan@amarulasolutions.com> References: <20200608183144.26809-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=KXrbf0GJ; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Current spl_board_init is mostly specific to puma-rk3399 target and in other words it cannot be required or useful for other rk3399 boards. Some boards require their custom initialization to be part of spl_board_init like roc-rk3399-pc require leds setup, environments. So, this patch handles all these possible scenarios. Add rk_spl_board_init as __weak so that boards that require their own custom initialization can be defined on their board file. Signed-off-by: Jagan Teki Tested-by: Suniel Mahesh --- Changes for v3: - new patch arch/arm/mach-rockchip/rk3399/rk3399.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index 4fda93b152..681f80f339 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -241,7 +241,7 @@ static void rk3399_force_power_on_reset(void) } #endif -void spl_board_init(void) +__weak void rk_spl_board_init(void) { #if defined(SPL_GPIO_SUPPORT) struct rockchip_cru *cru = rockchip_get_cru(); @@ -274,4 +274,11 @@ void spl_board_init(void) debug("%s: Cannot enable boot on regulator\n", __func__); #endif } + +void spl_board_init(void) +{ + /* board specific spl init */ + rk_spl_board_init(); +} + #endif From patchwork Mon Jun 8 18:31:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1347 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pl1-f198.google.com (mail-pl1-f198.google.com [209.85.214.198]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 463403F06D for ; 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[209.85.220.65]) by mx.google.com with SMTPS id n22sor549411pjn.13.2020.06.08.11.32.04 for (Google Transport Security); Mon, 08 Jun 2020 11:32:04 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:90b:110f:: with SMTP id gi15mr622869pjb.87.1591641124486; Mon, 08 Jun 2020 11:32:04 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:9043:af95:b7b4:3ade]) by smtp.gmail.com with ESMTPSA id k29sm6680961pgf.77.2020.06.08.11.32.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jun 2020 11:32:03 -0700 (PDT) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: Suniel Mahesh , U-Boot-Denx , linux-rockchip@lists.infradead.org, linux-amarula , Jagan Teki Subject: [PATCH v3 2/5] rk3399: spl: Print SPL banner after relocation Date: Mon, 8 Jun 2020 14:31:41 -0400 Message-Id: <20200608183144.26809-3-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200608183144.26809-1-jagan@amarulasolutions.com> References: <20200608183144.26809-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=o4vOcHSl; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Usually printing the SPL banner varies between architecture or board codes. - Some would print before relocation at the end board_init_f   for making sure all initialization prior to this would happen   properly. if at all there is a requirement for serial init,   that happens properly since it prints all after that. - Some would print after relocation at the spl_board_init for   making sure all initialization prior to relocation would happen properly. Also debug uart on these cases would be available before relocation. So debug support is available in before and after relocation. Rockchip SPL is following formar step to print the banner at the end of board_init_f. To support various custom use cases in SPL like leds, environment, board detections later options like printing the banner after relocation would be a better option. Printing banner would also help to support debugging availability between relocation codes, like debug uart available before relocation and banner availability after relation. By demonstrating all the above use cases, this patch is trying to print the SPL banner after relocation. Signed-off-by: Jagan Teki Tested-by: Suniel Mahesh --- Changes for v3: - new patch arch/arm/mach-rockchip/rk3399/rk3399.c | 2 ++ arch/arm/mach-rockchip/spl.c | 1 - 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index 681f80f339..af4b0e271b 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -279,6 +279,8 @@ void spl_board_init(void) { /* board specific spl init */ rk_spl_board_init(); + + preloader_console_init(); } #endif diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c index cddf4fd3d5..1c2dca8a72 100644 --- a/arch/arm/mach-rockchip/spl.c +++ b/arch/arm/mach-rockchip/spl.c @@ -147,7 +147,6 @@ void board_init_f(ulong dummy) gd->ram_top = gd->ram_base + get_effective_memsize(); gd->ram_top = board_get_usable_ram_top(gd->ram_size); #endif - preloader_console_init(); } #ifdef CONFIG_SPL_LOAD_FIT From patchwork Mon Jun 8 18:31:42 2020 Content-Type: text/plain; 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[209.85.220.65]) by mx.google.com with SMTPS id x1sor11347432plr.50.2020.06.08.11.32.10 for (Google Transport Security); Mon, 08 Jun 2020 11:32:10 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:902:fe01:: with SMTP id g1mr127225plj.254.1591641129758; Mon, 08 Jun 2020 11:32:09 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:9043:af95:b7b4:3ade]) by smtp.gmail.com with ESMTPSA id k29sm6680961pgf.77.2020.06.08.11.32.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jun 2020 11:32:09 -0700 (PDT) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: Suniel Mahesh , U-Boot-Denx , linux-rockchip@lists.infradead.org, linux-amarula , Jagan Teki Subject: [PATCH v3 3/5] roc-rk3399-pc: Move leds setup in SPL Date: Mon, 8 Jun 2020 14:31:42 -0400 Message-Id: <20200608183144.26809-4-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200608183144.26809-1-jagan@amarulasolutions.com> References: <20200608183144.26809-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=XzaGTtGK; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , roc-rk3399-pc has some specific requirements to support LEDS, environment. board detection and etc prior to U-Boot proper. So as of now SPL would be a better stage for these custom board requirements to support unlike TPL. Adding few of these custom requirements like LEDS in TPL would require extra code pulling and also the size of TPL can grow. So, this patch moves the leds code from TPL into SPL after relocation. Signed-off-by: Jagan Teki Tested-by: Suniel Mahesh --- Changes for v3: - new patch arch/arm/mach-rockchip/tpl.c | 7 ------- board/firefly/roc-pc-rk3399/Makefile | 4 ++++ board/firefly/roc-pc-rk3399/roc-pc-rk3399.c | 21 ------------------- board/firefly/roc-pc-rk3399/spl.c | 23 +++++++++++++++++++++ configs/roc-pc-mezzanine-rk3399_defconfig | 2 +- configs/roc-pc-rk3399_defconfig | 2 +- 6 files changed, 29 insertions(+), 30 deletions(-) create mode 100644 board/firefly/roc-pc-rk3399/spl.c diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c index 88f80b05a9..cc908e1b0e 100644 --- a/arch/arm/mach-rockchip/tpl.c +++ b/arch/arm/mach-rockchip/tpl.c @@ -43,18 +43,11 @@ __weak void rockchip_stimer_init(void) TIMER_CONTROL_REG); } -__weak int board_early_init_f(void) -{ - return 0; -} - void board_init_f(ulong dummy) { struct udevice *dev; int ret; - board_early_init_f(); - #if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL_SUPPORT) /* * Debug UART can be used from here if required: diff --git a/board/firefly/roc-pc-rk3399/Makefile b/board/firefly/roc-pc-rk3399/Makefile index 29c79b25d7..3a9c4c744d 100644 --- a/board/firefly/roc-pc-rk3399/Makefile +++ b/board/firefly/roc-pc-rk3399/Makefile @@ -4,4 +4,8 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else obj-y += roc-pc-rk3399.o +endif diff --git a/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c b/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c index 7c3a803654..581cdcd3b0 100644 --- a/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c +++ b/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c @@ -6,13 +6,8 @@ #include #include #include -#include #include -#include -#include -#include -#ifndef CONFIG_SPL_BUILD int board_early_init_f(void) { struct udevice *regulator; @@ -30,19 +25,3 @@ int board_early_init_f(void) out: return 0; } -#endif - -#if defined(CONFIG_TPL_BUILD) - -#define GPIO0_BASE 0xff720000 - -int board_early_init_f(void) -{ - struct rockchip_gpio_regs * const gpio0 = (void *)GPIO0_BASE; - - /* Turn on red LED, indicating full power mode */ - spl_gpio_output(gpio0, GPIO(BANK_B, 5), 1); - - return 0; -} -#endif diff --git a/board/firefly/roc-pc-rk3399/spl.c b/board/firefly/roc-pc-rk3399/spl.c new file mode 100644 index 0000000000..a7664c6b86 --- /dev/null +++ b/board/firefly/roc-pc-rk3399/spl.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2020 Amarula Solutions(India) + */ + +#include +#include +#include + +#define GPIO0_BASE 0xff720000 + +static void led_setup(void) +{ + struct rockchip_gpio_regs * const gpio0 = (void *)GPIO0_BASE; + + /* Turn on red LED, indicating full power mode */ + spl_gpio_output(gpio0, GPIO(BANK_B, 5), 1); +} + +void rk_spl_board_init(void) +{ + led_setup(); +} diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig index 03ba519af1..8ad74dc408 100644 --- a/configs/roc-pc-mezzanine-rk3399_defconfig +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_GPIO_SUPPORT=y CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_ENV_SECT_SIZE=0x1000 @@ -19,7 +20,6 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_SPI_LOAD=y CONFIG_TPL=y -CONFIG_TPL_GPIO_SUPPORT=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index b59b54bd89..6fd06d6381 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_GPIO_SUPPORT=y CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_ENV_SECT_SIZE=0x1000 @@ -19,7 +20,6 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_SPI_LOAD=y CONFIG_TPL=y -CONFIG_TPL_GPIO_SUPPORT=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y From patchwork Mon Jun 8 18:31:43 2020 Content-Type: text/plain; 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[209.85.220.65]) by mx.google.com with SMTPS id l1sor11499781plb.41.2020.06.08.11.32.15 for (Google Transport Security); Mon, 08 Jun 2020 11:32:15 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:902:7297:: with SMTP id d23mr125758pll.282.1591641134981; Mon, 08 Jun 2020 11:32:14 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:9043:af95:b7b4:3ade]) by smtp.gmail.com with ESMTPSA id k29sm6680961pgf.77.2020.06.08.11.32.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jun 2020 11:32:14 -0700 (PDT) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: Suniel Mahesh , U-Boot-Denx , linux-rockchip@lists.infradead.org, linux-amarula , Jagan Teki Subject: [PATCH v3 4/5] rockchip: Separate the reset cause from display cpuinfo Date: Mon, 8 Jun 2020 14:31:43 -0400 Message-Id: <20200608183144.26809-5-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200608183144.26809-1-jagan@amarulasolutions.com> References: <20200608183144.26809-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="oN/BomlY"; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , reset cause is a generic functionality based on the soc cru registers in rockchip. This can be used for printing the cause of reset in cpuinfo or some other place where reset cause is needed.  Other than cpuinfo, reset cause can also be using during bootcount for checking the specific reset cause and glow the led based on the reset cause. So, let's separate the reset cause code from cpuinfo, and add a check to build it for rk3399, rk3288 since these two soc are supporting reset cause as of now. Signed-off-by: Jagan Teki Tested-by: Suniel Mahesh --- Changes for v3: - none arch/arm/include/asm/arch-rockchip/cru.h | 2 ++ arch/arm/mach-rockchip/Makefile | 5 ++++- arch/arm/mach-rockchip/cpu-info.c | 20 ++++++++++++-------- 3 files changed, 18 insertions(+), 9 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h index 5eb17f9d55..317eb61049 100644 --- a/arch/arm/include/asm/arch-rockchip/cru.h +++ b/arch/arm/include/asm/arch-rockchip/cru.h @@ -31,4 +31,6 @@ enum { #define MHz 1000000 +char *get_reset_cause(void); + #endif /* _ROCKCHIP_CLOCK_H */ diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 5b38526fe0..ef4898e00c 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -15,6 +15,10 @@ obj-tpl-$(CONFIG_ROCKCHIP_PX30) += px30-board-tpl.o obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o +ifeq ($(CONFIG_ROCKCHIP_RK3288)$(CONFIG_ROCKCHIP_RK3399), y) +obj-y += cpu-info.o +endif + ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) # Always include boot_mode.o, as we bypass it (i.e. turn it off) @@ -22,7 +26,6 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) # we can have the preprocessor correctly recognise both 0x0 and 0 # meaning "turn it off". obj-y += boot_mode.o -obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o obj-$(CONFIG_MISC_INIT_R) += misc.o endif diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c index 21ca9dedce..76a840e2c3 100644 --- a/arch/arm/mach-rockchip/cpu-info.c +++ b/arch/arm/mach-rockchip/cpu-info.c @@ -13,7 +13,7 @@ #include #include -static char *get_reset_cause(void) +char *get_reset_cause(void) { struct rockchip_cru *cru = rockchip_get_cru(); char *cause = NULL; @@ -41,12 +41,6 @@ static char *get_reset_cause(void) cause = "unknown reset"; } - /** - * reset_reason env is used by rk3288, due to special use case - * to figure it the boot behavior. so keep this as it is. - */ - env_set("reset_reason", cause); - /* * Clear glb_rst_st, so we can determine the last reset cause * for following resets. @@ -56,12 +50,22 @@ static char *get_reset_cause(void) return cause; } +#ifdef CONFIG_DISPLAY_CPUINFO int print_cpuinfo(void) { + char *cause = get_reset_cause(); + printf("SoC: Rockchip %s\n", CONFIG_SYS_SOC); - printf("Reset cause: %s\n", get_reset_cause()); + printf("Reset cause: %s\n", cause); + + /** + * reset_reason env is used by rk3288, due to special use case + * to figure it the boot behavior. so keep this as it is. + */ + env_set("reset_reason", cause); /* TODO print operating temparature and clock */ return 0; } +#endif From patchwork Mon Jun 8 18:31:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1350 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pl1-f199.google.com (mail-pl1-f199.google.com [209.85.214.199]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 6BE3C3F06D for ; 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[209.85.220.65]) by mx.google.com with SMTPS id x12sor11647829plv.32.2020.06.08.11.32.20 for (Google Transport Security); Mon, 08 Jun 2020 11:32:20 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:902:bcc9:: with SMTP id o9mr94687pls.335.1591641140373; Mon, 08 Jun 2020 11:32:20 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:9043:af95:b7b4:3ade]) by smtp.gmail.com with ESMTPSA id k29sm6680961pgf.77.2020.06.08.11.32.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jun 2020 11:32:19 -0700 (PDT) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: Suniel Mahesh , U-Boot-Denx , linux-rockchip@lists.infradead.org, linux-amarula , Jagan Teki Subject: [PATCH v3 5/5] roc-rk3399-pc: Set LED only during POR and pwr_key=y Date: Mon, 8 Jun 2020 14:31:44 -0400 Message-Id: <20200608183144.26809-6-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200608183144.26809-1-jagan@amarulasolutions.com> References: <20200608183144.26809-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="VoxPyd/q"; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , ROC-RK3399-PC has specific set of configurations for on-board led setup. Due to easiness for user to know the state of the board roc-rk339-pc board code will setup the low power led on/off, and waiting for user to press power key and then glow full power led. All this needs to happen only during power-on-reset not for soft reset or WDT. Also, it is not a proper usage to ask the user to press the Power key if the board connected remotely, so add the environment variable 'pwr_key' to check as well. So, user need to press Power key only - during POR - pwr_key=y Tested-by: Suniel Mahesh Signed-off-by: Jagan Teki --- Changes for v3: - new patch board/firefly/roc-pc-rk3399/spl.c | 35 ++++++++++++++++++++++- configs/roc-pc-mezzanine-rk3399_defconfig | 4 ++- configs/roc-pc-rk3399_defconfig | 4 ++- 3 files changed, 40 insertions(+), 3 deletions(-) diff --git a/board/firefly/roc-pc-rk3399/spl.c b/board/firefly/roc-pc-rk3399/spl.c index a7664c6b86..771a7fb2f2 100644 --- a/board/firefly/roc-pc-rk3399/spl.c +++ b/board/firefly/roc-pc-rk3399/spl.c @@ -4,16 +4,49 @@ */ #include +#include #include +#include +#include #include +#include +#define PMUGRF_BASE 0xff320000 #define GPIO0_BASE 0xff720000 +/** + * LED setup for roc-rk3399-pc + * + * 1. Set the low power leds (only during POR, pwr_key env is 'y') + * glow yellow LED, termed as low power + * poll for on board power key press + * once powe key pressed, turn off yellow + * 2. Turn on red LED, indicating full power mode + */ static void led_setup(void) { struct rockchip_gpio_regs * const gpio0 = (void *)GPIO0_BASE; + struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE; + bool press_pwr_key = false; + + if (IS_ENABLED(CONFIG_SPL_ENV_SUPPORT)) { + env_init(); + env_load(); + if (env_get_yesno("pwr_key") == 1) + press_pwr_key = true; + } + + if (press_pwr_key && !strcmp(get_reset_cause(), "POR")) { + spl_gpio_output(gpio0, GPIO(BANK_A, 2), 1); + + spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_A, 5), + GPIO_PULL_NORMAL); + while (readl(&gpio0->ext_port) & 0x20) + ; + + spl_gpio_output(gpio0, GPIO(BANK_A, 2), 0); + } - /* Turn on red LED, indicating full power mode */ spl_gpio_output(gpio0, GPIO(BANK_B, 5), 1); } diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig index 8ad74dc408..d3369063ea 100644 --- a/configs/roc-pc-mezzanine-rk3399_defconfig +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -17,7 +17,8 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc-mezzanine.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x20000 +CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y @@ -32,6 +33,7 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3399-roc-pc-mezzanine" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index 6fd06d6381..0650b941c2 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -17,7 +17,8 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x20000 +CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y @@ -31,6 +32,7 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3399-roc-pc" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y