From patchwork Wed Jun 10 10:36:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1356 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pf1-f200.google.com (mail-pf1-f200.google.com [209.85.210.200]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id EEEF73F066 for ; Wed, 10 Jun 2020 12:37:21 +0200 (CEST) Received: by mail-pf1-f200.google.com with SMTP id i7sf1518464pfk.3 for ; Wed, 10 Jun 2020 03:37:21 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1591785440; cv=pass; d=google.com; s=arc-20160816; b=jmVEIi4O9SvEMhSD4t/kqfyFp+T+XQm2phlOhzMsyN67dKpmqTfe4qlMxdW2Jf6Oty qB3Xr5beGRmi3hu3WsPlKcVUXLfp5B+7NirfemipYaQzEQhEsf6+tAo7LlXtX8twD37L Gb5RYK7vam4XcBAxMXIMBPizeVDmTDxfLDRAbSBfw5jeROC3bix7nzbFsgak2oZd8v8E vST9DeZuTgUt/nWMW/aGVxhe95rp5inoT8M3BCPe3/q7ynbjWr+c56UyfxQp9FsB1w2L gYNymiv/ux+Pi+REdXqfNkx3OzbBz68swbZi/DB2tqpGfMf0aWJAARyxj7FeqVWmkFjs K0Ww== ARC-Message-Signature: i=2; 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[209.85.220.65]) by mx.google.com with SMTPS id mp5sor6896557pjb.32.2020.06.10.03.37.19 for (Google Transport Security); Wed, 10 Jun 2020 03:37:19 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:90b:2042:: with SMTP id ji2mr2489616pjb.68.1591785438843; Wed, 10 Jun 2020 03:37:18 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:9daa:1b72:7bd0:50df]) by smtp.gmail.com with ESMTPSA id x191sm12454754pfd.37.2020.06.10.03.37.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2020 03:37:17 -0700 (PDT) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: Tom Cubie , Suniel Mahesh , U-Boot-Denx , linux-rockchip@lists.infradead.org, linux-amarula , Jagan Teki Subject: [PATCH 1/4] arm64: dts: rockchip: Sync v5.7-rc1 rk3399pro.dtsi Date: Wed, 10 Jun 2020 16:06:55 +0530 Message-Id: <20200610103658.96678-2-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200610103658.96678-1-jagan@amarulasolutions.com> References: <20200610103658.96678-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=PtXicEfr; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Sync linux-next v5.7-rc1 rk3399pro.dtsi. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/rk3399pro.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 arch/arm/dts/rk3399pro.dtsi diff --git a/arch/arm/dts/rk3399pro.dtsi b/arch/arm/dts/rk3399pro.dtsi new file mode 100644 index 0000000000..bb5ebf6608 --- /dev/null +++ b/arch/arm/dts/rk3399pro.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. + +#include "rk3399.dtsi" + +/ { + compatible = "rockchip,rk3399pro"; +}; + +/* Default to enabled since AP talk to NPU part over pcie */ +&pcie_phy { + status = "okay"; +}; + +/* Default to enabled since AP talk to NPU part over pcie */ +&pcie0 { + ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn_cpm>; + status = "okay"; +}; From patchwork Wed Jun 10 10:36:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1357 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pj1-f71.google.com (mail-pj1-f71.google.com [209.85.216.71]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 03B1D3F066 for ; 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[209.85.220.65]) by mx.google.com with SMTPS id 142sor16694929pgg.4.2020.06.10.03.37.23 for (Google Transport Security); Wed, 10 Jun 2020 03:37:23 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a65:4903:: with SMTP id p3mr2085845pgs.318.1591785443279; Wed, 10 Jun 2020 03:37:23 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:9daa:1b72:7bd0:50df]) by smtp.gmail.com with ESMTPSA id x191sm12454754pfd.37.2020.06.10.03.37.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2020 03:37:22 -0700 (PDT) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: Tom Cubie , Suniel Mahesh , U-Boot-Denx , linux-rockchip@lists.infradead.org, linux-amarula , Jagan Teki Subject: [PATCH 2/4] arm64: dts: rockchip: Sync v5.7-rc1 VMARC RK3399Pro SOM Date: Wed, 10 Jun 2020 16:06:56 +0530 Message-Id: <20200610103658.96678-3-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200610103658.96678-1-jagan@amarulasolutions.com> References: <20200610103658.96678-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=X7+3yqY+; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , VMARC RK3399Pro SOM is a standard SMARC SOM design with Rockchip RK3399Pro SoC, which is designed by Vamrs. Specification: - Rockchip RK3399Pro - PMIC: RK809-3 - SD slot, 16GiB eMMC - 2xUSB-2.0, 1xUSB3.0 - USB-C for power supply - Ethernet, PCIe - HDMI, MIPI-DSI/CSI, eDP Add initial support for VMARC RK3399Pro SOM, this would use with associated carrier board. Sync this dtsi from linux-next v5.7-rc1. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/rk3399pro-vmarc-som.dtsi | 333 ++++++++++++++++++++++++++ 1 file changed, 333 insertions(+) create mode 100644 arch/arm/dts/rk3399pro-vmarc-som.dtsi diff --git a/arch/arm/dts/rk3399pro-vmarc-som.dtsi b/arch/arm/dts/rk3399pro-vmarc-som.dtsi new file mode 100644 index 0000000000..0a516334f1 --- /dev/null +++ b/arch/arm/dts/rk3399pro-vmarc-som.dtsi @@ -0,0 +1,333 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2019 Vamrs Limited + * Copyright (c) 2019 Amarula Solutions(India) + */ + +#include +#include +#include + +/ { + compatible = "vamrs,rk3399pro-vmarc-som", "rockchip,rk3399pro"; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <180>; + i2c-scl-falling-time-ns = <30>; + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = ; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc_buck5>; + vcc6-supply = <&vcc_buck5>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG4 { + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_buck5: DCDC_REG5 { + regulator-name = "vcc_buck5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2200000>; + }; + }; + + vcca_0v9: LDO_REG1 { + regulator-name = "vcca_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: LDO_REG2 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_0v9: LDO_REG3 { + regulator-name = "vcc_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vcca_1v8: LDO_REG4 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <1850000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* + * As per BSP, but schematic not showing any regulator + * pin for LD05. + */ + vdd1v5_dvp: LDO_REG5 { + regulator-name = "vdd1v5_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_3v0: LDO_REG7 { + regulator-name = "vccio_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG8 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* + * As per BSP, but schematic not showing any regulator + * pin for LD09. + */ + vcc_sd: LDO_REG9 { + regulator-name = "vcc_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v0_usb2: SWITCH_REG1 { + regulator-name = "vcc5v0_usb2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <5000000>; + }; + }; + + vccio_3v3: vcc_lan: SWITCH_REG2 { + regulator-name = "vccio_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&io_domains { + status = "okay"; + bt656-supply = <&vcca_1v8>; + sdmmc-supply = <&vccio_sd>; + gpio1830-supply = <&vccio_3v0>; +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_1v8>; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&tsadc { + status = "okay"; + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <1>; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 RK_PC2 0 &pcfg_pull_up>; + }; + }; +}; From patchwork Wed Jun 10 10:36:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1358 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pj1-f69.google.com (mail-pj1-f69.google.com [209.85.216.69]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 374143F066 for ; Wed, 10 Jun 2020 12:37:30 +0200 (CEST) Received: by mail-pj1-f69.google.com with SMTP id l62sf1456766pje.9 for ; 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[209.85.220.65]) by mx.google.com with SMTPS id 23sor2591879pgx.57.2020.06.10.03.37.28 for (Google Transport Security); Wed, 10 Jun 2020 03:37:28 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a63:550d:: with SMTP id j13mr2112855pgb.139.1591785448097; Wed, 10 Jun 2020 03:37:28 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:9daa:1b72:7bd0:50df]) by smtp.gmail.com with ESMTPSA id x191sm12454754pfd.37.2020.06.10.03.37.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2020 03:37:27 -0700 (PDT) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: Tom Cubie , Suniel Mahesh , U-Boot-Denx , linux-rockchip@lists.infradead.org, linux-amarula , Jagan Teki Subject: [PATCH 3/4] ARM: dts: rockchip: Sync v5.7-rc1 Radxa Dalang Carrier Date: Wed, 10 Jun 2020 16:06:57 +0530 Message-Id: <20200610103658.96678-4-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200610103658.96678-1-jagan@amarulasolutions.com> References: <20200610103658.96678-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=rTCjh+Hf; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Carrier board often referred as baseboard. For making complete SBC or any other industrial boards, these carrier boards will be used with associated SOMs. Radxa has Dalang carrier board which supports on-board peripherals, ports like USB-2.0, USB-3.0, HDMI, MIPI DSI/CSI, eDP, Ethernet, WiFi, PCIe, USB-C, 40-Pin GPIO header and etc. Right now Dalang carrier board is used with two SBC-variants: Rock Pi N10 => VMARC RK3399Por SOM + Dalang carrier board Rock Pi N8 => VMARC RK3288 SOM + Dalang carrier board(+codec) So add this carrier board dtsi as a separate file in ARM directory, so-that the same can reuse it in both rk3288, rk3399pro variants of Rockchip SOMs. Sync this dtsi from linux-next v5.7-rc1. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- .../dts/rockchip-radxa-dalang-carrier.dtsi | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi diff --git a/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi b/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi new file mode 100644 index 0000000000..df3712aedf --- /dev/null +++ b/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2019 Radxa Limited + * Copyright (c) 2019 Amarula Solutions(India) + */ + +#include + +/ { + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&gmac { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + i2c-scl-rising-time-ns = <140>; + i2c-scl-falling-time-ns = <30>; +}; + +&i2c2 { + status = "okay"; + clock-frequency = <400000>; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio4>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + vqmmc-supply = <&vccio_sd>; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = + <4 RK_PD6 0 &pcfg_pull_up>; + }; + }; +}; From patchwork Wed Jun 10 10:36:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1359 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pg1-f199.google.com (mail-pg1-f199.google.com [209.85.215.199]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id DFC0B3F066 for ; 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[209.85.220.65]) by mx.google.com with SMTPS id b4sor18186686plz.30.2020.06.10.03.37.32 for (Google Transport Security); Wed, 10 Jun 2020 03:37:32 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:902:8496:: with SMTP id c22mr2523993plo.57.1591785452416; Wed, 10 Jun 2020 03:37:32 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:9daa:1b72:7bd0:50df]) by smtp.gmail.com with ESMTPSA id x191sm12454754pfd.37.2020.06.10.03.37.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2020 03:37:31 -0700 (PDT) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: Tom Cubie , Suniel Mahesh , U-Boot-Denx , linux-rockchip@lists.infradead.org, linux-amarula , Jagan Teki Subject: [PATCH 4/4] arm64: dts: rockchip: Add Radxa Rock Pi N10 initial support Date: Wed, 10 Jun 2020 16:06:58 +0530 Message-Id: <20200610103658.96678-5-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200610103658.96678-1-jagan@amarulasolutions.com> References: <20200610103658.96678-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=aIOHuNko; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Rock Pi N10 is a Rockchip RK3399Pro based SBC, which has - VMARC RK3399Pro SOM (as per SMARC standard) from Vamrs. - Compatible carrier board from Radxa. VAMRC RK3399Pro SOM need to mount on top of radxa dalang carrier board for making Rock Pi N10 SBC. So, add initial support for Rock Pi N10 by including rk3399, rk3399pro vamrc-som and raxda dalang carrier board dtsi files. rk3399pro-rock-pi-n10.dts was synced from linux-next v5.7-rc1. Tested - ROCK PI N10 Model B - ROCK PI N10 Model C - Boot from SD Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 3 +- .../arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi | 7 +++ arch/arm/dts/rk3399pro-rock-pi-n10.dts | 18 ++++++++ arch/arm/dts/rk3399pro-u-boot.dtsi | 6 +++ board/rockchip/evb_rk3399/MAINTAINERS | 6 +++ configs/rock-pi-n10-rk3399pro_defconfig | 46 +++++++++++++++++++ 6 files changed, 85 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399pro-rock-pi-n10.dts create mode 100644 arch/arm/dts/rk3399pro-u-boot.dtsi create mode 100644 configs/rock-pi-n10-rk3399pro_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9900b44274..07dfe06230 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -136,7 +136,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-roc-pc-mezzanine.dtb \ rk3399-rock-pi-4.dtb \ rk3399-rock960.dtb \ - rk3399-rockpro64.dtb + rk3399-rockpro64.dtb \ + rk3399pro-rock-pi-n10.dtb dtb-$(CONFIG_ROCKCHIP_RV1108) += \ rv1108-elgin-r1.dtb \ diff --git a/arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi b/arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi new file mode 100644 index 0000000000..946a0230db --- /dev/null +++ b/arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki + */ + +#include "rk3399pro-u-boot.dtsi" +#include "rk3399-sdram-lpddr3-4GB-1600.dtsi" diff --git a/arch/arm/dts/rk3399pro-rock-pi-n10.dts b/arch/arm/dts/rk3399pro-rock-pi-n10.dts new file mode 100644 index 0000000000..6ac2d4d721 --- /dev/null +++ b/arch/arm/dts/rk3399pro-rock-pi-n10.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2019 Radxa Limited + * Copyright (c) 2019 Amarula Solutions(India) + */ + +/dts-v1/; +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" +#include "rk3399pro-vmarc-som.dtsi" +#include + +/ { + model = "Radxa ROCK Pi N10"; + compatible = "radxa,rockpi-n10", "vamrs,rk3399pro-vmarc-som", + "rockchip,rk3399pro"; +}; diff --git a/arch/arm/dts/rk3399pro-u-boot.dtsi b/arch/arm/dts/rk3399pro-u-boot.dtsi new file mode 100644 index 0000000000..7bddc3acdb --- /dev/null +++ b/arch/arm/dts/rk3399pro-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki + */ + +#include "rk3399-u-boot.dtsi" diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index 792df1087f..578638a58b 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -68,3 +68,9 @@ M: Jagan Teki S: Maintained F: configs/rock-pi-4-rk3399_defconfig F: arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi + +ROCK-PI-N10 +M: Jagan Teki +S: Maintained +F: configs/rock-pi-n10-rk3399pro_defconfig +F: arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi diff --git a/configs/rock-pi-n10-rk3399pro_defconfig b/configs/rock-pi-n10-rk3399pro_defconfig new file mode 100644 index 0000000000..c705ce01ce --- /dev/null +++ b/configs/rock-pi-n10-rk3399pro_defconfig @@ -0,0 +1,46 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_EVB_RK3399=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399pro-rock-pi-n10.dtb" +CONFIG_MISC_INIT_R=y +CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_TPL=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399pro-rock-pi-n10" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_ERRNO_STR=y