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[209.85.220.65]) by mx.google.com with SMTPS id p5sor2745212ilq.136.2020.06.18.09.07.59 for (Google Transport Security); Thu, 18 Jun 2020 09:07:59 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:902:7088:: with SMTP id z8mr4394536plk.320.1592496478973; Thu, 18 Jun 2020 09:07:58 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:b0c7:f192:869b:df87]) by smtp.gmail.com with ESMTPSA id u4sm3264943pfl.102.2020.06.18.09.07.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jun 2020 09:07:58 -0700 (PDT) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: Suniel Mahesh , U-Boot-Denx , linux-rockchip@lists.infradead.org, linux-amarula , Jagan Teki Subject: [PATCH v4 1/5] rockchip: spl: Add spl_board_init Date: Thu, 18 Jun 2020 21:09:44 +0530 Message-Id: <20200618153948.218506-2-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200618153948.218506-1-jagan@amarulasolutions.com> References: <20200618153948.218506-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=IYsmF42R; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , spl_board_init is a proper location and common practice option to have a custom board initialization code after relocation in SPL. This patch add the feasibility to add the custom SPL board initzlaization throughout rockchip platforms and adjust existing the spl board code on respective boards. Signed-off-by: Jagan Teki --- Changes for v4: - new patch arch/arm/Kconfig | 1 + arch/arm/mach-rockchip/Kconfig | 2 - arch/arm/mach-rockchip/rk3188/rk3188.c | 2 +- arch/arm/mach-rockchip/rk3399/rk3399.c | 57 ----------------- arch/arm/mach-rockchip/spl.c | 10 +++ board/firefly/firefly-rk3288/firefly-rk3288.c | 2 +- board/phytec/phycore_rk3288/phycore-rk3288.c | 2 +- .../puma_rk3399/puma-rk3399.c | 61 +++++++++++++++++++ 8 files changed, 75 insertions(+), 62 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index edc9e38c6c..57ddf15cb3 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1679,6 +1679,7 @@ config ARCH_ROCKCHIP select ENABLE_ARM_SOC_BOOT0_HOOK select OF_CONTROL select SPI + select SPL_BOARD_INIT if SPL select SPL_DM if SPL select SYS_MALLOC_F select SYS_THUMB_BUILD if !ARM64 diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 0cb1f23d0f..b1008a5058 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -49,7 +49,6 @@ config ROCKCHIP_RK3128 config ROCKCHIP_RK3188 bool "Support Rockchip RK3188" select CPU_V7A - select SPL_BOARD_INIT if SPL select SUPPORT_SPL select SPL select SPL_CLK @@ -208,7 +207,6 @@ config ROCKCHIP_RK3399 select SPL select SPL_ATF select SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF - select SPL_BOARD_INIT if SPL select SPL_LOAD_FIT select SPL_CLK if SPL select SPL_PINCTRL if SPL diff --git a/arch/arm/mach-rockchip/rk3188/rk3188.c b/arch/arm/mach-rockchip/rk3188/rk3188.c index ef57dfd761..0c0fe84ad5 100644 --- a/arch/arm/mach-rockchip/rk3188/rk3188.c +++ b/arch/arm/mach-rockchip/rk3188/rk3188.c @@ -111,7 +111,7 @@ static int setup_led(void) return 0; } -void spl_board_init(void) +void rk_spl_board_init(void) { int ret; diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index 4fda93b152..b53a111769 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -217,61 +217,4 @@ void spl_perform_fixups(struct spl_image_info *spl_image) "u-boot,spl-boot-device", boot_ofpath); } -#if defined(SPL_GPIO_SUPPORT) -static void rk3399_force_power_on_reset(void) -{ - ofnode node; - struct gpio_desc sysreset_gpio; - - debug("%s: trying to force a power-on reset\n", __func__); - - node = ofnode_path("/config"); - if (!ofnode_valid(node)) { - debug("%s: no /config node?\n", __func__); - return; - } - - if (gpio_request_by_name_nodev(node, "sysreset-gpio", 0, - &sysreset_gpio, GPIOD_IS_OUT)) { - debug("%s: could not find a /config/sysreset-gpio\n", __func__); - return; - } - - dm_gpio_set_value(&sysreset_gpio, 1); -} -#endif - -void spl_board_init(void) -{ -#if defined(SPL_GPIO_SUPPORT) - struct rockchip_cru *cru = rockchip_get_cru(); - - /* - * The RK3399 resets only 'almost all logic' (see also in the TRM - * "3.9.4 Global software reset"), when issuing a software reset. - * This may cause issues during boot-up for some configurations of - * the application software stack. - * - * To work around this, we test whether the last reset reason was - * a power-on reset and (if not) issue an overtemp-reset to reset - * the entire module. - * - * While this was previously fixed by modifying the various places - * that could generate a software reset (e.g. U-Boot's sysreset - * driver, the ATF or Linux), we now have it here to ensure that - * we no longer have to track this through the various components. - */ - if (cru->glb_rst_st != 0) - rk3399_force_power_on_reset(); -#endif - -#if defined(SPL_DM_REGULATOR) - /* - * Turning the eMMC and SPI back on (if disabled via the Qseven - * BIOS_ENABLE) signal is done through a always-on regulator). - */ - if (regulators_enable_boot_on(false)) - debug("%s: Cannot enable boot on regulator\n", __func__); -#endif -} #endif diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c index cddf4fd3d5..d4c83a1119 100644 --- a/arch/arm/mach-rockchip/spl.c +++ b/arch/arm/mach-rockchip/spl.c @@ -150,6 +150,16 @@ void board_init_f(ulong dummy) preloader_console_init(); } +__weak void rk_spl_board_init(void) +{ +} + +void spl_board_init(void) +{ + /* board specific spl init */ + rk_spl_board_init(); +} + #ifdef CONFIG_SPL_LOAD_FIT int __weak board_fit_config_name_match(const char *name) { diff --git a/board/firefly/firefly-rk3288/firefly-rk3288.c b/board/firefly/firefly-rk3288/firefly-rk3288.c index 1965985a0f..96d44b1d9f 100644 --- a/board/firefly/firefly-rk3288/firefly-rk3288.c +++ b/board/firefly/firefly-rk3288/firefly-rk3288.c @@ -31,7 +31,7 @@ static int setup_led(void) return 0; } -void spl_board_init(void) +void rk_spl_board_init(void) { int ret; diff --git a/board/phytec/phycore_rk3288/phycore-rk3288.c b/board/phytec/phycore_rk3288/phycore-rk3288.c index ecc73227a0..b33070f62e 100644 --- a/board/phytec/phycore_rk3288/phycore-rk3288.c +++ b/board/phytec/phycore_rk3288/phycore-rk3288.c @@ -104,7 +104,7 @@ static int phycore_init(void) } #endif -void spl_board_init(void) +void rk_spl_board_init(void) { #if !defined(CONFIG_SPL_OF_PLATDATA) int ret; diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c index deeba3084a..fd5cdd9ea1 100644 --- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c +++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c @@ -152,3 +152,64 @@ void get_board_serial(struct tag_serialnr *serialnr) serialnr->low = (u32)(serial & 0xffffffff); } #endif + +#if defined(CONFIG_SPL_BUILD) + +#if defined(SPL_GPIO_SUPPORT) +static void rk3399_force_power_on_reset(void) +{ + ofnode node; + struct gpio_desc sysreset_gpio; + + debug("%s: trying to force a power-on reset\n", __func__); + + node = ofnode_path("/config"); + if (!ofnode_valid(node)) { + debug("%s: no /config node?\n", __func__); + return; + } + + if (gpio_request_by_name_nodev(node, "sysreset-gpio", 0, + &sysreset_gpio, GPIOD_IS_OUT)) { + debug("%s: could not find a /config/sysreset-gpio\n", __func__); + return; + } + + dm_gpio_set_value(&sysreset_gpio, 1); +} +#endif + +void rk_spl_board_init(void) +{ +#if defined(SPL_GPIO_SUPPORT) + struct rockchip_cru *cru = rockchip_get_cru(); + + /* + * The RK3399 resets only 'almost all logic' (see also in the TRM + * "3.9.4 Global software reset"), when issuing a software reset. + * This may cause issues during boot-up for some configurations of + * the application software stack. + * + * To work around this, we test whether the last reset reason was + * a power-on reset and (if not) issue an overtemp-reset to reset + * the entire module. + * + * While this was previously fixed by modifying the various places + * that could generate a software reset (e.g. U-Boot's sysreset + * driver, the ATF or Linux), we now have it here to ensure that + * we no longer have to track this through the various components. + */ + if (cru->glb_rst_st != 0) + rk3399_force_power_on_reset(); +#endif + +#if defined(SPL_DM_REGULATOR) + /* + * Turning the eMMC and SPI back on (if disabled via the Qseven + * BIOS_ENABLE) signal is done through a always-on regulator). + */ + if (regulators_enable_boot_on(false)) + debug("%s: Cannot enable boot on regulator\n", __func__); +#endif +} +#endif /* CONFIG_SPL_BUILD */ From patchwork Thu Jun 18 15:39:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1409 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pl1-f200.google.com (mail-pl1-f200.google.com [209.85.214.200]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 07C223F03F for ; Thu, 18 Jun 2020 18:08:06 +0200 (CEST) Received: by mail-pl1-f200.google.com with SMTP id d13sf4177261plr.20 for ; Thu, 18 Jun 2020 09:08:05 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1592496484; cv=pass; d=google.com; s=arc-20160816; b=zAr+cfwox2fUesAQsSJk/Nz6zJIS6LFjOBkYqoi7dtTfE6TmeQyFseRi1mnteQXEU0 giHMYrMMrNBZ13UsBnh9pejKzLOlUanxiRNj/ANHkM3xC7bTFim09gYhQ4T1Rb0kVBlB HY2E0q0zmR/lqhYZPGDhkWtr/Cfe1jtKhmFRVnKkPXdWnPj9VNcE10r8reTYuDPAbRWX Cmcz5FIQOiaPIKZoXkDPJav57YB5oh9tfaMaCG0rf53S4mp3UuRJrHFfmEI3bjPWjkC1 +3+yPNqleXhpe3CLCjDp1zgGOnVqd+5qWxsKcjgF/MY/k8+hICK1VlUd3N7DZCoUinL9 eR8A== ARC-Message-Signature: i=2; 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[209.85.220.65]) by mx.google.com with SMTPS id a8sor4710443plp.19.2020.06.18.09.08.03 for (Google Transport Security); Thu, 18 Jun 2020 09:08:03 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:902:ea8a:: with SMTP id x10mr4325689plb.330.1592496483193; Thu, 18 Jun 2020 09:08:03 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:b0c7:f192:869b:df87]) by smtp.gmail.com with ESMTPSA id u4sm3264943pfl.102.2020.06.18.09.07.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jun 2020 09:08:02 -0700 (PDT) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: Suniel Mahesh , U-Boot-Denx , linux-rockchip@lists.infradead.org, linux-amarula , Jagan Teki Subject: [PATCH v4 2/5] rk3399: spl: Print SPL banner after relocation Date: Thu, 18 Jun 2020 21:09:45 +0530 Message-Id: <20200618153948.218506-3-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200618153948.218506-1-jagan@amarulasolutions.com> References: <20200618153948.218506-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=CLJW58wU; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Usually printing the SPL banner varies between architecture or board codes. - Some would print before relocation at the end board_init_f   for making sure all initialization prior to this would happen   properly. if at all there is a requirement for serial init,   that happens properly since it prints all after that. - Some would print after relocation at the spl_board_init for   making sure all initialization prior to relocation would happen properly. Also debug uart on these cases would be available before relocation. So debug support is available in before and after relocation. Rockchip SPL is following formar step to print the banner at the end of board_init_f. To support various custom use cases in SPL like leds, environment, board detections later options like printing the banner after relocation would be a better option. Printing banner would also help to support debugging availability between relocation codes, like debug uart available before relocation and banner availability after relation. By demonstrating all the above use cases, this patch is trying to print the SPL banner after relocation. Signed-off-by: Jagan Teki Tested-by: Suniel Mahesh --- Changes for v4: - none arch/arm/mach-rockchip/spl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c index d4c83a1119..6d5c058548 100644 --- a/arch/arm/mach-rockchip/spl.c +++ b/arch/arm/mach-rockchip/spl.c @@ -147,7 +147,6 @@ void board_init_f(ulong dummy) gd->ram_top = gd->ram_base + get_effective_memsize(); gd->ram_top = board_get_usable_ram_top(gd->ram_size); #endif - preloader_console_init(); } __weak void rk_spl_board_init(void) @@ -158,6 +157,8 @@ void spl_board_init(void) { /* board specific spl init */ rk_spl_board_init(); + + preloader_console_init(); } #ifdef CONFIG_SPL_LOAD_FIT From patchwork Thu Jun 18 15:39:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1410 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pj1-f72.google.com (mail-pj1-f72.google.com [209.85.216.72]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 172C53F03F for ; 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[209.85.220.65]) by mx.google.com with SMTPS id lt12sor4073326pjb.38.2020.06.18.09.08.08 for (Google Transport Security); Thu, 18 Jun 2020 09:08:08 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:90b:1009:: with SMTP id gm9mr5016843pjb.213.1592496487794; Thu, 18 Jun 2020 09:08:07 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:b0c7:f192:869b:df87]) by smtp.gmail.com with ESMTPSA id u4sm3264943pfl.102.2020.06.18.09.08.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jun 2020 09:08:07 -0700 (PDT) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: Suniel Mahesh , U-Boot-Denx , linux-rockchip@lists.infradead.org, linux-amarula , Jagan Teki Subject: [PATCH v4 3/5] roc-rk3399-pc: Move leds setup in SPL Date: Thu, 18 Jun 2020 21:09:46 +0530 Message-Id: <20200618153948.218506-4-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200618153948.218506-1-jagan@amarulasolutions.com> References: <20200618153948.218506-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=ZtGWj5LQ; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , roc-rk3399-pc has some specific requirements to support LEDS, environment. board detection and etc prior to U-Boot proper. So as of now SPL would be a better stage for these custom board requirements to support unlike TPL. Adding few of these custom requirements like LEDS in TPL would require extra code pulling and also the size of TPL can grow. So, this patch moves the leds code from TPL into SPL after relocation. Signed-off-by: Jagan Teki Tested-by: Suniel Mahesh --- Changes for v4: - none arch/arm/mach-rockchip/tpl.c | 7 ------- board/firefly/roc-pc-rk3399/Makefile | 4 ++++ board/firefly/roc-pc-rk3399/roc-pc-rk3399.c | 21 ------------------- board/firefly/roc-pc-rk3399/spl.c | 23 +++++++++++++++++++++ configs/roc-pc-mezzanine-rk3399_defconfig | 2 +- configs/roc-pc-rk3399_defconfig | 2 +- 6 files changed, 29 insertions(+), 30 deletions(-) create mode 100644 board/firefly/roc-pc-rk3399/spl.c diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c index 88f80b05a9..cc908e1b0e 100644 --- a/arch/arm/mach-rockchip/tpl.c +++ b/arch/arm/mach-rockchip/tpl.c @@ -43,18 +43,11 @@ __weak void rockchip_stimer_init(void) TIMER_CONTROL_REG); } -__weak int board_early_init_f(void) -{ - return 0; -} - void board_init_f(ulong dummy) { struct udevice *dev; int ret; - board_early_init_f(); - #if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL_SUPPORT) /* * Debug UART can be used from here if required: diff --git a/board/firefly/roc-pc-rk3399/Makefile b/board/firefly/roc-pc-rk3399/Makefile index 29c79b25d7..3a9c4c744d 100644 --- a/board/firefly/roc-pc-rk3399/Makefile +++ b/board/firefly/roc-pc-rk3399/Makefile @@ -4,4 +4,8 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else obj-y += roc-pc-rk3399.o +endif diff --git a/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c b/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c index 7c3a803654..581cdcd3b0 100644 --- a/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c +++ b/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c @@ -6,13 +6,8 @@ #include #include #include -#include #include -#include -#include -#include -#ifndef CONFIG_SPL_BUILD int board_early_init_f(void) { struct udevice *regulator; @@ -30,19 +25,3 @@ int board_early_init_f(void) out: return 0; } -#endif - -#if defined(CONFIG_TPL_BUILD) - -#define GPIO0_BASE 0xff720000 - -int board_early_init_f(void) -{ - struct rockchip_gpio_regs * const gpio0 = (void *)GPIO0_BASE; - - /* Turn on red LED, indicating full power mode */ - spl_gpio_output(gpio0, GPIO(BANK_B, 5), 1); - - return 0; -} -#endif diff --git a/board/firefly/roc-pc-rk3399/spl.c b/board/firefly/roc-pc-rk3399/spl.c new file mode 100644 index 0000000000..a7664c6b86 --- /dev/null +++ b/board/firefly/roc-pc-rk3399/spl.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2020 Amarula Solutions(India) + */ + +#include +#include +#include + +#define GPIO0_BASE 0xff720000 + +static void led_setup(void) +{ + struct rockchip_gpio_regs * const gpio0 = (void *)GPIO0_BASE; + + /* Turn on red LED, indicating full power mode */ + spl_gpio_output(gpio0, GPIO(BANK_B, 5), 1); +} + +void rk_spl_board_init(void) +{ + led_setup(); +} diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig index 595f052cb7..060b4bfecf 100644 --- a/configs/roc-pc-mezzanine-rk3399_defconfig +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_GPIO_SUPPORT=y CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_ENV_SECT_SIZE=0x1000 @@ -20,7 +21,6 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_SPI_LOAD=y CONFIG_TPL=y -CONFIG_TPL_GPIO_SUPPORT=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index 1c4db3443f..9897a52cd8 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_GPIO_SUPPORT=y CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_ENV_SECT_SIZE=0x1000 @@ -20,7 +21,6 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_SPI_LOAD=y CONFIG_TPL=y -CONFIG_TPL_GPIO_SUPPORT=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y From patchwork Thu Jun 18 15:39:47 2020 Content-Type: text/plain; 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[209.85.220.65]) by mx.google.com with SMTPS id n21sor4156699pjt.11.2020.06.18.09.08.12 for (Google Transport Security); Thu, 18 Jun 2020 09:08:12 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:90b:2308:: with SMTP id mt8mr4896758pjb.211.1592496491737; Thu, 18 Jun 2020 09:08:11 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:b0c7:f192:869b:df87]) by smtp.gmail.com with ESMTPSA id u4sm3264943pfl.102.2020.06.18.09.08.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jun 2020 09:08:11 -0700 (PDT) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: Suniel Mahesh , U-Boot-Denx , linux-rockchip@lists.infradead.org, linux-amarula , Jagan Teki Subject: [PATCH v4 4/5] rockchip: Separate the reset cause from display cpuinfo Date: Thu, 18 Jun 2020 21:09:47 +0530 Message-Id: <20200618153948.218506-5-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200618153948.218506-1-jagan@amarulasolutions.com> References: <20200618153948.218506-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=dBUjzQQ0; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , reset cause is a generic functionality based on the soc cru registers in rockchip. This can be used for printing the cause of reset in cpuinfo or some other place where reset cause is needed.  Other than cpuinfo, reset cause can also be using during bootcount for checking the specific reset cause and glow the led based on the reset cause. So, let's separate the reset cause code from cpuinfo, and add a check to build it for rk3399, rk3288 since these two soc are supporting reset cause as of now. Signed-off-by: Jagan Teki Tested-by: Suniel Mahesh --- Changes for v4: - none arch/arm/include/asm/arch-rockchip/cru.h | 2 ++ arch/arm/mach-rockchip/Makefile | 5 ++++- arch/arm/mach-rockchip/cpu-info.c | 20 ++++++++++++-------- 3 files changed, 18 insertions(+), 9 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h index 5eb17f9d55..317eb61049 100644 --- a/arch/arm/include/asm/arch-rockchip/cru.h +++ b/arch/arm/include/asm/arch-rockchip/cru.h @@ -31,4 +31,6 @@ enum { #define MHz 1000000 +char *get_reset_cause(void); + #endif /* _ROCKCHIP_CLOCK_H */ diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 5b38526fe0..ef4898e00c 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -15,6 +15,10 @@ obj-tpl-$(CONFIG_ROCKCHIP_PX30) += px30-board-tpl.o obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o +ifeq ($(CONFIG_ROCKCHIP_RK3288)$(CONFIG_ROCKCHIP_RK3399), y) +obj-y += cpu-info.o +endif + ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) # Always include boot_mode.o, as we bypass it (i.e. turn it off) @@ -22,7 +26,6 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) # we can have the preprocessor correctly recognise both 0x0 and 0 # meaning "turn it off". obj-y += boot_mode.o -obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o obj-$(CONFIG_MISC_INIT_R) += misc.o endif diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c index 21ca9dedce..76a840e2c3 100644 --- a/arch/arm/mach-rockchip/cpu-info.c +++ b/arch/arm/mach-rockchip/cpu-info.c @@ -13,7 +13,7 @@ #include #include -static char *get_reset_cause(void) +char *get_reset_cause(void) { struct rockchip_cru *cru = rockchip_get_cru(); char *cause = NULL; @@ -41,12 +41,6 @@ static char *get_reset_cause(void) cause = "unknown reset"; } - /** - * reset_reason env is used by rk3288, due to special use case - * to figure it the boot behavior. so keep this as it is. - */ - env_set("reset_reason", cause); - /* * Clear glb_rst_st, so we can determine the last reset cause * for following resets. @@ -56,12 +50,22 @@ static char *get_reset_cause(void) return cause; } +#ifdef CONFIG_DISPLAY_CPUINFO int print_cpuinfo(void) { + char *cause = get_reset_cause(); + printf("SoC: Rockchip %s\n", CONFIG_SYS_SOC); - printf("Reset cause: %s\n", get_reset_cause()); + printf("Reset cause: %s\n", cause); + + /** + * reset_reason env is used by rk3288, due to special use case + * to figure it the boot behavior. so keep this as it is. + */ + env_set("reset_reason", cause); /* TODO print operating temparature and clock */ return 0; } +#endif From patchwork Thu Jun 18 15:39:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1412 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pj1-f70.google.com (mail-pj1-f70.google.com [209.85.216.70]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 408103F03F for ; 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[209.85.220.65]) by mx.google.com with SMTPS id s1sor4148008pjz.0.2020.06.18.09.08.16 for (Google Transport Security); Thu, 18 Jun 2020 09:08:16 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:90b:1013:: with SMTP id gm19mr5002759pjb.231.1592496496134; Thu, 18 Jun 2020 09:08:16 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:b0c7:f192:869b:df87]) by smtp.gmail.com with ESMTPSA id u4sm3264943pfl.102.2020.06.18.09.08.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jun 2020 09:08:15 -0700 (PDT) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: Suniel Mahesh , U-Boot-Denx , linux-rockchip@lists.infradead.org, linux-amarula , Jagan Teki Subject: [PATCH v4 5/5] roc-rk3399-pc: Set LED only during POR and pwr_key=y Date: Thu, 18 Jun 2020 21:09:48 +0530 Message-Id: <20200618153948.218506-6-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200618153948.218506-1-jagan@amarulasolutions.com> References: <20200618153948.218506-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=W0hvtWN9; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , ROC-RK3399-PC has specific set of configurations for on-board led setup. Due to easiness for user to know the state of the board roc-rk339-pc board code will setup the low power led on/off, and waiting for user to press power key and then glow full power led. All this needs to happen only during power-on-reset not for soft reset or WDT. Also, it is not a proper usage to ask the user to press the Power key if the board connected remotely, so add the environment variable 'pwr_key' to check as well. So, user need to press Power key only - during POR - pwr_key=y Tested-by: Suniel Mahesh Signed-off-by: Jagan Teki --- Changes for v4: - none board/firefly/roc-pc-rk3399/spl.c | 35 ++++++++++++++++++++++- configs/roc-pc-mezzanine-rk3399_defconfig | 4 ++- configs/roc-pc-rk3399_defconfig | 4 ++- 3 files changed, 40 insertions(+), 3 deletions(-) diff --git a/board/firefly/roc-pc-rk3399/spl.c b/board/firefly/roc-pc-rk3399/spl.c index a7664c6b86..771a7fb2f2 100644 --- a/board/firefly/roc-pc-rk3399/spl.c +++ b/board/firefly/roc-pc-rk3399/spl.c @@ -4,16 +4,49 @@ */ #include +#include #include +#include +#include #include +#include +#define PMUGRF_BASE 0xff320000 #define GPIO0_BASE 0xff720000 +/** + * LED setup for roc-rk3399-pc + * + * 1. Set the low power leds (only during POR, pwr_key env is 'y') + * glow yellow LED, termed as low power + * poll for on board power key press + * once powe key pressed, turn off yellow + * 2. Turn on red LED, indicating full power mode + */ static void led_setup(void) { struct rockchip_gpio_regs * const gpio0 = (void *)GPIO0_BASE; + struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE; + bool press_pwr_key = false; + + if (IS_ENABLED(CONFIG_SPL_ENV_SUPPORT)) { + env_init(); + env_load(); + if (env_get_yesno("pwr_key") == 1) + press_pwr_key = true; + } + + if (press_pwr_key && !strcmp(get_reset_cause(), "POR")) { + spl_gpio_output(gpio0, GPIO(BANK_A, 2), 1); + + spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_A, 5), + GPIO_PULL_NORMAL); + while (readl(&gpio0->ext_port) & 0x20) + ; + + spl_gpio_output(gpio0, GPIO(BANK_A, 2), 0); + } - /* Turn on red LED, indicating full power mode */ spl_gpio_output(gpio0, GPIO(BANK_B, 5), 1); } diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig index 060b4bfecf..7ca9fd0906 100644 --- a/configs/roc-pc-mezzanine-rk3399_defconfig +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -18,7 +18,8 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc-mezzanine.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x20000 +CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y @@ -33,6 +34,7 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3399-roc-pc-mezzanine" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index 9897a52cd8..440c1ab303 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -18,7 +18,8 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x20000 +CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y @@ -32,6 +33,7 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3399-roc-pc" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y