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[213.198.163.240]) by smtp.gmail.com with ESMTPSA id o4sm8732756wrq.66.2018.12.20.04.54.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 20 Dec 2018 04:54:49 -0800 (PST) From: Jagan Teki To: Yong Deng , Mauro Carvalho Chehab , Maxime Ripard , Rob Herring , Mark Rutland , Chen-Yu Tsai , linux-media@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi , linux-amarula@amarulasolutions.com, Michael Trimarchi Cc: Jagan Teki Subject: [PATCH v5 1/6] dt-bindings: media: sun6i: Add A64 CSI compatible Date: Thu, 20 Dec 2018 18:24:33 +0530 Message-Id: <20181220125438.11700-2-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20181220125438.11700-1-jagan@amarulasolutions.com> References: <20181220125438.11700-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=ijpQewih; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Allwinner A64 CSI is a single channel time-multiplexed BT.656 protocol interface. Add separate compatible string for A64 since it require explicit change in sun6i_csi driver to update default CSI_SCLK rate. Reviewed-by: Rob Herring Signed-off-by: Jagan Teki --- Documentation/devicetree/bindings/media/sun6i-csi.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/media/sun6i-csi.txt b/Documentation/devicetree/bindings/media/sun6i-csi.txt index cc37cf7fd051..0dd540bb03db 100644 --- a/Documentation/devicetree/bindings/media/sun6i-csi.txt +++ b/Documentation/devicetree/bindings/media/sun6i-csi.txt @@ -8,6 +8,7 @@ Required properties: * "allwinner,sun6i-a31-csi" * "allwinner,sun8i-h3-csi" * "allwinner,sun8i-v3s-csi" + * "allwinner,sun50i-a64-csi" - reg: base address and size of the memory-mapped region. - interrupts: interrupt associated to this IP - clocks: phandles to the clocks feeding the CSI From patchwork Thu Dec 20 12:54:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 110 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-wm1-f71.google.com (cartago.priv [10.11.12.1]) by cassiopea (Postfix) with ESMTPS id 91C462E5528 for ; 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[213.198.163.240]) by smtp.gmail.com with ESMTPSA id o4sm8732756wrq.66.2018.12.20.04.54.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 20 Dec 2018 04:54:50 -0800 (PST) From: Jagan Teki To: Yong Deng , Mauro Carvalho Chehab , Maxime Ripard , Rob Herring , Mark Rutland , Chen-Yu Tsai , linux-media@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi , linux-amarula@amarulasolutions.com, Michael Trimarchi Cc: Jagan Teki Subject: [PATCH v5 2/6] media: sun6i: Add mod_rate quirk Date: Thu, 20 Dec 2018 18:24:34 +0530 Message-Id: <20181220125438.11700-3-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20181220125438.11700-1-jagan@amarulasolutions.com> References: <20181220125438.11700-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=FhO6jXCT; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Unfortunately default CSI_SCLK rate cannot work properly to drive the connected sensor interface, particularly on few Allwinner SoC's like A64. So, add mod_rate quirk via driver data so-that the respective SoC's which require to alter the default mod clock rate can assign the operating clock rate. Signed-off-by: Jagan Teki --- .../platform/sunxi/sun6i-csi/sun6i_csi.c | 34 +++++++++++++++---- 1 file changed, 28 insertions(+), 6 deletions(-) diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c index ee882b66a5ea..fe002beae09c 100644 --- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c +++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -28,8 +29,13 @@ #define MODULE_NAME "sun6i-csi" +struct sun6i_csi_variant { + unsigned long mod_rate; +}; + struct sun6i_csi_dev { struct sun6i_csi csi; + const struct sun6i_csi_variant *variant; struct device *dev; struct regmap *regmap; @@ -822,33 +828,43 @@ static int sun6i_csi_resource_request(struct sun6i_csi_dev *sdev, return PTR_ERR(sdev->clk_mod); } + if (sdev->variant->mod_rate) + clk_set_rate_exclusive(sdev->clk_mod, sdev->variant->mod_rate); + sdev->clk_ram = devm_clk_get(&pdev->dev, "ram"); if (IS_ERR(sdev->clk_ram)) { dev_err(&pdev->dev, "Unable to acquire dram-csi clock\n"); - return PTR_ERR(sdev->clk_ram); + ret = PTR_ERR(sdev->clk_ram); + goto err_unprotect_clk; } sdev->rstc_bus = devm_reset_control_get_shared(&pdev->dev, NULL); if (IS_ERR(sdev->rstc_bus)) { dev_err(&pdev->dev, "Cannot get reset controller\n"); return PTR_ERR(sdev->rstc_bus); + goto err_unprotect_clk; } irq = platform_get_irq(pdev, 0); if (irq < 0) { dev_err(&pdev->dev, "No csi IRQ specified\n"); ret = -ENXIO; - return ret; + goto err_unprotect_clk; } ret = devm_request_irq(&pdev->dev, irq, sun6i_csi_isr, 0, MODULE_NAME, sdev); if (ret) { dev_err(&pdev->dev, "Cannot request csi IRQ\n"); - return ret; + goto err_unprotect_clk; } return 0; + +err_unprotect_clk: + if (sdev->variant->mod_rate) + clk_rate_exclusive_put(sdev->clk_mod); + return ret; } /* @@ -871,6 +887,7 @@ static int sun6i_csi_probe(struct platform_device *pdev) sdev->dev = &pdev->dev; /* The DMA bus has the memory mapped at 0 */ sdev->dev->dma_pfn_offset = PHYS_OFFSET >> PAGE_SHIFT; + sdev->variant = of_device_get_match_data(sdev->dev); ret = sun6i_csi_resource_request(sdev, pdev); if (ret) @@ -887,14 +904,19 @@ static int sun6i_csi_remove(struct platform_device *pdev) struct sun6i_csi_dev *sdev = platform_get_drvdata(pdev); sun6i_csi_v4l2_cleanup(&sdev->csi); + if (sdev->variant->mod_rate) + clk_rate_exclusive_put(sdev->clk_mod); return 0; } +static const struct sun6i_csi_variant sun6i_a31_csi = { +}; + static const struct of_device_id sun6i_csi_of_match[] = { - { .compatible = "allwinner,sun6i-a31-csi", }, - { .compatible = "allwinner,sun8i-h3-csi", }, - { .compatible = "allwinner,sun8i-v3s-csi", }, + { .compatible = "allwinner,sun6i-a31-csi", .data = &sun6i_a31_csi, }, + { .compatible = "allwinner,sun8i-h3-csi", .data = &sun6i_a31_csi, }, + { .compatible = "allwinner,sun8i-v3s-csi", .data = &sun6i_a31_csi, }, {}, }; MODULE_DEVICE_TABLE(of, sun6i_csi_of_match); From patchwork Thu Dec 20 12:54:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 111 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-wr1-f70.google.com (cartago.priv [10.11.12.1]) by cassiopea (Postfix) with ESMTPS id 179542E54F7 for ; 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[213.198.163.240]) by smtp.gmail.com with ESMTPSA id o4sm8732756wrq.66.2018.12.20.04.54.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 20 Dec 2018 04:54:52 -0800 (PST) From: Jagan Teki To: Yong Deng , Mauro Carvalho Chehab , Maxime Ripard , Rob Herring , Mark Rutland , Chen-Yu Tsai , linux-media@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi , linux-amarula@amarulasolutions.com, Michael Trimarchi Cc: Jagan Teki Subject: [PATCH v5 3/6] media: sun6i: Add A64 CSI block support Date: Thu, 20 Dec 2018 18:24:35 +0530 Message-Id: <20181220125438.11700-4-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20181220125438.11700-1-jagan@amarulasolutions.com> References: <20181220125438.11700-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=guAKJy0O; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , CSI block in Allwinner A64 has similar features as like in H3, but default mod clock rate in BSP along with latest mainline testing require to operate it at 300MHz. So, add A64 CSI compatibe along with mod_rate quirk. Signed-off-by: Jagan Teki --- drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c index fe002beae09c..48919aabefdb 100644 --- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c +++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c @@ -913,10 +913,15 @@ static int sun6i_csi_remove(struct platform_device *pdev) static const struct sun6i_csi_variant sun6i_a31_csi = { }; +static const struct sun6i_csi_variant sun50i_a64_csi = { + .mod_rate = 300000000, +}; + static const struct of_device_id sun6i_csi_of_match[] = { { .compatible = "allwinner,sun6i-a31-csi", .data = &sun6i_a31_csi, }, { .compatible = "allwinner,sun8i-h3-csi", .data = &sun6i_a31_csi, }, { .compatible = "allwinner,sun8i-v3s-csi", .data = &sun6i_a31_csi, }, + { .compatible = "allwinner,sun50i-a64-csi", .data = &sun50i_a64_csi, }, {}, }; MODULE_DEVICE_TABLE(of, sun6i_csi_of_match); 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[213.198.163.240]) by smtp.gmail.com with ESMTPSA id o4sm8732756wrq.66.2018.12.20.04.54.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 20 Dec 2018 04:54:55 -0800 (PST) From: Jagan Teki To: Yong Deng , Mauro Carvalho Chehab , Maxime Ripard , Rob Herring , Mark Rutland , Chen-Yu Tsai , linux-media@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi , linux-amarula@amarulasolutions.com, Michael Trimarchi Cc: Jagan Teki Subject: [PATCH v5 4/6] arm64: dts: allwinner: a64: Add A64 CSI controller Date: Thu, 20 Dec 2018 18:24:36 +0530 Message-Id: <20181220125438.11700-5-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20181220125438.11700-1-jagan@amarulasolutions.com> References: <20181220125438.11700-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=KuwjOwsz; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add dts node details for Allwinner A64 CSI controller. A64 CSI has similar features as like in H3, but the CSI_SCLK need to update it to 300MHz than default clock rate. Signed-off-by: Jagan Teki --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 384c417cb7a2..89a0deb3fe6a 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -532,6 +532,12 @@ interrupt-controller; #interrupt-cells = <3>; + csi_pins: csi-pins { + pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", + "PE7", "PE8", "PE9", "PE10", "PE11"; + function = "csi0"; + }; + i2c0_pins: i2c0_pins { pins = "PH0", "PH1"; function = "i2c0"; @@ -899,6 +905,20 @@ status = "disabled"; }; + csi: csi@1cb0000 { + compatible = "allwinner,sun50i-a64-csi"; + reg = <0x01cb0000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI_SCLK>, + <&ccu CLK_DRAM_CSI>; + clock-names = "bus", "mod", "ram"; + resets = <&ccu RST_BUS_CSI>; + pinctrl-names = "default"; + pinctrl-0 = <&csi_pins>; + status = "disabled"; + }; + hdmi: hdmi@1ee0000 { compatible = "allwinner,sun50i-a64-dw-hdmi", "allwinner,sun8i-a83t-dw-hdmi"; From patchwork Thu Dec 20 12:54:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 113 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-wm1-f69.google.com (cartago.priv [10.11.12.1]) by cassiopea (Postfix) with ESMTPS id B84DB2E5524 for ; Thu, 20 Dec 2018 13:54:58 +0100 (CET) Received: by mail-wm1-f69.google.com with SMTP id v7sf752677wme.9 for ; Thu, 20 Dec 2018 04:54:58 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1545310498; cv=pass; d=google.com; s=arc-20160816; b=jj23KZ8bkHyEakLSy2MtdtuNcXmPvkVAFD/GRpYkgajSmYApxdvN8yQlLtx9cUW1vw RIxp7y5BotZWp2fZkZ47IWHDoQbgzBZ2HxXoQ+JWPEEC0cPdiC2moKhQWeKTdEa8c/zu 8CUe5pOHQf2XCDTON5wYBcGzdqIxJtJ9g08nIpS9/87vE+ZlZRaOKVR9mnrB6aiMUGks X5vg6QiWiNN7B+eG+5u0OOv6SrW3nsQc0APaStYZ+Kd082noaauGvshoxtcctrNeROH8 uqcbZKQbK2aWw/DhUiDhzMqbuBHQKTxIWdQ26Yr8aA8uE+55elN4VKYLLtulDfCHfgq8 8meQ== ARC-Message-Signature: i=2; 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[213.198.163.240]) by smtp.gmail.com with ESMTPSA id o4sm8732756wrq.66.2018.12.20.04.54.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 20 Dec 2018 04:54:57 -0800 (PST) From: Jagan Teki To: Yong Deng , Mauro Carvalho Chehab , Maxime Ripard , Rob Herring , Mark Rutland , Chen-Yu Tsai , linux-media@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi , linux-amarula@amarulasolutions.com, Michael Trimarchi Cc: Jagan Teki Subject: [PATCH v5 5/6] arm64: dts: allwinner: a64: Add pinmux setting for CSI MCLK on PE1 Date: Thu, 20 Dec 2018 18:24:37 +0530 Message-Id: <20181220125438.11700-6-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20181220125438.11700-1-jagan@amarulasolutions.com> References: <20181220125438.11700-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=BQmZ72bR; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Some camera modules have the SoC feeding a master clock to the sensor instead of having a standalone crystal. This clock signal is generated from the clock control unit and output from the CSI MCLK function of pin PE1. Add a pinmux setting for it for camera sensors to reference. Signed-off-by: Jagan Teki --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 89a0deb3fe6a..dd5740bc3fc9 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -538,6 +538,11 @@ function = "csi0"; }; + csi_mclk_pin: csi-mclk { + pins = "PE1"; + function = "csi0"; + }; + i2c0_pins: i2c0_pins { pins = "PH0", "PH1"; function = "i2c0"; From patchwork Thu Dec 20 12:54:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 114 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-wr1-f69.google.com (cartago.priv [10.11.12.1]) by cassiopea (Postfix) with ESMTPS id 49C0D2E5528 for ; Thu, 20 Dec 2018 13:55:00 +0100 (CET) Received: by mail-wr1-f69.google.com with SMTP id e17sf568351wrw.13 for ; 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[213.198.163.240]) by smtp.gmail.com with ESMTPSA id o4sm8732756wrq.66.2018.12.20.04.54.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 20 Dec 2018 04:54:58 -0800 (PST) From: Jagan Teki To: Yong Deng , Mauro Carvalho Chehab , Maxime Ripard , Rob Herring , Mark Rutland , Chen-Yu Tsai , linux-media@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi , linux-amarula@amarulasolutions.com, Michael Trimarchi Cc: Jagan Teki Subject: [DO NOT MERGE] [PATCH v5 6/6] arm64: dts: allwinner: bananapi-m64: Add HDF5640 camera module Date: Thu, 20 Dec 2018 18:24:38 +0530 Message-Id: <20181220125438.11700-7-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20181220125438.11700-1-jagan@amarulasolutions.com> References: <20181220125438.11700-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=OqNkOUfz; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Bananapi M64 comes with an optional sensor based on the ov5640, add support for it with below pin information. - PE13, PE12 via i2c-gpio bitbanging - CLK_CSI_MCLK as external clock - PE1 as external clock pin muxing - DLDO3 as AVDD supply - ALDO1 as DOVDD supply - ELDO3 as DVDD supply - PE16 gpio for reset pin - PE17 gpio for powerdown pin Signed-off-by: Jagan Teki --- .../dts/allwinner/sun50i-a64-bananapi-m64.dts | 65 +++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts index 83e30e0afe5b..c185ceec8c81 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts @@ -60,6 +60,41 @@ stdout-path = "serial0:115200n8"; }; + i2c-csi { + compatible = "i2c-gpio"; + sda-gpios = <&pio 4 13 GPIO_ACTIVE_HIGH>; /* CSI0-SDA: PE13 */ + scl-gpios = <&pio 4 12 GPIO_ACTIVE_HIGH>; /* CSI0-SCK: PE12 */ + i2c-gpio,delay-us = <5>; + #address-cells = <1>; + #size-cells = <0>; + + ov5640: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&csi_mclk_pin>; + clocks = <&ccu CLK_CSI_MCLK>; + clock-names = "xclk"; + + AVDD-supply = <®_dldo3>; + DOVDD-supply = <®_aldo1>; + DVDD-supply = <®_eldo3>; + reset-gpios = <&pio 4 16 GPIO_ACTIVE_LOW>; /* CSI0-RST: PE16 */ + powerdown-gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* CSI0-PWDN: PE17 */ + + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi_ep>; + bus-width = <8>; + hsync-active = <1>; /* Active high */ + vsync-active = <0>; /* Active low */ + data-active = <1>; /* Active high */ + pclk-sample = <1>; /* Rising */ + }; + }; + }; + }; + hdmi-connector { compatible = "hdmi-connector"; type = "a"; @@ -106,6 +141,24 @@ status = "okay"; }; +&csi { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + csi_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + bus-width = <8>; + hsync-active = <1>; /* Active high */ + vsync-active = <0>; /* Active low */ + data-active = <1>; /* Active high */ + pclk-sample = <1>; /* Rising */ + }; + }; +}; + &dai { status = "okay"; }; @@ -296,6 +349,12 @@ regulator-name = "vcc-wifi"; }; +®_dldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "avdd-csi"; +}; + ®_dldo4 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; @@ -313,6 +372,12 @@ regulator-name = "cpvdd"; }; +®_eldo3 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "dvdd-csi"; +}; + ®_fldo1 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>;