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[209.85.220.65]) by mx.google.com with SMTPS id l17sor24325692plb.27.2020.07.20.23.47.12 for (Google Transport Security); Mon, 20 Jul 2020 23:47:12 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:902:9a4b:: with SMTP id x11mr21179729plv.255.1595314031816; Mon, 20 Jul 2020 23:47:11 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:38b9:d6b4:d935:307b]) by smtp.gmail.com with ESMTPSA id mv6sm1709069pjb.57.2020.07.20.23.47.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jul 2020 23:47:10 -0700 (PDT) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: Suniel Mahesh , U-Boot-Denx , linux-rockchip@lists.infradead.org, linux-amarula , Jagan Teki Subject: [PATCH v3 1/2] rockchip: Add rk3288 SoC detection helper Date: Tue, 21 Jul 2020 12:16:37 +0530 Message-Id: <20200721064638.16236-1-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=go4DHpIP; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Rockchip SoC's has a new revision chip for rk3288 SoCs. RK3288 has a new revision chip called RK3288W which is similar but different hclk_vio clock and fixed OHCI host. Add common Rockchip SoC detection helper to support this rk3288w detection. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- Changes for v3: - add rk3288 cpu spec header .../include/asm/arch-rockchip/cpu_rk3288.h | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/cpu_rk3288.h diff --git a/arch/arm/include/asm/arch-rockchip/cpu_rk3288.h b/arch/arm/include/asm/arch-rockchip/cpu_rk3288.h new file mode 100644 index 0000000000..7445e64b8c --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cpu_rk3288.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Rockchip Electronics Co., Ltd. + */ + +#ifndef __ASM_ARCH_CPU_RK3288_H +#define __ASM_ARCH_CPU_RK3288_H + +#include + +#define ROCKCHIP_CPU_MASK 0xffff0000 +#define ROCKCHIP_CPU_RK3288 0x32880000 + +#define ROCKCHIP_SOC_MASK (ROCKCHIP_CPU_MASK | 0xff) +#define ROCKCHIP_SOC_RK3288 (ROCKCHIP_CPU_RK3288 | 0x00) +#define ROCKCHIP_SOC_RK3288W (ROCKCHIP_CPU_RK3288 | 0x01) + +#define RK3288_HDMI_PHYS 0xff980000 +#define HDMI_CONFIG0_ID 0x4 +#define RK3288W_HDMI_REVID 0x1a + +static inline int rockchip_soc_id(void) +{ + u8 reg; + +#if defined(CONFIG_ROCKCHIP_RK3288) + reg = readb(RK3288_HDMI_PHYS + HDMI_CONFIG0_ID); + if (reg == RK3288W_HDMI_REVID) + return ROCKCHIP_SOC_RK3288W; + else + return ROCKCHIP_SOC_RK3288; +#else + return 0; +#endif +} + +#define ROCKCHIP_SOC(id, ID) \ +static inline bool soc_is_##id(void) \ +{ \ + int soc_id = rockchip_soc_id(); \ + if (soc_id) \ + return ((soc_id & ROCKCHIP_SOC_MASK) == ROCKCHIP_SOC_ ##ID); \ + return false; \ +} + +ROCKCHIP_SOC(rk3288, RK3288) +ROCKCHIP_SOC(rk3288w, RK3288W) + +#endif /* __ASM_ARCH_CPU_RK3288_H */ From patchwork Tue Jul 21 06:46:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1538 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pf1-f200.google.com (mail-pf1-f200.google.com [209.85.210.200]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id BE47E3F1E7 for ; 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[209.85.220.65]) by mx.google.com with SMTPS id y188sor23342822pfg.77.2020.07.20.23.47.15 for (Google Transport Security); Mon, 20 Jul 2020 23:47:15 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:aa7:984d:: with SMTP id n13mr23999459pfq.276.1595314035387; Mon, 20 Jul 2020 23:47:15 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:38b9:d6b4:d935:307b]) by smtp.gmail.com with ESMTPSA id mv6sm1709069pjb.57.2020.07.20.23.47.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jul 2020 23:47:14 -0700 (PDT) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: Suniel Mahesh , U-Boot-Denx , linux-rockchip@lists.infradead.org, linux-amarula , Jagan Teki Subject: [PATCH v3 2/2] rockchip: rk3288: Add OF board setup Date: Tue, 21 Jul 2020 12:16:38 +0530 Message-Id: <20200721064638.16236-2-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200721064638.16236-1-jagan@amarulasolutions.com> References: <20200721064638.16236-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=QPsjBHHM; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The new rk3288 revision rk3288w has some changes with respect to legacy rk3288 like hclk_vio in cru and usb host0 ohci. Linux clock driver already handle this via rockchip,rk3288w-cru compatible. USB ohci host can enable via dts for rk3288w based boards. So, add fdt board setup code to update cru compatible with rk3288w-cru compatible if the SOC revision is RK3288W. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- Changes for v3: - use struct bd_info - drop ifdef OF_BOARD_SETUP since it select by default arch/arm/mach-rockchip/Kconfig | 1 + arch/arm/mach-rockchip/rk3288/rk3288.c | 30 ++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index e2b6326584..fcab1d5cee 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -99,6 +99,7 @@ config ROCKCHIP_RK322X config ROCKCHIP_RK3288 bool "Support Rockchip RK3288" select CPU_V7A + select OF_BOARD_SETUP select SUPPORT_SPL select SPL select SUPPORT_TPL diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c index 804abe8a1b..1a4ecdf625 100644 --- a/arch/arm/mach-rockchip/rk3288/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -115,6 +116,35 @@ int rk_board_late_init(void) return rk3288_board_late_init(); } +static int ft_rk3288w_setup(void *blob) +{ + const char *path; + int offs, ret; + + path = "/clock-controller@ff760000"; + offs = fdt_path_offset(blob, path); + if (offs < 0) { + debug("failed to found fdt path %s\n", path); + return offs; + } + + ret = fdt_setprop_string(blob, offs, "compatible", "rockchip,rk3288w-cru"); + if (ret) { + printf("failed to set rk3288w-cru compatible (ret=%d)\n", ret); + return ret; + } + + return ret; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + if (soc_is_rk3288w()) + return ft_rk3288w_setup(blob); + + return 0; +} + static int do_clock(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) {