From patchwork Wed Nov 3 09:04:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suniel Mahesh X-Patchwork-Id: 1723 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pj1-f72.google.com (mail-pj1-f72.google.com [209.85.216.72]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id B11573F09E for ; Wed, 3 Nov 2021 10:04:44 +0100 (CET) Received: by mail-pj1-f72.google.com with SMTP id y18-20020a17090abd1200b001a4dcd1501csf663932pjr.4 for ; Wed, 03 Nov 2021 02:04:44 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1635930282; cv=pass; d=google.com; s=arc-20160816; b=dOQuyHeHjPhBuGWmjMG/pk6mf6JZzzdWROZ0ovBfMUkekSUXJlUkwhKS/50DKroZcT JrM9/yfojX9oZQsto+v4B9WT5iLBwcJaOdEmoYdKN4ro0Usx1P+1t6IEc7Aof1UbE4KV yxbqogatrVawOk/AeUylSPU4wE22z2qXuJGcATwobNLIsNpLrym4QTOoJmm4L1iuCty9 eJLcCwYafv5YD8c3oCLv+1+sEeAAfVi+B3DZYv1CI8N2u+gqeYvPKBV/4rwMLEPWpUAU YUQhywPfeDuW5B+9QZMI2WgWBvXdSLwJ7117H2C0nUdTrZXtgLWsxtWPFhiQ3NrkwZkK WzJw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:message-id:date:subject:cc:to :from:dkim-signature; bh=HJJnjTjJ2oypM6UBmmyqGInuQN05vueNQHizdPJZ2v8=; b=WO6T4fn4hWmHbuOo65zaUY5LpgD1tGkeeTM8yvRbfXiGDrtUuyN3WD8mL23qDatXBp vgfJde2AtUZUjvnjb+SvNdn75KUUx2c50jnwtSLMlLSW/Z05T97sutxStXaaBaW0pAIm e2SWMv3+yYhWXY3bSfEoyfZvdvJNik8SIA9AMajjVl5y5O8sckvvczVc5O/3H11E8mho KrThgD24ejjE2740Gmj3DtR7hqDeWWo/7RKGWB0zX4NIuFx26e2dukXiMVaBuX8qQMOm unhMVrcOxHRHod5jQSqahFHhYlikx4QXo3G0DURpTchkqM1/FLirgL49DsNmP2XRcfl1 Ox5g== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=Fl3US3I5; spf=pass (google.com: domain of sunil@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=sunil@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=HJJnjTjJ2oypM6UBmmyqGInuQN05vueNQHizdPJZ2v8=; b=e1mzArIrw8KGJDUx7TGUiy2nNC113CX1nvVudlpptcYMfgEHF7DhXGT5+3v59Rlu1C z8E+eaacd+h4pCINfiIw9d9l+MchMnCgTCfl2lbmc5KgvykvZIMY5Tg5BIcFmEubVF+W XwEugW/dTtgzMi8t4iZnZzcnCKP1R5L4/O1ZU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :x-original-sender:x-original-authentication-results:precedence :mailing-list:list-id:x-spam-checked-in-group:list-post:list-help :list-archive:list-unsubscribe; bh=HJJnjTjJ2oypM6UBmmyqGInuQN05vueNQHizdPJZ2v8=; b=2QLvTCN8TJT7gyja7Preeei+1JM+yYlaPpNYPjO7MrALF3uhUSt5eWh2+8BlF6ypE/ DOqgoydGF7RzSVcyp09rChdJVdAE/S4p+48jpktOgIsvoWJifrbxjoEStRQhoblBNL7V +MRnsCY6wlpsLFc5+/tY75gEDL0hTmELXAkWyaoU/1kOCQoJjA9oZlAqSh17cCzdjsVA R/FiQ5uaKDLUGDS/5KkFd/mrpBLKlhVdCle8I/8A6YeqmV9DPJG4JX+r2shBmGv3X31k oTYw//jhkePJN+hvQJhm39J4/nk2txKJkit9t1CGgSsM1vhr/mOfvVPjhm7SvhJnlFlq fGlQ== X-Gm-Message-State: AOAM533fSoXbiD45y4GdEU5O+gLm9TS5wSRp+HT8tFBfJl/ScUxYkoC0 zoPaMO6WO3SoxMRzm6W437JTSdPw X-Google-Smtp-Source: ABdhPJw73c2/5Rc1xfzZH5JbkApwpAJYXBigQqs3LAhNvxBL5r0wF0WB6zpfAWw1yXLLzKenzgK/+g== X-Received: by 2002:a63:b25d:: with SMTP id t29mr16110218pgo.79.1635930282556; Wed, 03 Nov 2021 02:04:42 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:903:1c2:: with SMTP id e2ls925710plh.9.gmail; Wed, 03 Nov 2021 02:04:42 -0700 (PDT) X-Received: by 2002:a17:90b:1b4d:: with SMTP id nv13mr9180310pjb.234.1635930281814; Wed, 03 Nov 2021 02:04:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635930281; cv=none; d=google.com; s=arc-20160816; b=vLkn8U2/dtrBE4rqbpe0mUQZb4os1dZhptw39FQRApJW2Fi1lURyPxzGAVuQ5okmGy k0yDCGwHe53RIDbNEc7BvBe1DUryr9O4emked2CuQa4dlhf3mF3irXiMZ5R5OHXxwJVG I49UhGgMdvC63QrcPRrQbqgiY28QaV3RJ4WSfAuXutDy4nKfFfXFC229pOxE8d95y6wi yy1Z2JHMcCKMs/ao+1hgAYKNhVZDQxoIShRZrW/QVmFsg+AaHr5D/Acy4KAL9tZAhyxW oJ+/eyNZYwTv/KsjfwU7sLPYamK+2EFnTRbAondVGVZUF2tdlbkfdLHSDjo881X6+MFn isNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:dkim-signature; bh=G4NHEQwdCnmyNnScdDNuo2wDBXHXVhr836L6TRXOttg=; b=i5Fk+HkuWVJbaxFYQ65vtY0yGB2DQzdjXOmQnuNzAShm40QaN+YSshdW/lf9H0879P 7Q7MpRxEXRGWgOTOetU2sPXKBRT1BCNsIJD1c5bdv4xVq5xHZvFeINHGRs+0arP6vwHy BeqNIrLsPj5lb+R6OTEnYoQqBjBwmwpqdN2PozaC04LCoFDghpkX+pC8rTtHmugq1KBM 3oiSeMvs3aMV3jcluNGbb+oK4ocwKz6H9w58e3gkl8M3D/S2kBtZjhQ4cp5EP6asvwXf JMHdlgThvMrUDEf/tsKGIn1wbNo2dsLW2HMwQGICMHgBfm9Vd5BxjjtMrf8Jd4x5Dwbx QB9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=Fl3US3I5; spf=pass (google.com: domain of sunil@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=sunil@amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id g3sor733282pgf.47.2021.11.03.02.04.41 for (Google Transport Security); Wed, 03 Nov 2021 02:04:41 -0700 (PDT) Received-SPF: pass (google.com: domain of sunil@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a65:62c1:: with SMTP id m1mr32513624pgv.339.1635930280319; Wed, 03 Nov 2021 02:04:40 -0700 (PDT) Received: from localhost.localdomain ([49.206.57.164]) by smtp.gmail.com with ESMTPSA id s2sm1802292pfg.167.2021.11.03.02.04.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Nov 2021 02:04:39 -0700 (PDT) From: Suniel Mahesh To: linux-amarula@amarulasolutions.com Cc: Jagan Teki Subject: [PATCH 1/5] arm64: dts: rockchip: px30: Sync Linux PX30.Core files Date: Wed, 3 Nov 2021 14:34:24 +0530 Message-Id: <20211103090428.12664-1-sunil@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Original-Sender: sunil@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=Fl3US3I5; spf=pass (google.com: domain of sunil@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=sunil@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Jagan Teki Engicam PX30.Core SoM and it's associated Carrier board device tree files are different than the one it present in U-Boot. Let's Sync the same from Linux-5.14-rc3 with removal of unneeded nodes to satisfy the build. Signed-off-by: Jagan Teki Signed-off-by: Suniel Mahesh --- Changes for v2: - Tested on Engicam EDIMM2.2 with PX30 SOM based carrier board - new patch addition to the series - Rebased on top of v2022.01-rc1 --- arch/arm/dts/Makefile | 4 +- ...dts => px30-engicam-px30-core-ctouch2.dts} | 4 +- ...ts => px30-engicam-px30-core-edimm2.2.dts} | 4 +- arch/arm/dts/px30-engicam-px30-core.dtsi | 241 ++++++++++++++++++ configs/px30-core-ctouch2-px30_defconfig | 4 +- configs/px30-core-edimm2.2-px30_defconfig | 4 +- 6 files changed, 251 insertions(+), 10 deletions(-) rename arch/arm/dts/{px30-px30-core-ctouch2.dts => px30-engicam-px30-core-ctouch2.dts} (80%) rename arch/arm/dts/{px30-px30-core-edimm2.2.dts => px30-engicam-px30-core-edimm2.2.dts} (79%) create mode 100644 arch/arm/dts/px30-engicam-px30-core.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index cc34da7bd8..57a33d0bc4 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -78,8 +78,8 @@ dtb-$(CONFIG_MACH_S700) += \ dtb-$(CONFIG_ROCKCHIP_PX30) += \ px30-evb.dtb \ px30-firefly.dtb \ - px30-px30-core-ctouch2.dtb \ - px30-px30-core-edimm2.2.dtb \ + px30-engicam-px30-core-ctouch2.dtb \ + px30-engicam-px30-core-edimm2.2.dtb \ rk3326-odroid-go2.dtb dtb-$(CONFIG_ROCKCHIP_RK3036) += \ diff --git a/arch/arm/dts/px30-px30-core-ctouch2.dts b/arch/arm/dts/px30-engicam-px30-core-ctouch2.dts similarity index 80% rename from arch/arm/dts/px30-px30-core-ctouch2.dts rename to arch/arm/dts/px30-engicam-px30-core-ctouch2.dts index 2da0128188..5a0ecb8fae 100644 --- a/arch/arm/dts/px30-px30-core-ctouch2.dts +++ b/arch/arm/dts/px30-engicam-px30-core-ctouch2.dts @@ -9,11 +9,11 @@ /dts-v1/; #include "px30.dtsi" #include "px30-engicam-ctouch2.dtsi" -#include "px30-px30-core.dtsi" +#include "px30-engicam-px30-core.dtsi" / { model = "Engicam PX30.Core C.TOUCH 2.0"; - compatible = "engicam,px30-core-ctouch2", "engicam,px30-px30-core", + compatible = "engicam,px30-core-ctouch2", "engicam,px30-core", "rockchip,px30"; chosen { diff --git a/arch/arm/dts/px30-px30-core-edimm2.2.dts b/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts similarity index 79% rename from arch/arm/dts/px30-px30-core-edimm2.2.dts rename to arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts index c36280ce7f..e54d1e480d 100644 --- a/arch/arm/dts/px30-px30-core-edimm2.2.dts +++ b/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts @@ -8,11 +8,11 @@ /dts-v1/; #include "px30.dtsi" #include "px30-engicam-edimm2.2.dtsi" -#include "px30-px30-core.dtsi" +#include "px30-engicam-px30-core.dtsi" / { model = "Engicam PX30.Core EDIMM2.2 Starter Kit"; - compatible = "engicam,px30-core-edimm2.2", "engicam,px30-px30-core", + compatible = "engicam,px30-core-edimm2.2", "engicam,px30-core", "rockchip,px30"; chosen { diff --git a/arch/arm/dts/px30-engicam-px30-core.dtsi b/arch/arm/dts/px30-engicam-px30-core.dtsi new file mode 100644 index 0000000000..7249871530 --- /dev/null +++ b/arch/arm/dts/px30-engicam-px30-core.dtsi @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutons + * Copyright (c) 2020 Amarula Solutons(India) + */ + +#include +#include + +/ { + compatible = "engicam,px30-core", "rockchip,px30"; + + aliases { + mmc0 = &emmc; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + cap-mmc-highspeed; + mmc-hs200-1_8v; + non-removable; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc3v3_sys: DCDC_REG5 { + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v0: LDO_REG1 { + regulator-name = "vcc_1v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_1v8: LDO_REG2 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_1v0: LDO_REG3 { + regulator-name = "vdd_1v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v0_pmu: LDO_REG4 { + regulator-name = "vcc3v0_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc3v3_lcd: SWITCH_REG1 { + regulator-boot-on; + regulator-name = "vcc3v3_lcd"; + }; + + vcc5v0_host: SWITCH_REG2 { + regulator-name = "vcc5v0_host"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&io_domains { + vccio1-supply = <&vcc_3v3>; + vccio2-supply = <&vcc_3v3>; + vccio3-supply = <&vcc_3v3>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + status = "okay"; +}; + +&pinctrl { + pmic { + pmic_int: pmic_int { + rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc_3v3>; + pmuio2-supply = <&vcc_3v3>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig index a5dbbd7453..7d1920458e 100644 --- a/configs/px30-core-ctouch2-px30_defconfig +++ b/configs/px30-core-ctouch2-px30_defconfig @@ -6,7 +6,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_DEFAULT_DEVICE_TREE="px30-px30-core-ctouch2" +CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-ctouch2" CONFIG_SPL_TEXT_BASE=0x00000000 CONFIG_ROCKCHIP_PX30=y CONFIG_TARGET_PX30_CORE=y @@ -23,7 +23,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y -CONFIG_DEFAULT_FDT_FILE="rockchip/px30-px30-core-ctouch2.dtb" +CONFIG_DEFAULT_FDT_FILE="rockchip/px30-engicam-px30-core-ctouch2.dtb" # CONFIG_CONSOLE_MUX is not set # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig index 1e138d63ed..84c57337ce 100644 --- a/configs/px30-core-edimm2.2-px30_defconfig +++ b/configs/px30-core-edimm2.2-px30_defconfig @@ -6,7 +6,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_DEFAULT_DEVICE_TREE="px30-px30-core-edimm2.2" +CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-edimm2.2" CONFIG_SPL_TEXT_BASE=0x00000000 CONFIG_ROCKCHIP_PX30=y CONFIG_TARGET_PX30_CORE=y @@ -23,7 +23,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y -CONFIG_DEFAULT_FDT_FILE="rockchip/px30-px30-core-edimm2.2.dtb" +CONFIG_DEFAULT_FDT_FILE="rockchip/px30-engicam-px30-core-edimm2.2.dtb" # CONFIG_CONSOLE_MUX is not set # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y From patchwork Wed Nov 3 09:04:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suniel Mahesh X-Patchwork-Id: 1724 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pj1-f71.google.com (mail-pj1-f71.google.com [209.85.216.71]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 9B78E3F09E for ; Wed, 3 Nov 2021 10:04:46 +0100 (CET) Received: by mail-pj1-f71.google.com with SMTP id m2-20020a17090a158200b001a18e07bfc0sf431344pja.2 for ; Wed, 03 Nov 2021 02:04:46 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1635930285; cv=pass; d=google.com; s=arc-20160816; b=FyWvhoESFSdyoomvswSpfIGSwbluUVtPkDS93SMGuNZrQoCtzSLw/yMYEp5mUFujpu Ep5rrBz1vx9CSSZPfX+E9WwGGAc9eOaGR6032R3RixuE0Ham/t18QS9tvQncXMpZfhA+ 9iPol9CM178rQfU7lHdju9NComzWqHaDLM+LSJkRg2FS6jBl0qGrusGJWAVHJYhzChqb SOf8VRaSi264kmlmhlg+gu8mImYiu8LbfCETsShuipEnJKtPRukStI4V4JzpPaWjDXCh mxgLVql3sgZBk0bX2+nJlTFEACyxXZ2YyQ12YWfa2kvXqccC+4QjzzUvxlhJYuHR2SOm WcaA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=IHh08se8q3b/+N4hSP91yEp06r4b5jspjgIOVL0nM6M=; b=aBxcaKChAAH2jHGvU+kK9E5EXJ8pWBsuPUijVIczo0NzgQScaAPkEK2301Eonx+IX2 uiwppZb4Pkq1OdFyAVpCNBfX2x67XaFFoF0+0/zm/x7Ka906sQJTFvDLY1vXMasFQkNP W9Xvk2Uh4ZNZQ5mR0LuHQ8FxZiUh79BCdpW9TKKwqJNSRP6WZAaWkOYbsaOe8uaVdbir d5Hyg3CcH/iHP465bDZadIE5gFhCgRd3iGVmXNjuOm14PZHiS1rUcncHKQ9KO7CoPWVH bEIlZExifCkGyaSNgZsgggI28zo+AZYvqWipW4B6kTTkO9QA5YRSBeI0lnrJ68gD8TfK bjmw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=RAe2ziPP; spf=pass (google.com: domain of sunil@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=sunil@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=IHh08se8q3b/+N4hSP91yEp06r4b5jspjgIOVL0nM6M=; b=p0B+flBuazEk3orK9Li2Vnt3w7ZpJMjD07o8aP6NUHTTpx8VAY4JeksoxZ1455CN3f 4qq7XiyzcLYUvM4PGHI12UwXCUQFt448bSbTLcBvbgrluSmni8tfJtN5m/b+0sLcy+CJ 4vfQ12vp76xCsGT+TXbUU0EyIS4Sxq9GIc7yA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=IHh08se8q3b/+N4hSP91yEp06r4b5jspjgIOVL0nM6M=; b=6SGVa/TmkWL3DqhMc/hQdHiCmLNylKm0gfhT+OndehjxP0cC7TBAj6OcVNfeuM7XSd ZPawZr/m/skt0cHNk0cEvKtf/iJA6hciKNG2Xy8pjtqpxH01dkTDbq4UEMj2l+XxZ8of Fv+/M2UV3yEW/qYYrxjIrAu4oTcNrk+pCdmdf80zGOUByJTPu0hyzACMeJkWHGazIBAJ vhAz4iu3YjWf70fFzCBchdghFzu31lpRTJ189p5YJz35d+ZH+568AvyRUqb3tLl1Ecb1 xzQOnNNBNCRlHZ8Cr6QHZugaudWlGpSYUxeKuG8L/nlGxrOZgL+zIaFKpBkk9sYr9SYM bmzw== X-Gm-Message-State: AOAM5314yu8eSnGbAJUiwdmWm43o7ByW+vBud8E4/WGAOZwJzTTDd2aU dX3k08Ql9Lgf9btVmepCaek9Yoko X-Google-Smtp-Source: ABdhPJxpArOizlc+Fy9Ku3Re6SamWhK6NLJ/s9H9ecwdOWZzVxFwR7TE8eL0RfyKav3Hcv1yLh+gYQ== X-Received: by 2002:a17:90b:124d:: with SMTP id gx13mr13156054pjb.106.1635930285439; Wed, 03 Nov 2021 02:04:45 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a05:6a00:1684:: with SMTP id k4ls706933pfc.11.gmail; Wed, 03 Nov 2021 02:04:45 -0700 (PDT) X-Received: by 2002:a05:6a00:1484:b0:48c:2e58:8d39 with SMTP id v4-20020a056a00148400b0048c2e588d39mr5614723pfu.13.1635930284746; Wed, 03 Nov 2021 02:04:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635930284; cv=none; d=google.com; s=arc-20160816; b=uOJPV9SGj7SpLt7CVK9IXEH/qvFtfHMXhBTllgK3Oqw1JpNQGficEXiglNfrRDoHlt J7Rypko0v0Wv3ku69QkpeW5hzgh/H9sdbsDZlDph40ZVqgOop0FA1yvAS5FMYlSE80yd i9mvcv3BFvc7YA/0A/UQu+w+jr8yqJDUuCSzW2v2mzLVH7u2hukmriOczZeeis+RI9Ud 8nTZiC8l5ikq7+3PmGdjhEuFxxuFlDPGKHAXk1tYQcZZgzzu0vYnR71v7OxleXq7cTuS Mh03d6vKOf5mjZFTx8iMSp2/zEcrh3DKbib7IABSdh6VYPxDGy7UspJcT6uH8fxPJPPJ xROA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=ylVRc0qjymf38VwqsDiiidAfoucxXBtV0egqr6qU9Rg=; b=FLcRjm/oB1+uGKGeGx80CtkecwN/AtrTy5SOtEZekyPxHtwDUNlEVbjzCYrZ9Yre2z jRUNXN3HpQJEf0USTW1+W/9p73GP3fG2YyBmuakqGrWtaO/MGsHIssNhNpeSub9OCyvD aEMZXqQ0HAu2cXPgcyTjLfrDVp/vzP9tm8sDd/G2qeJIfv9GGuzpdGfs1J8q6MAw+xkq k7OYjAVDCKmt07w171DRBTcWNSh6ogMCX8jJaFPOC47zkQlJjFQPZV4o7rwNZoFgoIcc jIuUKUXVYvq0xvy43/xisl35dnjRurxnpqfraAM4+RZqbru8fRW1EhZfkm2rYMpyi2d4 Ylng== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=RAe2ziPP; spf=pass (google.com: domain of sunil@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=sunil@amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id c17sor3338964pjs.34.2021.11.03.02.04.44 for (Google Transport Security); Wed, 03 Nov 2021 02:04:44 -0700 (PDT) Received-SPF: pass (google.com: domain of sunil@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:90a:fe14:: with SMTP id ck20mr13103412pjb.72.1635930284426; Wed, 03 Nov 2021 02:04:44 -0700 (PDT) Received: from localhost.localdomain ([49.206.57.164]) by smtp.gmail.com with ESMTPSA id s2sm1802292pfg.167.2021.11.03.02.04.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Nov 2021 02:04:44 -0700 (PDT) From: Suniel Mahesh To: linux-amarula@amarulasolutions.com Cc: Jagan Teki Subject: [PATCH 2/5] arm64: dts: rockchip: px30: Move dmc into -u-boot.dtsi Date: Wed, 3 Nov 2021 14:34:25 +0530 Message-Id: <20211103090428.12664-2-sunil@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211103090428.12664-1-sunil@amarulasolutions.com> References: <20211103090428.12664-1-sunil@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: sunil@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=RAe2ziPP; spf=pass (google.com: domain of sunil@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=sunil@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Jagan Teki dmc node is specific to U-Boot, it is always better practice to maintain U-Boot specific nodes into -u-boot.dtsi files in order to maintain Linux dts file sync compatibility. Move the dmc into px30-u-boot.dtsi, also add dmc node explicitly in rk3326-odroid-go2-u-boot.dtsi since it is using px30.dts. Signed-off-by: Jagan Teki Signed-off-by: Suniel Mahesh --- Changes for v2: - Tested on Engicam EDIMM2.2 with PX30 SOM based carrier board - new patch addition to the series - Rebased on top of v2022.01-rc1 --- arch/arm/dts/px30-u-boot.dtsi | 10 ++++++---- arch/arm/dts/px30.dtsi | 5 ----- arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 10 ++++++---- 3 files changed, 12 insertions(+), 13 deletions(-) diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi index 029c8fbd8d..bbed7dcde5 100644 --- a/arch/arm/dts/px30-u-boot.dtsi +++ b/arch/arm/dts/px30-u-boot.dtsi @@ -13,6 +13,12 @@ u-boot,spl-boot-order = &emmc, &sdmmc; }; + dmc { + u-boot,dm-pre-reloc; + compatible = "rockchip,px30-dmc", "syscon"; + reg = <0x0 0xff2a0000 0x0 0x1000>; + }; + rng: rng@ff0b0000 { compatible = "rockchip,cryptov2-rng"; reg = <0x0 0xff0b0000 0x0 0x4000>; @@ -20,10 +26,6 @@ }; }; -&dmc { - u-boot,dm-pre-reloc; -}; - &uart2 { clock-frequency = <24000000>; u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/px30.dtsi b/arch/arm/dts/px30.dtsi index ef706486dc..ef77b7b997 100644 --- a/arch/arm/dts/px30.dtsi +++ b/arch/arm/dts/px30.dtsi @@ -151,11 +151,6 @@ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; - dmc: dmc { - compatible = "rockchip,px30-dmc", "syscon"; - reg = <0x0 0xff2a0000 0x0 0x1000>; - }; - display_subsystem: display-subsystem { compatible = "rockchip,display-subsystem"; ports = <&vopb_out>, <&vopl_out>; diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi index bffaa3edf3..63d87e16e1 100644 --- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi +++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi @@ -16,6 +16,12 @@ serial2 = &uart2; spi0 = &sfc; }; + + dmc { + u-boot,dm-pre-reloc; + compatible = "rockchip,px30-dmc", "syscon"; + reg = <0x0 0xff2a0000 0x0 0x1000>; + }; }; /* U-Boot clk driver for px30 cannot set GPU_CLK */ @@ -32,10 +38,6 @@ <100000000>, <17000000>; }; -&dmc { - u-boot,dm-pre-reloc; -}; - &gpio0 { u-boot,dm-pre-reloc; }; From patchwork Wed Nov 3 09:04:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suniel Mahesh X-Patchwork-Id: 1725 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pf1-f199.google.com (mail-pf1-f199.google.com [209.85.210.199]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id B23A33F09E for ; Wed, 3 Nov 2021 10:04:52 +0100 (CET) Received: by mail-pf1-f199.google.com with SMTP id r2-20020a627602000000b00480f8ce37absf996976pfc.8 for ; Wed, 03 Nov 2021 02:04:52 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1635930291; cv=pass; d=google.com; s=arc-20160816; b=ATu6uVyTW+wxGfU/nqX5GnFdCQiVPppcY0tSy5ceDHzrRNaOr7S7sp3F0N3nD3HkTf CsXAyoqIk6W6llvArH3ax5M3RLurb3h5D+lvaZ7pt5DTKGDgt7IpqQcrbguwpMQtlKAX XcWslt3Xvrb7eYttr+YTB3uyIb4ZwuImZtzQwfWTVn1nx5wK9UP7uZBOCUbWkxXI8WLI c1eFeMjrOyARvdei9BrrPVpTDVxH5vbTZTi0AAnZbu9gL8EAo0QrKZUJuclnydAvcC/U dIg7+Bvz0ZR+anqL5j7I8jVt/1Y63FOl5EQ8CCdz5+/9icKHNBSs8yC1jy0nBJ9dSXdF 00ww== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Ml3OcLY76A84HZjqH+WdmrM6J4uSpDnXw7e+DdrE0y4=; b=SRjPdUTAojdPQU9MsQNg1eKFVK9zXfL8tJSW6GOl0YbvCsACY6dGWUsjrxiWgcRfoW QMMp4XSvdeYX9JiVvLqnGaf/1G2jXtKBkNgyBvbVNmqdo9YOFHRYcseNjqA1PEP9oN66 VEXzfGzxUCTssu6qiBOhpRwllfQ8Za3Skikjkl+gClvmFuswFfoEln4EkoRePu6jQrE4 I+zypfHmAOEKG+boJHogshOB0tl0/5neWei9mvcvxKDqn9N6Eh85vobBJwXj7+Dkz/cA 2ifFc4bmTdYmcjxTtJXWtWZlAVNE3cOVXH7kBUZveOv3i4O7eoqyh8b3lzw8ri4E13BE PZ+A== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=SfWc5Cg1; spf=pass (google.com: domain of sunil@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=sunil@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=Ml3OcLY76A84HZjqH+WdmrM6J4uSpDnXw7e+DdrE0y4=; b=QnUn8DlP4SBZRwWW3sMY27l44VbQ7ubxUuhklGu3jGA2YFWcjOAC6JzGlnqaC0wB6R mTxROhURx9/BlTmMst8rL+izKedJDkGQvYtyqs6ZabVyZOOrlMazmuOOvVK6qkct8ac1 9z0ZuViFAshF49gNm9kfgN0M7Anln1EnrKM3k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=Ml3OcLY76A84HZjqH+WdmrM6J4uSpDnXw7e+DdrE0y4=; b=RyTKCG0E91+P3l0W00M7KNudzi/pvaiOPJeofn2mDRPxrFT1lil0yZwGVsVOY+UlNd rJxft9H7QzY+7PDzkeNllae5xyjkwHwhATxGe+TvBe7Lpfw1HBirAtbAPZdBY9GB4V7T jjNAd+iCSW7cHIGxS2CD9cNGvABn4q+EOT7J4vjb+QZOc9GmIlI/J2XdIDhMLy9Qyzna l9pSTiZDWvcTklDkQ9d9V5I/V/+jkQIoKG472bEPHeUR45TNuCs8pHZmOkeLrfe85pl0 jV6FS/xjaQGJ+eNfoS2FGVcS4d9bm6LbnYYLVxNLxRf/p1quHpvwTzXBWjIuCSIlSHJw bzsg== X-Gm-Message-State: AOAM531rzPw//NTmAx3JzQq4jz1TTLycf2gqnYaW7BU0115Fop5eufzJ 7dz99P7fY6hyazT/bokKCqa8VamO X-Google-Smtp-Source: ABdhPJxuloJGhoB2oafsMUKWSBLyyeBbZtV+FpzIQFaLrTdxvSlMGZUvgYKQ9pjNa/BohSj6YVG8gA== X-Received: by 2002:a63:6b42:: with SMTP id g63mr32505039pgc.461.1635930291039; Wed, 03 Nov 2021 02:04:51 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:902:f687:: with SMTP id l7ls925072plg.10.gmail; Wed, 03 Nov 2021 02:04:50 -0700 (PDT) X-Received: by 2002:a17:90a:9906:: with SMTP id b6mr13028603pjp.180.1635930290286; Wed, 03 Nov 2021 02:04:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635930290; cv=none; d=google.com; s=arc-20160816; b=aQos9eZ1le/Da5txrZeFElBmSYObKhxMNECoOMLIYNrLEi0CZnprm4+6sSurDVKopY Ys+cTJ/5TEA9tcp3OOIoenfFyrHDMGtaXgnblVj2DiXKYRJx+EbRmDNK80AjSk4Qp8eV 5kDWWQxNEATT5w3vsNPoRduU4qd0uF6dXOaYw6ZZ48pUj5drNh6CtNDrKTPAx2eIPFak cD8/iLQ/ZSzbutraeqfDUCKpeyAqPasx9kuWCuJsMCx1XlI60DfU1vdsV4aRgjjIsS2P jknFiVjShIRcpP8IB33CbHK3+tRmkspmt0LPhYO9rwO2XtXeGDbjKl19PPR91c+IFNDi Lu5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=s5GwcszlqkCtsP5sFAwby9unmiQBPP6qvP8z7Tc9jKs=; b=RWeWuG79Bt4g8dManXtWf9hOs114PHym8OgDfwUMC4IT/njq4N4mirIpbICOm9KKjA x/qhw7egQAAM81QkRnC6X/pvdpqlr4UQvo4cGYleLATgaj06WrINWfQhvgEvRBCpfO0Z R9UmQEoc7+FkuvnMTcO6+HaU9OGJ7XSyESq3KczMBWMmDH0nEIGIBxcPZuCC+HEcI3YG Inl3Kqzx2nFvrae+WBx/84UTjaCFakg+EQJxS6EQiBa77sN/QY135hZg6e32owQ8sRMn 5fBcvYQZIDZtyWxRj3vH2fkmvNiMxXwqEE4PVyiXe7Uu3iPkIgd4komVrH+0acmifpMg KZ0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=SfWc5Cg1; spf=pass (google.com: domain of sunil@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=sunil@amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id a15sor925187plm.66.2021.11.03.02.04.50 for (Google Transport Security); Wed, 03 Nov 2021 02:04:50 -0700 (PDT) Received-SPF: pass (google.com: domain of sunil@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:903:1c7:b0:141:e630:130c with SMTP id e7-20020a17090301c700b00141e630130cmr18324782plh.80.1635930289806; Wed, 03 Nov 2021 02:04:49 -0700 (PDT) Received: from localhost.localdomain ([49.206.57.164]) by smtp.gmail.com with ESMTPSA id s2sm1802292pfg.167.2021.11.03.02.04.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Nov 2021 02:04:49 -0700 (PDT) From: Suniel Mahesh To: linux-amarula@amarulasolutions.com Cc: Jagan Teki Subject: [PATCH 3/5] arm64: dts: rockchip: px30: Sync Linux-5.14-rc3 dts(i) Date: Wed, 3 Nov 2021 14:34:26 +0530 Message-Id: <20211103090428.12664-3-sunil@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211103090428.12664-1-sunil@amarulasolutions.com> References: <20211103090428.12664-1-sunil@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: sunil@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=SfWc5Cg1; spf=pass (google.com: domain of sunil@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=sunil@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Jagan Teki Sync the px30 devicetree files from Linux-5.14-rc3. Signed-off-by: Jagan Teki Signed-off-by: Suniel Mahesh --- Changes for v2: - Tested on Engicam EDIMM2.2 with PX30 SOM based carrier board - new patch addition to the series - Rebased on top of v2022.01-rc1 --- arch/arm/dts/px30-engicam-common.dtsi | 90 +++++++++ arch/arm/dts/px30-engicam-ctouch2.dtsi | 22 +++ arch/arm/dts/px30-engicam-edimm2.2.dtsi | 59 ++++++ .../px30-engicam-px30-core-ctouch2-of10.dts | 77 ++++++++ .../dts/px30-engicam-px30-core-edimm2.2.dts | 22 +++ arch/arm/dts/px30-evb.dts | 91 +++++++-- arch/arm/dts/px30.dtsi | 178 +++++++++++------- 7 files changed, 457 insertions(+), 82 deletions(-) create mode 100644 arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts diff --git a/arch/arm/dts/px30-engicam-common.dtsi b/arch/arm/dts/px30-engicam-common.dtsi index bd5bde989e..3429e124d9 100644 --- a/arch/arm/dts/px30-engicam-common.dtsi +++ b/arch/arm/dts/px30-engicam-common.dtsi @@ -6,6 +6,11 @@ */ / { + aliases { + mmc1 = &sdmmc; + mmc2 = &sdio; + }; + vcc5v0_sys: vcc5v0-sys { compatible = "regulator-fixed"; regulator-name = "vcc5v0_sys"; /* +5V */ @@ -14,6 +19,63 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&xin32k>; + clock-names = "ext_clock"; + post-power-on-delay-ms = <80>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + }; + + vcc3v3_btreg: vcc3v3-btreg { + compatible = "regulator-gpio"; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&bt_enable_h>; + regulator-name = "btreg-gpio-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + states = <3300000 0x0>; + }; + + vcc3v3_rf_aux_mod: vcc3v3-rf-aux-mod { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_rf_aux_mod"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + }; +}; + +&sdio { + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + clock-frequency = <50000000>; + cap-sdio-irq; + cap-sd-highspeed; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + sd-uhs-sdr104; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + }; }; &gmac { @@ -25,6 +87,10 @@ status = "okay"; }; +&pwm0 { + status = "okay"; +}; + &sdmmc { cap-sd-highspeed; card-detect-delay = <800>; @@ -33,7 +99,31 @@ status = "okay"; }; +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "okay"; + }; + + u2phy_otg: otg-port { + status = "okay"; + }; +}; + &uart2 { pinctrl-0 = <&uart2m1_xfer>; status = "okay"; }; + +&usb20_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; diff --git a/arch/arm/dts/px30-engicam-ctouch2.dtsi b/arch/arm/dts/px30-engicam-ctouch2.dtsi index 58425b1e55..bf10a3d29f 100644 --- a/arch/arm/dts/px30-engicam-ctouch2.dtsi +++ b/arch/arm/dts/px30-engicam-ctouch2.dtsi @@ -6,3 +6,25 @@ */ #include "px30-engicam-common.dtsi" + +&pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdio_pwrseq { + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; +}; + +&vcc3v3_btreg { + enable-gpio = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm/dts/px30-engicam-edimm2.2.dtsi b/arch/arm/dts/px30-engicam-edimm2.2.dtsi index cb00988953..449b8eb645 100644 --- a/arch/arm/dts/px30-engicam-edimm2.2.dtsi +++ b/arch/arm/dts/px30-engicam-edimm2.2.dtsi @@ -5,3 +5,62 @@ */ #include "px30-engicam-common.dtsi" + +/ { + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + }; + + panel { + compatible = "yes-optoelectronics,ytc700tlag-05-201c"; + backlight = <&backlight>; + data-mapping = "vesa-24"; + power-supply = <&vcc3v3_lcd>; + + port { + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi_dphy { + status = "okay"; +}; + +/* LVDS_B(secondary) */ +&lvds { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts b/arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts new file mode 100644 index 0000000000..47aa30505a --- /dev/null +++ b/arch/arm/dts/px30-engicam-px30-core-ctouch2-of10.dts @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions(India) + */ + +/dts-v1/; +#include "px30.dtsi" +#include "px30-engicam-ctouch2.dtsi" +#include "px30-engicam-px30-core.dtsi" + +/ { + model = "Engicam PX30.Core C.TOUCH 2.0 10.1\" Open Frame"; + compatible = "engicam,px30-core-ctouch2-of10", "engicam,px30-core", + "rockchip,px30"; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + panel { + compatible = "ampire,am-1280800n3tzqw-t00h"; + backlight = <&backlight>; + power-supply = <&vcc3v3_lcd>; + data-mapping = "vesa-24"; + + port { + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi_dphy { + status = "okay"; +}; + +&lvds { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts b/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts index e54d1e480d..d759478e1c 100644 --- a/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts +++ b/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts @@ -19,3 +19,25 @@ stdout-path = "serial2:115200n8"; }; }; + +&pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdio_pwrseq { + reset-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>; +}; + +&vcc3v3_btreg { + enable-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm/dts/px30-evb.dts b/arch/arm/dts/px30-evb.dts index 4134e2ee13..c1ce9c295e 100644 --- a/arch/arm/dts/px30-evb.dts +++ b/arch/arm/dts/px30-evb.dts @@ -13,8 +13,14 @@ model = "Rockchip PX30 EVB"; compatible = "rockchip,px30-evb", "rockchip,px30"; + aliases { + mmc0 = &sdmmc; + mmc1 = &sdio; + mmc2 = &emmc; + }; + chosen { - stdout-path = "serial2:115200n8"; + stdout-path = "serial5:115200n8"; }; adc-keys { @@ -126,22 +132,15 @@ }; panel@0 { - compatible = "sitronix,st7703"; + compatible = "xinpeng,xpp055c272"; reg = <0>; backlight = <&backlight>; iovcc-supply = <&vcc_1v8>; vci-supply = <&vcc3v3_lcd>; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mipi_in_panel: endpoint { - remote-endpoint = <&mipi_out_panel>; - }; + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; }; }; }; @@ -152,7 +151,6 @@ }; &emmc { - bus-width = <8>; cap-mmc-highspeed; mmc-hs200-1_8v; non-removable; @@ -171,6 +169,11 @@ status = "okay"; }; +&gpu { + mali-supply = <&vdd_log>; + status = "okay"; +}; + &i2c0 { status = "okay"; @@ -388,6 +391,43 @@ }; }; +&i2c1 { + status = "okay"; + + sensor@d { + compatible = "asahi-kasei,ak8963"; + reg = <0x0d>; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + vdd-supply = <&vcc3v0_pmu>; + mount-matrix = "1", /* x0 */ + "0", /* y0 */ + "0", /* z0 */ + "0", /* x1 */ + "1", /* y1 */ + "0", /* z1 */ + "0", /* x2 */ + "0", /* y2 */ + "1"; /* z2 */ + }; + + touchscreen@14 { + compatible = "goodix,gt1151"; + reg = <0x14>; + interrupt-parent = <&gpio0>; + interrupts = ; + irq-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + VDDIO-supply = <&vcc3v3_lcd>; + }; + + sensor@4c { + compatible = "fsl,mma7660"; + reg = <0x4c>; + interrupt-parent = <&gpio0>; + interrupts = ; + }; +}; + &i2s1_2ch { status = "okay"; }; @@ -464,7 +504,6 @@ }; &sdmmc { - bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; card-detect-delay = <800>; @@ -474,10 +513,10 @@ sd-uhs-sdr104; vmmc-supply = <&vcc_sd>; vqmmc-supply = <&vccio_sd>; + status = "okay"; }; &sdio { - bus-width = <4>; cap-sd-highspeed; keep-power-in-suspend; non-removable; @@ -486,13 +525,27 @@ status = "okay"; }; -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer &uart1_cts>; +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy { status = "okay"; + + u2phy_host: host-port { + status = "okay"; + }; + + u2phy_otg: otg-port { + status = "okay"; + }; }; -&uart2 { +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer &uart1_cts>; status = "okay"; }; diff --git a/arch/arm/dts/px30.dtsi b/arch/arm/dts/px30.dtsi index ef77b7b997..10bfe84554 100644 --- a/arch/arm/dts/px30.dtsi +++ b/arch/arm/dts/px30.dtsi @@ -143,7 +143,7 @@ }; arm-pmu { - compatible = "arm,cortex-a53-pmu"; + compatible = "arm,cortex-a35-pmu"; interrupts = , , , @@ -244,28 +244,31 @@ #size-cells = <0>; /* These power domains are grouped by VD_LOGIC */ - pd_usb@PX30_PD_USB { + power-domain@PX30_PD_USB { reg = ; clocks = <&cru HCLK_HOST>, <&cru HCLK_OTG>, <&cru SCLK_OTG_ADP>; pm_qos = <&qos_usb_host>, <&qos_usb_otg>; + #power-domain-cells = <0>; }; - pd_sdcard@PX30_PD_SDCARD { + power-domain@PX30_PD_SDCARD { reg = ; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; pm_qos = <&qos_sdmmc>; + #power-domain-cells = <0>; }; - pd_gmac@PX30_PD_GMAC { + power-domain@PX30_PD_GMAC { reg = ; clocks = <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, <&cru SCLK_MAC_REF>, <&cru SCLK_GMAC_RX_TX>; pm_qos = <&qos_gmac>; + #power-domain-cells = <0>; }; - pd_mmc_nand@PX30_PD_MMC_NAND { + power-domain@PX30_PD_MMC_NAND { reg = ; clocks = <&cru HCLK_NANDC>, <&cru HCLK_EMMC>, @@ -277,15 +280,17 @@ <&cru SCLK_SFC>; pm_qos = <&qos_emmc>, <&qos_nand>, <&qos_sdio>, <&qos_sfc>; + #power-domain-cells = <0>; }; - pd_vpu@PX30_PD_VPU { + power-domain@PX30_PD_VPU { reg = ; clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>, <&cru SCLK_CORE_VPU>; pm_qos = <&qos_vpu>, <&qos_vpu_r128>; + #power-domain-cells = <0>; }; - pd_vo@PX30_PD_VO { + power-domain@PX30_PD_VO { reg = ; clocks = <&cru ACLK_RGA>, <&cru ACLK_VOPB>, @@ -300,8 +305,9 @@ <&cru SCLK_VOPB_PWM>; pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, <&qos_vop_m0>, <&qos_vop_m1>; + #power-domain-cells = <0>; }; - pd_vi@PX30_PD_VI { + power-domain@PX30_PD_VI { reg = ; clocks = <&cru ACLK_CIF>, <&cru ACLK_ISP>, @@ -311,11 +317,13 @@ pm_qos = <&qos_isp_128>, <&qos_isp_rd>, <&qos_isp_wr>, <&qos_isp_m1>, <&qos_vip>; + #power-domain-cells = <0>; }; - pd_gpu@PX30_PD_GPU { + power-domain@PX30_PD_GPU { reg = ; clocks = <&cru SCLK_GPU>; pm_qos = <&qos_gpu>; + #power-domain-cells = <0>; }; }; }; @@ -600,7 +608,7 @@ }; wdt: watchdog@ff1e0000 { - compatible = "snps,dw-wdt"; + compatible = "rockchip,px30-wdt", "snps,dw-wdt"; reg = <0x0 0xff1e0000 0x0 0x100>; clocks = <&cru PCLK_WDT_NS>; interrupts = ; @@ -703,21 +711,15 @@ clock-names = "pclk", "timer"; }; - amba { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - dmac: dmac@ff240000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff240000 0x0 0x4000>; - interrupts = , - ; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; + dmac: dmac@ff240000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff240000 0x0 0x4000>; + interrupts = , + ; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + #dma-cells = <1>; }; tsadc: tsadc@ff280000 { @@ -733,9 +735,9 @@ rockchip,grf = <&grf>; rockchip,hw-tshut-temp = <120000>; pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&tsadc_otp_gpio>; + pinctrl-0 = <&tsadc_otp_pin>; pinctrl-1 = <&tsadc_otp_out>; - pinctrl-2 = <&tsadc_otp_gpio>; + pinctrl-2 = <&tsadc_otp_pin>; #thermal-sensor-cells = <1>; status = "disabled"; }; @@ -784,6 +786,16 @@ rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; + + assigned-clocks = <&cru PLL_NPLL>, + <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, + <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, + <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>; + + assigned-clock-rates = <1188000000>, + <200000000>, <200000000>, + <150000000>, <150000000>, + <100000000>, <200000000>; }; pmucru: clock-controller@ff2bc000 { @@ -794,6 +806,13 @@ rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; + + assigned-clocks = + <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, + <&pmucru SCLK_WIFI_PMU>; + assigned-clock-rates = + <1200000000>, <100000000>, + <26000000>; }; usb2phy_grf: syscon@ff2c0000 { @@ -803,7 +822,7 @@ #address-cells = <1>; #size-cells = <1>; - u2phy: usb2-phy@100 { + u2phy: usb2phy@100 { compatible = "rockchip,px30-usb2phy"; reg = <0x100 0x20>; clocks = <&pmucru SCLK_USBPHY_REF>; @@ -856,7 +875,6 @@ g-np-tx-fifo-size = <16>; g-rx-fifo-size = <280>; g-tx-fifo-size = <256 128 128 64 32 16>; - g-use-dma; phys = <&u2phy_otg>; phy-names = "usb2-phy"; power-domains = <&power PX30_PD_USB>; @@ -868,7 +886,6 @@ reg = <0x0 0xff340000 0x0 0x10000>; interrupts = ; clocks = <&cru HCLK_HOST>; - clock-names = "usbhost"; phys = <&u2phy_host>; phy-names = "usb"; power-domains = <&power PX30_PD_USB>; @@ -880,7 +897,6 @@ reg = <0x0 0xff350000 0x0 0x10000>; interrupts = ; clocks = <&cru HCLK_HOST>; - clock-names = "usbhost"; phys = <&u2phy_host>; phy-names = "usb"; power-domains = <&power PX30_PD_USB>; @@ -910,13 +926,14 @@ status = "disabled"; }; - sdmmc: dwmmc@ff370000 { + sdmmc: mmc@ff370000 { compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff370000 0x0 0x4000>; interrupts = ; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + bus-width = <4>; fifo-depth = <0x100>; max-frequency = <150000000>; pinctrl-names = "default"; @@ -925,13 +942,14 @@ status = "disabled"; }; - sdio: dwmmc@ff380000 { + sdio: mmc@ff380000 { compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff380000 0x0 0x4000>; interrupts = ; clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + bus-width = <4>; fifo-depth = <0x100>; max-frequency = <150000000>; pinctrl-names = "default"; @@ -940,13 +958,14 @@ status = "disabled"; }; - emmc: dwmmc@ff390000 { + emmc: mmc@ff390000 { compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff390000 0x0 0x4000>; interrupts = ; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + bus-width = <8>; fifo-depth = <0x100>; max-frequency = <150000000>; pinctrl-names = "default"; @@ -967,6 +986,42 @@ status = "disabled"; }; + nfc: nand-controller@ff3b0000 { + compatible = "rockchip,px30-nfc"; + reg = <0x0 0xff3b0000 0x0 0x4000>; + interrupts = ; + clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; + clock-names = "ahb", "nfc"; + assigned-clocks = <&cru SCLK_NANDC>; + assigned-clock-rates = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0 + &flash_rdn &flash_rdy &flash_wrn &flash_dqs>; + power-domains = <&power PX30_PD_MMC_NAND>; + status = "disabled"; + }; + + gpu_opp_table: opp-table2 { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <950000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <975000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1050000>; + }; + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-microvolt = <1125000>; + }; + }; + gpu: gpu@ff400000 { compatible = "rockchip,px30-mali", "arm,mali-bifrost"; reg = <0x0 0xff400000 0x0 0x4000>; @@ -977,6 +1032,7 @@ clocks = <&cru SCLK_GPU>; #cooling-cells = <2>; power-domains = <&power PX30_PD_GPU>; + operating-points-v2 = <&gpu_opp_table>; status = "disabled"; }; @@ -1029,7 +1085,6 @@ reset-names = "axi", "ahb", "dclk"; iommus = <&vopb_mmu>; power-domains = <&power PX30_PD_VO>; - rockchip,grf = <&grf>; status = "disabled"; vopb_out: port { @@ -1052,7 +1107,6 @@ compatible = "rockchip,iommu"; reg = <0x0 0xff460f00 0x0 0x100>; interrupts = ; - interrupt-names = "vopb_mmu"; clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>; clock-names = "aclk", "iface"; power-domains = <&power PX30_PD_VO>; @@ -1071,7 +1125,6 @@ reset-names = "axi", "ahb", "dclk"; iommus = <&vopl_mmu>; power-domains = <&power PX30_PD_VO>; - rockchip,grf = <&grf>; status = "disabled"; vopl_out: port { @@ -1093,8 +1146,7 @@ vopl_mmu: iommu@ff470f00 { compatible = "rockchip,iommu"; reg = <0x0 0xff470f00 0x0 0x100>; - interrupts = ; - interrupt-names = "vopl_mmu"; + interrupts = ; clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>; clock-names = "aclk", "iface"; power-domains = <&power PX30_PD_VO>; @@ -1103,102 +1155,102 @@ }; qos_gmac: qos@ff518000 { - compatible = "syscon"; + compatible = "rockchip,px30-qos", "syscon"; reg = <0x0 0xff518000 0x0 0x20>; }; qos_gpu: qos@ff520000 { - compatible = "syscon"; + compatible = "rockchip,px30-qos", "syscon"; reg = <0x0 0xff520000 0x0 0x20>; }; qos_sdmmc: qos@ff52c000 { - compatible = "syscon"; + compatible = "rockchip,px30-qos", "syscon"; reg = <0x0 0xff52c000 0x0 0x20>; }; qos_emmc: qos@ff538000 { - compatible = "syscon"; + compatible = "rockchip,px30-qos", "syscon"; reg = <0x0 0xff538000 0x0 0x20>; }; qos_nand: qos@ff538080 { - compatible = "syscon"; + compatible = "rockchip,px30-qos", "syscon"; reg = <0x0 0xff538080 0x0 0x20>; }; qos_sdio: qos@ff538100 { - compatible = "syscon"; + compatible = "rockchip,px30-qos", "syscon"; reg = <0x0 0xff538100 0x0 0x20>; }; qos_sfc: qos@ff538180 { - compatible = "syscon"; + compatible = "rockchip,px30-qos", "syscon"; reg = <0x0 0xff538180 0x0 0x20>; }; qos_usb_host: qos@ff540000 { - compatible = "syscon"; + compatible = "rockchip,px30-qos", "syscon"; reg = <0x0 0xff540000 0x0 0x20>; }; qos_usb_otg: qos@ff540080 { - compatible = "syscon"; + compatible = "rockchip,px30-qos", "syscon"; reg = <0x0 0xff540080 0x0 0x20>; }; qos_isp_128: qos@ff548000 { - compatible = "syscon"; + compatible = "rockchip,px30-qos", "syscon"; reg = <0x0 0xff548000 0x0 0x20>; }; qos_isp_rd: qos@ff548080 { - compatible = "syscon"; + compatible = "rockchip,px30-qos", "syscon"; reg = <0x0 0xff548080 0x0 0x20>; }; qos_isp_wr: qos@ff548100 { - compatible = "syscon"; + compatible = "rockchip,px30-qos", "syscon"; reg = <0x0 0xff548100 0x0 0x20>; }; qos_isp_m1: qos@ff548180 { - compatible = "syscon"; + compatible = "rockchip,px30-qos", "syscon"; reg = <0x0 0xff548180 0x0 0x20>; }; qos_vip: qos@ff548200 { - compatible = "syscon"; + compatible = "rockchip,px30-qos", "syscon"; reg = <0x0 0xff548200 0x0 0x20>; }; qos_rga_rd: qos@ff550000 { - compatible = "syscon"; + compatible = "rockchip,px30-qos", "syscon"; reg = <0x0 0xff550000 0x0 0x20>; }; qos_rga_wr: qos@ff550080 { - compatible = "syscon"; + compatible = "rockchip,px30-qos", "syscon"; reg = <0x0 0xff550080 0x0 0x20>; }; qos_vop_m0: qos@ff550100 { - compatible = "syscon"; + compatible = "rockchip,px30-qos", "syscon"; reg = <0x0 0xff550100 0x0 0x20>; }; qos_vop_m1: qos@ff550180 { - compatible = "syscon"; + compatible = "rockchip,px30-qos", "syscon"; reg = <0x0 0xff550180 0x0 0x20>; }; qos_vpu: qos@ff558000 { - compatible = "syscon"; + compatible = "rockchip,px30-qos", "syscon"; reg = <0x0 0xff558000 0x0 0x20>; }; qos_vpu_r128: qos@ff558080 { - compatible = "syscon"; + compatible = "rockchip,px30-qos", "syscon"; reg = <0x0 0xff558080 0x0 0x20>; }; @@ -1370,7 +1422,7 @@ }; tsadc { - tsadc_otp_gpio: tsadc-otp-gpio { + tsadc_otp_pin: tsadc-otp-pin { rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; }; From patchwork Wed Nov 3 09:04:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suniel Mahesh X-Patchwork-Id: 1726 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pf1-f197.google.com (mail-pf1-f197.google.com [209.85.210.197]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 46DDE3F09E for ; Wed, 3 Nov 2021 10:04:56 +0100 (CET) Received: by mail-pf1-f197.google.com with SMTP id r2-20020a627602000000b00480f8ce37absf997050pfc.8 for ; Wed, 03 Nov 2021 02:04:56 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1635930295; cv=pass; d=google.com; s=arc-20160816; b=rwAcqGfbaj9rJ6nsidpSo4QMQ3+cas3W/r+3f8MWjnkLqbY8iLYutPi/yK7+HhDvuE hyiO/5fyFFinnfd13VdlLRjzjEcM21jlXz9dfbPFEFscHSUKDu+bmCckbAQXHy5PZeWh hDpmiwN8irFm0y3S8B04AumuF+61j6YrXxd23nRy0o5yop+NkNsUbuU+ouIdgQI8a0Bv GiujTbWpYh1DefdSGKLSaBmvHTE16aGWnhWmUhax8V4RoF5HwZNpIXU+sPFMkemY6tA9 3qujp0dBlfSKxH4dAE6wdXUpqqBG9C53yVap8BnqQtD35Ic64PLnYGoHb+CpGqEXg007 c0Uw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=dLwsw0nNBYcD2Lprp4togu4ciQ6PLfNQpxHV54bbBI8=; b=jhasiYgiLsTzZbwMknHiqbmYMUNmXsIkjkxnZUzwXVGtpY648wPUMYAIxqzbMfCDy0 0R3N5mNNLqZBoMAFDl7woJ2O9h/jfVeDzBxfL3fevPf9qIjoXeoJ+5XPLdjEV8e7lOY0 9+faJvceKgtCrfFCXqDLwKZ0+FLpNwEiQcZsE7XwxpAjWPh1WLs4zjW3HNISMgvoktCs 6rZRxvSsXlWy9FQ1tlRFXhxTErZGvq3wbBboR4U6E8U2e1I0Qeb/VcqNaw57HTwBf36a zKHbz3mjWUe57plqo6dylri4A81peU3nwdpo8oYR5ipT20gFkLuA7NuQVkUUA/+dWL5h ggZg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=EAOukKAR; spf=pass (google.com: domain of sunil@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=sunil@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=dLwsw0nNBYcD2Lprp4togu4ciQ6PLfNQpxHV54bbBI8=; b=n+99jyRsfYY2UVj5+RZ1Ic+oObDTGlLM1cX7a7SpPWcrks6kzqka9nMpeq48vjANI8 KXgamXolMBffU61/jnB48sko6bcY93bcBoQJ9iXdJJW4xYa2JQNDNyNm8fFF6Q+JeBcm bBNCR+q9MXX8KNKU/FeI6AJFALjaOwrsE6+UI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=dLwsw0nNBYcD2Lprp4togu4ciQ6PLfNQpxHV54bbBI8=; b=VA7Or5DtCtaDOwzS7R1CiCrBo63XK8ltt/yNm6qLWnI/Y/TKz1dxpBP+dXEcweFD3m XNBx2sp4/XBrlN6fC9R26NjYqrrbwTeCtma6Yl+REZ7j+sr0LcHUpnuD/1rU+s9d7XiL rKLIPV4oWohi45/NuhxQ8PAVz1WvEWwNr7pIdiLrvP4XBIeUwXasz2DFg4oenFmUydj9 Z+WzW5ywE1OP5wX0koxIHwMFRa3QYsdW9ZE+Q2UYRUPNpGsF08dznhFjPdYTmUuUMqJZ 5NYjuXCXDQSyWcwZhC9sa/HuACFrzBq4S6RSblLUnSvNqsbP47zQppShCmj4S6YPAoKV 4lTg== X-Gm-Message-State: AOAM531qaboL4pdAFiF/AF1QjwQlxypvlm1wX/zWlrXBaGezDCKWgwM9 CiA7PtR7RjTYjeIV4Gqhrfv8VFz3 X-Google-Smtp-Source: ABdhPJzadeumZ/eXkHT+F8xa6rnkrryntIqIxBOO7bY88jGTnpCcOOLS8KlF24qjNP3Y+uKN4hZyAw== X-Received: by 2002:a62:1496:0:b0:47b:d2ba:8791 with SMTP id 144-20020a621496000000b0047bd2ba8791mr42682741pfu.18.1635930295061; Wed, 03 Nov 2021 02:04:55 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a05:6a00:853:: with SMTP id q19ls97006pfk.8.gmail; Wed, 03 Nov 2021 02:04:54 -0700 (PDT) X-Received: by 2002:a63:4b22:: with SMTP id y34mr14166756pga.382.1635930294284; Wed, 03 Nov 2021 02:04:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635930294; cv=none; d=google.com; s=arc-20160816; b=YVmOsn8/LnvI97R2WN9v+3tq0BsuyfxrMSGZbis8W0J48tYsTZYH7y7FO7SCvWI683 WIkK6b0ccQAOeMZS4FtutDrhbwUccVwVbUFP4dSjQLM+D+9pvxjfRTT3XEEmgo907Laf hyRvIBA/TCMqGaUkPRnas+yPqtKfOUwwpX9lrxLQSH3BvwU8iQV5PUH6b33SC4Qib4LV 10Ik9oZYgTsh7iSvP6QtvKrOKjzbbvS68WCLY77nPWqmuZG/WAObA9iNtyYSDSuSDwCa 5TOnkCDY90GQmFI+rOAL82fWLuFXWm0/inRT9B1la7SlCdnicP5JTyd4GegI2eGgH6cA NhDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=QEvUtHo0TwnmdCSPLWrixHcYBzGIkl7xDxrjWsfX/uA=; b=N6H1RP1W7CAMd/eNtShdEhyk1RlxS5RMgXmO7EgRnwy5cnxGBtBY27c7U+NCgcpjqp /0YEvhj+eUEQKmSpfE56dXA3kR47BXhMo6Zg/nDqdnDhhX54Q6krQybAe9zGQgtX4YFO B7xyHz2UAs4cT7OkHwvm+1Z/3IYYvbuvMBdRERThp0raQ8G9JUFrnYlH9KnV99ahRX8X Fl0R3LI4jfeZFfd6ewgDEGZ6mIv81gkcbfsPv6MHnZpTlrbFG7rHU1Ucls3UQxIxI5L2 HA29echJDJYvOBYxJ09dOeIjFkv6TcGUe1wlM00OTnQAlsxZVSIwJatThiL3HFHTZCmL Ssdg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=EAOukKAR; spf=pass (google.com: domain of sunil@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=sunil@amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id q11sor959026plx.41.2021.11.03.02.04.54 for (Google Transport Security); Wed, 03 Nov 2021 02:04:54 -0700 (PDT) Received-SPF: pass (google.com: domain of sunil@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:902:b593:b0:12d:7aa5:de2d with SMTP id a19-20020a170902b59300b0012d7aa5de2dmr37449256pls.31.1635930293975; Wed, 03 Nov 2021 02:04:53 -0700 (PDT) Received: from localhost.localdomain ([49.206.57.164]) by smtp.gmail.com with ESMTPSA id s2sm1802292pfg.167.2021.11.03.02.04.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Nov 2021 02:04:53 -0700 (PDT) From: Suniel Mahesh To: linux-amarula@amarulasolutions.com Cc: Jagan Teki Subject: [PATCH 4/5] engicam: px30: Add Engicam PX30.Core C.TOUCH 2.0 10.1" OF Date: Wed, 3 Nov 2021 14:34:27 +0530 Message-Id: <20211103090428.12664-4-sunil@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211103090428.12664-1-sunil@amarulasolutions.com> References: <20211103090428.12664-1-sunil@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: sunil@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=EAOukKAR; spf=pass (google.com: domain of sunil@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=sunil@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Jagan Teki PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. C.TOUCH 2.0 is a general purpose carrier board with capacitive touch interface support. 10.1" OF is a capacitive touch 10.1" Open Frame panel solutions. PX30.Core needs to mount on top of C.TOUCH 2.0 carrier with pluged 10.1" OF for creating complete PX30.Core C.TOUCH 2.0 10.1" Open Frame. Add support for it. Signed-off-by: Jagan Teki Signed-off-by: Suniel Mahesh --- Changes for v2: - Tested on Engicam EDIMM2.2 with PX30 SOM based carrier board - new patch addition to the series - Rebased on top of v2022.01-rc1" --- arch/arm/dts/Makefile | 1 + arch/arm/mach-rockchip/px30/Kconfig | 8 ++ board/engicam/px30_core/MAINTAINERS | 6 + configs/px30-core-ctouch2-of10-px30_defconfig | 107 ++++++++++++++++++ 4 files changed, 122 insertions(+) create mode 100644 configs/px30-core-ctouch2-of10-px30_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 57a33d0bc4..95465d1dac 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -79,6 +79,7 @@ dtb-$(CONFIG_ROCKCHIP_PX30) += \ px30-evb.dtb \ px30-firefly.dtb \ px30-engicam-px30-core-ctouch2.dtb \ + px30-engicam-px30-core-ctouch2-of10.dtb \ px30-engicam-px30-core-edimm2.2.dtb \ rk3326-odroid-go2.dtb diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index aa5cc471ee..145bf3591f 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -27,6 +27,14 @@ config TARGET_PX30_CORE * PX30.Core needs to mount on top of CTOUCH2.0 for creating complete PX30.Core C.TOUCH Carrier board. + PX30.Core CTOUCH2-OF10: + * PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. + * CTOUCH2.0 is a general purpose Carrier board with capacitive + touch interface support. + * 10.1" OF is a capacitive touch 10.1" Open Frame panel solutions. + * PX30.Core needs to mount on top of C.TOUCH 2.0 carrier with pluged + 10.1" OF for creating complete PX30.Core C.TOUCH 2.0 10.1" Open Frame. + config ROCKCHIP_BOOT_MODE_REG default 0xff010200 diff --git a/board/engicam/px30_core/MAINTAINERS b/board/engicam/px30_core/MAINTAINERS index b87ca22207..77f0c2dba5 100644 --- a/board/engicam/px30_core/MAINTAINERS +++ b/board/engicam/px30_core/MAINTAINERS @@ -4,6 +4,12 @@ M: Suniel Mahesh S: Maintained F: configs/px30-core-ctouch2-px30_defconfig +PX30-Core-CTOUCH2.0-OF10 +M: Jagan Teki +M: Suniel Mahesh +S: Maintained +F: configs/px30-core-ctouch2-of10-px30_defconfig + PX30-Core-EDIMM2.2 M: Jagan Teki M: Suniel Mahesh diff --git a/configs/px30-core-ctouch2-of10-px30_defconfig b/configs/px30-core-ctouch2-of10-px30_defconfig new file mode 100644 index 0000000000..b92e876556 --- /dev/null +++ b/configs/px30-core-ctouch2-of10-px30_defconfig @@ -0,0 +1,107 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_TEXT_BASE=0x00000000 +CONFIG_ROCKCHIP_PX30=y +CONFIG_TARGET_PX30_CORE=y +CONFIG_DEBUG_UART_CHANNEL=1 +CONFIG_TPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_DEBUG_UART_BASE=0xFF160000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-ctouch2-of10" +CONFIG_DEBUG_UART=y +CONFIG_TPL_SYS_MALLOC_F_LEN=0x600 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/px30-engicam-px30-core-ctouch2-of10.dtb" +# CONFIG_CONSOLE_MUX is not set +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_MISC_INIT_R=y +CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_STACK_R=y +# CONFIG_TPL_BANNER_PRINT is not set +CONFIG_SPL_CRC32_SUPPORT=y +CONFIG_SPL_ATF=y +# CONFIG_TPL_FRAMEWORK is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNZIP is not set +CONFIG_CMD_GPT=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_BUF_SIZE=0x04000000 +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_ROCKCHIP_OTP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_ROCKCHIP_SDRAM_COMMON=y +CONFIG_DM_RESET=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y +# CONFIG_SPECIFY_CONSOLE_INDEX is not set +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SOUND=y +CONFIG_SYSRESET=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_LCD=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPL_TINY_MEMSET=y +CONFIG_LZO=y +CONFIG_ERRNO_STR=y From patchwork Wed Nov 3 09:04:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suniel Mahesh X-Patchwork-Id: 1727 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pg1-f197.google.com (mail-pg1-f197.google.com [209.85.215.197]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 2C6903F09E for ; Wed, 3 Nov 2021 10:05:02 +0100 (CET) Received: by mail-pg1-f197.google.com with SMTP id g18-20020a631112000000b00299f5f53824sf1204149pgl.2 for ; Wed, 03 Nov 2021 02:05:02 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1635930300; cv=pass; d=google.com; s=arc-20160816; b=CFlFZS3bUOBTE4y5YojGsl19fUTXyQZFIp1vwQbAiouZ6k07+BIluX0MHQqwXTvb88 mTRisCc5VWhReqI07a9cNSxuICqKsQZb0PAC5hCuXcjvgMG9MaVs45zcX9Y0fSfwP0ue /IhMpSjryFE0qqwF62n8S+GtHHo9pIHDenTYvAFv67MS/IW0+wAbn7zl3CKIG0Ca9g0q sW3mP2a+8RjmZL1d713PpQqA3a++VYhe1tWVjqvCN5R75fUh030kZRB4PGvhgc/6Yfn2 pS8WOsYwNvC4M9VJT5W3Q4C9b0MZVIXMYhaA0+McGEtHLnJJ9JcjgLvcslWkaxHqqxo/ nW1w== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=nXSj0he53Y7W2xUng4wrzFhtl4WXeG+iNJNGmaSaFtA=; b=X8w6asxGa4Z/dCBAlnx9yAI1I10C9hKJWNwfsC+6u3/AJVGhHCBwuPjmXboVH3yLzo L+8hPKuuw1cW6+Ff4K5EJQ1PWAAjWfcQrIRU0m8KqovHv4XqnyTEWyReO09bFBsH9fhV Uxwu/swnoaQhAxzSm80Ak/lNUKU+WPozIMR7CTesXrS0LtU2UGuHLPKUkcOA7weIx4E4 UruKwu8NX0SRnTx/pyGYR0wg+vCXW1GCbsIbjLi+NIqVVxRMIVuKS3LADZT2w/TicBwB 8iZwnhFK++0/qvidpMF8nP1klfMX0L2rD/ABFANQfK6rh0JbCdpNLL1WK8zNJpQJwM1h usTQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=GclgYK4W; spf=pass (google.com: domain of sunil@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=sunil@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=nXSj0he53Y7W2xUng4wrzFhtl4WXeG+iNJNGmaSaFtA=; b=G4GRmjLo7RFyJy7R+/dkUFrfKOg5N9zTZqjoQQ0U0U23TQkP8fZbOSvkFgiva+W1dZ 32PbWggw43MxHZpJKwVPf1+DIJlz869uW3pOEaEl6vX6Kyjked14szqxb0IittpFaZnM 3MeVTVg7VlYLyiAzGD4zOoRqRg4rXUmFMOzDY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=nXSj0he53Y7W2xUng4wrzFhtl4WXeG+iNJNGmaSaFtA=; b=ii6BdDHU3XOITK5yR9Qq2FjtHJLhVGkCnDneUkwLfUQWpQVvk9TaUa8Ixf7OS1eOHW cn3emol0794P+ib/iUazy/8ruhmWJX+zMSUL/jVNGDTV/lhSCgtUEUw1kG9ylDXmTJOG LkgVpieWPdkOegkREMzZWXGPIbIaur7Z2iG4l+3I5uOZjjenSQTPVn+N60wey0AuoouD 6oSvnrF522vCgvcBcsQ1JqaiQgXAAEm6MkfuyEUElZnkJEai1Bzc3B80OpWEXTGx+0+K q9s1ZNq3I+9QIeYXB/KuVZW+a2Q59q+pWeYksi13Bpc76RYwpmgZHorxKS/qKu0Qk5DM oQdg== X-Gm-Message-State: AOAM5316FosRyEPi9UMmLKTcMUOfY9gxHUHu8RhruaiweY4puwUIF5Me ldo4/wGhvy4FZr4a9XYq+ywx14WT X-Google-Smtp-Source: ABdhPJwX9Wu1hdNE5EVi0QyhD8eFtvzZ/Tj0O040RP3Uc/VMQqZsOcRVPHsripaYMkuBCzzDHrhW6w== X-Received: by 2002:a63:161b:: with SMTP id w27mr21168179pgl.261.1635930300675; Wed, 03 Nov 2021 02:05:00 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:902:da8c:: with SMTP id j12ls934923plx.4.gmail; Wed, 03 Nov 2021 02:05:00 -0700 (PDT) X-Received: by 2002:a17:903:1c3:b0:142:3ae:5c09 with SMTP id e3-20020a17090301c300b0014203ae5c09mr11165095plh.52.1635930299978; Wed, 03 Nov 2021 02:04:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635930299; cv=none; d=google.com; s=arc-20160816; b=QFToEfD7uWitr5wbSBy/IqtIJ7lf4zcS+MGUkWjzHHNFwNDThIqfGMuZ0YUtxH3gOy A2zqvirES1r7mNRI9YboMA/7mjahwxOlS5jeR3/PwaDRjhR9x07ixRbldUxcbT4LfGrQ XcYurya1c/AFnfqoq4CNZ/6KfO9syUfm2WheCRUrjDtI2qDV8v4UygGOSo7TSMmZ0WRZ kvHev5g34CU8+S4ephsXtq5z0WzTGrPmp8lbEfWuePpqxweXJr9xkbOuwsuG2TXHtiHU ShhzUTDlfqDpUd9AN6qXIRr4LV57OzPRvUX/tkOTHb26S3/ea03j0qLboM0fNxMNLxmb z3YQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=dEYOzalRstO1a24+4A1LuJVpgp55/3dC8XE3OMRrTG4=; b=JPh2d46ZKbEpryjhWDELgsOmSFN70LFCuQZ24MOJZjj26Ys2VwTLDj54I5UR/Cazsa GNV5QRUpucbuenAY4H1/34SBOOaRjg5+rd2rVjSubAQfQJ4HnfLu1+dL/meTm2LiV4Tc +62UkG6XIVBYDmZ3POsA8rPwtJ7utKaM0tYkSACFYw+rVnkwCjFLojZXXHjWcjl4cZp5 Q8jklA7UJWLvWeuppX9hYmZb1yrCa81cPOmWw0GM7KgH0SnWq3e06rp4LvkWbxBe+kvt 0D2WfXFX77PUjayN/HDKcIne5oz9BxC5i9h6W9V240dsJmF11N2j2Hswq3Li9SItzFRB R/cg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=GclgYK4W; spf=pass (google.com: domain of sunil@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=sunil@amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id l16sor854993pfc.31.2021.11.03.02.04.59 for (Google Transport Security); Wed, 03 Nov 2021 02:04:59 -0700 (PDT) Received-SPF: pass (google.com: domain of sunil@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:aa7:8b56:0:b0:44c:10a:4ee9 with SMTP id i22-20020aa78b56000000b0044c010a4ee9mr43232251pfd.46.1635930299579; Wed, 03 Nov 2021 02:04:59 -0700 (PDT) Received: from localhost.localdomain ([49.206.57.164]) by smtp.gmail.com with ESMTPSA id s2sm1802292pfg.167.2021.11.03.02.04.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Nov 2021 02:04:59 -0700 (PDT) From: Suniel Mahesh To: linux-amarula@amarulasolutions.com Cc: Jagan Teki Subject: [PATCH 5/5] engicam: Rename board dir, px30_core to px30 Date: Wed, 3 Nov 2021 14:34:28 +0530 Message-Id: <20211103090428.12664-5-sunil@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211103090428.12664-1-sunil@amarulasolutions.com> References: <20211103090428.12664-1-sunil@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: sunil@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=GclgYK4W; spf=pass (google.com: domain of sunil@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=sunil@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Jagan Teki Engicam hardware design solutions are based on System On Modules(SoM) with various SoCs like i.MX6, i.MX8 and PX30 etc. The current directory structure uses the simplest way to understand these designs by listing each of these SoC in board/engicam/SoC and inside SoC directory has SoM file name as a board file name. Right now all of the SoC's follow a similar approach except px30. So rename px30_core to px30. Signed-off-by: Jagan Teki Signed-off-by: Suniel Mahesh --- Changes for v2: - Tested on Engicam EDIMM2.2 with PX30 SOM based carrier board - new patch addition to the series - Rebased on top of v2022.01-rc1" --- arch/arm/mach-rockchip/px30/Kconfig | 2 +- board/engicam/{px30_core => px30}/Kconfig | 2 +- board/engicam/{px30_core => px30}/MAINTAINERS | 0 board/engicam/{px30_core => px30}/Makefile | 0 board/engicam/{px30_core => px30}/px30_core.c | 0 5 files changed, 2 insertions(+), 2 deletions(-) rename board/engicam/{px30_core => px30}/Kconfig (90%) rename board/engicam/{px30_core => px30}/MAINTAINERS (100%) rename board/engicam/{px30_core => px30}/Makefile (100%) rename board/engicam/{px30_core => px30}/px30_core.c (100%) diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index 145bf3591f..0a94391512 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -68,7 +68,7 @@ config DEBUG_UART_CHANNEL For using the UART for early debugging the route to use needs to be declared (0 or 1). -source "board/engicam/px30_core/Kconfig" +source "board/engicam/px30/Kconfig" source "board/hardkernel/odroid_go2/Kconfig" source "board/rockchip/evb_px30/Kconfig" diff --git a/board/engicam/px30_core/Kconfig b/board/engicam/px30/Kconfig similarity index 90% rename from board/engicam/px30_core/Kconfig rename to board/engicam/px30/Kconfig index a03be78369..10a7ec203f 100644 --- a/board/engicam/px30_core/Kconfig +++ b/board/engicam/px30/Kconfig @@ -1,7 +1,7 @@ if TARGET_PX30_CORE config SYS_BOARD - default "px30_core" + default "px30" config SYS_VENDOR default "engicam" diff --git a/board/engicam/px30_core/MAINTAINERS b/board/engicam/px30/MAINTAINERS similarity index 100% rename from board/engicam/px30_core/MAINTAINERS rename to board/engicam/px30/MAINTAINERS diff --git a/board/engicam/px30_core/Makefile b/board/engicam/px30/Makefile similarity index 100% rename from board/engicam/px30_core/Makefile rename to board/engicam/px30/Makefile diff --git a/board/engicam/px30_core/px30_core.c b/board/engicam/px30/px30_core.c similarity index 100% rename from board/engicam/px30_core/px30_core.c rename to board/engicam/px30/px30_core.c