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[209.85.220.41]) by mx.google.com with SMTPS id lk12sor1630062pjb.35.2021.11.11.02.15.15 for (Google Transport Security); Thu, 11 Nov 2021 02:15:15 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:90b:4b86:: with SMTP id lr6mr6847752pjb.98.1636625714755; Thu, 11 Nov 2021 02:15:14 -0800 (PST) Received: from localhost.localdomain ([2405:201:c00a:a0a9:3041:135c:4e21:846c]) by smtp.gmail.com with ESMTPSA id t12sm8035667pjo.44.2021.11.11.02.15.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Nov 2021 02:15:14 -0800 (PST) From: Jagan Teki To: Tim Harvey , Adam Ford , Fabio Estevam , Lucas Stach , Peng Fan , Shawn Guo , Marek Vasut , Frieder Schrempf Cc: NXP Linux Team , linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-amarula@amarulasolutions.com, Matteo Lisi , Jagan Teki Subject: [RFC PATCH v2 1/3] arm64: dts: imx8mm: Add eLCDIF node support Date: Thu, 11 Nov 2021 15:44:54 +0530 Message-Id: <20211111101456.584061-2-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211111101456.584061-1-jagan@amarulasolutions.com> References: <20211111101456.584061-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=X7UxPIRa; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add eLCDIF controller node for i.MX8MM. Signed-off-by: Jagan Teki --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index c2f3f118f82e..caeb93313413 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1068,6 +1068,25 @@ aips4: bus@32c00000 { #size-cells = <1>; ranges = <0x32c00000 0x32c00000 0x400000>; + lcdif: lcdif@32e00000 { + compatible = "fsl,imx28-lcdif"; + reg = <0x32e00000 0x10000>; + clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>, + <&clk IMX8MM_CLK_DISP_AXI_ROOT>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>; + clock-names = "pix", "disp_axi", "axi"; + assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>, + <&clk IMX8MM_CLK_DISP_AXI>, + <&clk IMX8MM_CLK_DISP_APB>; + assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>, + <&clk IMX8MM_SYS_PLL2_1000M>, + <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rate = <594000000>, <500000000>, <200000000>; + interrupts = ; + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>; + status = "disabled"; + }; + disp_blk_ctrl: blk-ctrl@32e28000 { compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon"; reg = <0x32e28000 0x100>; From patchwork Thu Nov 11 10:14:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1738 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pl1-f199.google.com (mail-pl1-f199.google.com [209.85.214.199]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 20FC33F075 for ; Thu, 11 Nov 2021 11:15:22 +0100 (CET) Received: by mail-pl1-f199.google.com with SMTP id m15-20020a170902bb8f00b0014382b67873sf1787928pls.19 for ; Thu, 11 Nov 2021 02:15:22 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1636625720; cv=pass; d=google.com; s=arc-20160816; b=VPGbkPv1OjjETa6Nm79wAhtTepX+zDVmysCVRh12HsITiNhsnCG2cKAOtHnr0djpKm 3yXxSSuAoWXwDbgLKDnOOBPgw/echsy/nVWs9Y0IRD3P0D4HyafABxs/BUqfQQ05b9UD jE8vzoY0GCOGEm1byN9D3GLWU7IYFfth9M28aczDNvOWHVgwyx6nFEAhh1rVbf2QYk9U 4S4BzHSn/zhWeQuWcAnN4NLiQjfVBE/5wuzm66k5ACrpcLI4DJVimp48+1m+t87wGzx5 9oehiZBH4XL0bvay3WdPnYlC0hw0hvn/KcfEQzQLUCA0muT9p5gG4D+MUejc8XyQyZZC wU3w== ARC-Message-Signature: i=2; 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[209.85.220.41]) by mx.google.com with SMTPS id d18sor1411545pfv.20.2021.11.11.02.15.19 for (Google Transport Security); Thu, 11 Nov 2021 02:15:19 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:aa7:9101:0:b0:49f:af85:b72c with SMTP id 1-20020aa79101000000b0049faf85b72cmr5502332pfh.53.1636625719136; Thu, 11 Nov 2021 02:15:19 -0800 (PST) Received: from localhost.localdomain ([2405:201:c00a:a0a9:3041:135c:4e21:846c]) by smtp.gmail.com with ESMTPSA id t12sm8035667pjo.44.2021.11.11.02.15.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Nov 2021 02:15:18 -0800 (PST) From: Jagan Teki To: Tim Harvey , Adam Ford , Fabio Estevam , Lucas Stach , Peng Fan , Shawn Guo , Marek Vasut , Frieder Schrempf Cc: NXP Linux Team , linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-amarula@amarulasolutions.com, Matteo Lisi , Jagan Teki Subject: [RFC PATCH v2 2/3] arm64: dts: imx8mm: Add MIPI DSI pipeline Date: Thu, 11 Nov 2021 15:44:55 +0530 Message-Id: <20211111101456.584061-3-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211111101456.584061-1-jagan@amarulasolutions.com> References: <20211111101456.584061-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=pX2LgSK0; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add MIPI DSI pipeline for i.MX8MM. Video pipeline start from eLCDIF to MIPI DSI and respective Panel or Bridge on the backend side. Add support for it. Signed-off-by: Jagan Teki --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 55 +++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index caeb93313413..eddf3a467fd2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -188,6 +188,12 @@ clk_ext4: clock-ext4 { clock-output-names = "clk_ext4"; }; + mipi_phy: mipi-video-phy { + compatible = "fsl,imx8mm-mipi-video-phy"; + syscon = <&disp_blk_ctrl>; + #phy-cells = <1>; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -1085,6 +1091,55 @@ lcdif: lcdif@32e00000 { interrupts = ; power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>; status = "disabled"; + + port { + lcdif_out_dsi: endpoint { + remote-endpoint = <&dsi_in_lcdif>; + }; + }; + }; + + dsi: dsi@32e10000 { + compatible = "fsl,imx8mm-mipi-dsim"; + reg = <0x32e10000 0x400>; + clocks = <&clk IMX8MM_CLK_DSI_CORE>, + <&clk IMX8MM_CLK_DSI_PHY_REF>; + clock-names = "bus_clk", "sclk_mipi"; + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>, + <&clk IMX8MM_VIDEO_PLL1_OUT>, + <&clk IMX8MM_CLK_DSI_PHY_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, + <&clk IMX8MM_VIDEO_PLL1_BYPASS>, + <&clk IMX8MM_VIDEO_PLL1_OUT>; + assigned-clock-rates = <266000000>, <594000000>, <27000000>; + interrupts = ; + phys = <&mipi_phy 0>; + phy-names = "dsim"; + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>; + samsung,burst-clock-frequency = <891000000>; + samsung,esc-clock-frequency = <54000000>; + samsung,pll-clock-frequency = <27000000>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dsi_in_lcdif: endpoint@0 { + reg = <0>; + remote-endpoint = <&lcdif_out_dsi>; + }; + }; + + port@1 { + reg = <1>; + }; + }; }; disp_blk_ctrl: blk-ctrl@32e28000 { From patchwork Thu Nov 11 10:14:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1739 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pl1-f197.google.com (mail-pl1-f197.google.com [209.85.214.197]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 62C803F075 for ; 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[209.85.220.41]) by mx.google.com with SMTPS id oa7sor6053474pjb.20.2021.11.11.02.15.24 for (Google Transport Security); Thu, 11 Nov 2021 02:15:24 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:90b:33d0:: with SMTP id lk16mr6984798pjb.66.1636625723610; Thu, 11 Nov 2021 02:15:23 -0800 (PST) Received: from localhost.localdomain ([2405:201:c00a:a0a9:3041:135c:4e21:846c]) by smtp.gmail.com with ESMTPSA id t12sm8035667pjo.44.2021.11.11.02.15.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Nov 2021 02:15:23 -0800 (PST) From: Jagan Teki To: Tim Harvey , Adam Ford , Fabio Estevam , Lucas Stach , Peng Fan , Shawn Guo , Marek Vasut , Frieder Schrempf Cc: NXP Linux Team , linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-amarula@amarulasolutions.com, Matteo Lisi , Jagan Teki Subject: [RFC PATCH v2 3/3] arm64: dts: imx8mm-icore: Enable LVDS panel for EDIMM2.2 Date: Thu, 11 Nov 2021 15:44:56 +0530 Message-Id: <20211111101456.584061-4-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211111101456.584061-1-jagan@amarulasolutions.com> References: <20211111101456.584061-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=AODSSiz+; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Enable LVDS Panel for Engicam i.Core MX8MMini EDIMM2.2 board. Signed-off-by: Jagan Teki --- .../freescale/imx8mm-icore-mx8mm-edimm2.2.dts | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts index a4a2ada14835..58065fee27f6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts @@ -14,9 +14,45 @@ / { compatible = "engicam,icore-mx8mm-edimm2.2", "engicam,icore-mx8mm", "fsl,imx8mm"; + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + pwms = <&pwm1 0 1000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + chosen { stdout-path = &uart2; }; + + panel { + compatible = "yes-optoelectronics,ytc700tlag-05-201c"; + backlight = <&backlight>; + + port { + panel_out_bridge: endpoint { + remote-endpoint = <&bridge_out_panel>; + }; + }; + }; +}; + +&dsi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + dsi_out_bridge: endpoint { + remote-endpoint = <&bridge_in_dsi>; + }; + }; + }; }; &fec1 { @@ -35,9 +71,44 @@ &i2c4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c4>; status = "okay"; + + bridge@2c { + compatible = "ti,sn65dsi84"; + reg = <0x2c>; + enable-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dsi_bridge_enable>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + bridge_in_dsi: endpoint { + remote-endpoint = <&dsi_out_bridge>; + data-lanes = <0 1>; + }; + }; + + port@2 { + reg = <2>; + bridge_out_panel: endpoint { + remote-endpoint = <&panel_out_bridge>; + }; + }; + }; + }; }; &iomuxc { + pinctrl_dsi_bridge_enable: dsibridgeenablegrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 + MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x19 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 @@ -52,6 +123,12 @@ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 >; }; + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x19 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 @@ -77,6 +154,14 @@ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 }; }; +&lcdif { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>;