From patchwork Fri Apr  8 16:20:58 2022
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
X-Patchwork-Submitter: Jagan Teki <jagan@amarulasolutions.com>
X-Patchwork-Id: 1902
Return-Path: 
 <linux-amarula+bncBD7MFH7A7EEBBOWCYGJAMGQE3K54WQY@amarulasolutions.com>
X-Original-To: linux-amarula@patchwork.amarulasolutions.com
Delivered-To: linux-amarula@patchwork.amarulasolutions.com
Received: from mail-pf1-f199.google.com (mail-pf1-f199.google.com
	[209.85.210.199])
	by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 13F083F066
	for <linux-amarula@patchwork.amarulasolutions.com>;
	Fri,  8 Apr 2022 18:22:20 +0200 (CEST)
Received: by mail-pf1-f199.google.com with SMTP id
	g5-20020a62f945000000b0050578328060sf1867469pfm.17
	for <linux-amarula@patchwork.amarulasolutions.com>;
	Fri, 08 Apr 2022 09:22:20 -0700 (PDT)
ARC-Seal: i=2; a=rsa-sha256; t=1649434939; cv=pass;
	d=google.com; s=arc-20160816;
	b=dalhmyDyMR8KdRQ09Tx8XA3levt6Ev1/Z56aZ4aCMqkEQ5qwUqylTc0dZqU4eYp0bP
	oRqJZuz91RB3Rl8+RjH6GYVe8+K4B/e8tscapysDeWucYjWyP8FlcvYS5WP8j26uBYGO
	jhzffBom0HdD4xn78/xompATrfAJs0Ia4dNOQqlFkxeDAzABvs1MHcGlYpIoQ19j1tf8
	9ok6SKgRbrMuZGMEEV7X52STMcc6T3r7Q/eYJYWloD7p/iUHPd8dqS4EqVW1IMFrYf+0
	bac5ElhvcsXz/UshIOrKJ1n6zP7wK7s3hOVygjGFtBpXHkuPvbC1ZW1nlVjPAhadOegi
	fRKA==
ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com;
	s=arc-20160816;
	h=list-unsubscribe:list-archive:list-help:list-post:list-id
	:mailing-list:precedence:content-transfer-encoding:mime-version
	:references:in-reply-to:message-id:date:subject:cc:to:from
	:dkim-signature;
	bh=FpYnxLi4gac2MI55GGmwm46CUaythRspEoDdeINyskc=;
	b=p1bayMJ1wj5LclRzfLOSGtVmKNtQH99aW35Gn2XH4UJ4eKLXfhg1moTS1io8/Oue4g
	pQUKGUedpZ2zUu1Jpl014h4ityZkWH7vBEJozvFmfk2CpiFTQA+cqG2Z+UFQwseEEAWU
	fBKAROzkC+6nBxnuOuONY1AbiOIiwWSe7owoVjGpIrL2On01En/paU5DLObuawY9eQyx
	KEn6OSFw3LVQ2hV09fBr7kcYZAVYDhi17HHjiyUmxAP0LEmAlwQ4AKvIFsK0xIYd3j6r
	/RjXzJVHzXLq77h6liT+LzTc9cfe4hhx1G61GSl3pDJGp8oc6ZdOu/TyLi6MJqoiQPC3
	1cZQ==
ARC-Authentication-Results: i=2; mx.google.com;
	dkim=pass header.i=@amarulasolutions.com header.s=google
	header.b=dP2QHqYn;
	spf=pass (google.com: domain of jagan@amarulasolutions.com designates
	209.85.220.41 as permitted sender)
	smtp.mailfrom=jagan@amarulasolutions.com;
	dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
	d=amarulasolutions.com; s=google;
	h=from:to:cc:subject:date:message-id:in-reply-to:references
	:mime-version:content-transfer-encoding:x-original-sender
	:x-original-authentication-results:precedence:mailing-list:list-id
	:list-post:list-help:list-archive:list-unsubscribe;
	bh=FpYnxLi4gac2MI55GGmwm46CUaythRspEoDdeINyskc=;
	b=Xp8jHLjmHnR3QJrocAh4B0MVqr0tVrzmpDVtUDexNQzfpr4Pl7CfL8ycnTQFe9Mc2Q
	+rXGl3fFKxlmOuVO/CGhU1bPwLSUmg0keifOpZ4yCgZbEEDhyVgupo/tPGlK/DASrN9W
	Dg1q5sh1wn8q8Tr2Da9YXtrmqqo978agemFf8=
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
	d=1e100.net; s=20210112;
	h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to
	:references:mime-version:content-transfer-encoding:x-original-sender
	:x-original-authentication-results:precedence:mailing-list:list-id
	:x-spam-checked-in-group:list-post:list-help:list-archive
	:list-unsubscribe;
	bh=FpYnxLi4gac2MI55GGmwm46CUaythRspEoDdeINyskc=;
	b=20hvHGbhHDLrH3WPFBRKkQ7uGKdQe6MwuMjz+J0Lm06qPN8EQnnF8y5RRvJwep9NdF
	4FI9B/5EXoiVqH/8Uaxs3pdXbb4mycvXcgeFlHJ1SywXbfF44fYFeDcKBJR43aJ5Ta5y
	HxgDxU7JmbagVWymtLB6vyolCI0cbfjf98F3Opsl7oP44PlLGlRBBqXRbbkL8jZiOPqI
	zw7s1HClEWM1BIaDNiC8PiXmViQ81uGnN/J5oYbyIrRRr7Jh+a2e4OAhUxADrMY9hBZ+
	9CU/stOsQXLpXG4IG+wCVyQ7+5NFNruS/IpmVObPPCrvTUtMNALg8tkUvsoAYOuETDLB
	U5Fw==
X-Gm-Message-State: AOAM531UqN2RyfLibvpyT308RUkRWWEwAjvuT6bTFK2gyCjSlwF8zyKO
	xXy7/dATo+PAELl489Kg7qa97Zad
X-Google-Smtp-Source: 
 ABdhPJxct0cqgqvWZ0imPS4Zn8Hyx7TkZJAL/L0fz5XYxJFM0m6J2ZaQepenkmuMmprSG7ireP70Kw==
X-Received: by 2002:a17:90b:2516:b0:1ca:aa68:ca71 with SMTP id
	ns22-20020a17090b251600b001caaa68ca71mr22661576pjb.58.1649434938788;
	Fri, 08 Apr 2022 09:22:18 -0700 (PDT)
X-BeenThere: linux-amarula@amarulasolutions.com
Received: by 2002:a17:903:1cc:b0:157:1e76:6fe1 with SMTP id
	e12-20020a17090301cc00b001571e766fe1ls2204556plh.9.gmail;
	Fri, 08 Apr 2022 09:22:18 -0700 (PDT)
X-Received: by 2002:a17:90b:1b01:b0:1c7:79d5:696 with SMTP id
	nu1-20020a17090b1b0100b001c779d50696mr22380097pjb.11.1649434937712;
	Fri, 08 Apr 2022 09:22:17 -0700 (PDT)
ARC-Seal: i=1; a=rsa-sha256; t=1649434937; cv=none;
	d=google.com; s=arc-20160816;
	b=THcoUJ0l2b9UDd/oQNbGFUi1r7g0L7aRSx0eTL53vVlxeznkzunKCmAoyRVwoYxqe1
	kXwqLZtxzXTHg+tJnK1CbR4QQzKw/UpQPyNwGzM4GRCaTpjX8Zet5A1ndl9DcayGZtRS
	t4+xNpCVRRUucYHEqbyVNCOBpRalZ2CeLrMUP2QJDv6u0oyNrF0Mvg9ktFd3V6ShBxCn
	SgZOFIOLiuoiARkih/DAQgjeATTjouAYXlk9fGty7P0Qez4PnLL4PQPVGi9IYk3e3STO
	QuWI3DO2v661zXke+hQRy5pqREJwFd2ov3ez5FFcGoCwofschLbfN62L1bq3RiLTJ7ql
	GckA==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com;
	s=arc-20160816;
	h=content-transfer-encoding:mime-version:references:in-reply-to
	:message-id:date:subject:cc:to:from:dkim-signature;
	bh=yFYPOZOPADwoXgFGXTmen69cS3AUy8rlr+D+K3XmPUU=;
	b=YRXfX/j8v1So5xoLO37/sizDOr8UqIoAg9/mQH+weaq8dBsISK5JDPeoFKREB+kyQZ
	k+J2Odp77plZzBky1kP95yrUtJY4H8B38hz++af1fBhYX0lpR6n0pnquCekXXNq+eNzM
	l0eldvjdoTmRtvRi2n9Vi15oibdiJL5Y33BexUGc3Ems4jWKZuAIGUZBqhED4YfKATGP
	eBon899DHLNq6SMrpl50gTXvStl55Ck+F9fAlhJ641H/oPIS+xRw63Pf2CKHZUgtkEEl
	A+WxsK8a4guukjsT2LGBKuBT35hx2HGaK6T2ix2sPEnCDoHCPvaQyRp10QtJiNn/gxYN
	xjYQ==
ARC-Authentication-Results: i=1; mx.google.com;
	dkim=pass header.i=@amarulasolutions.com header.s=google
	header.b=dP2QHqYn;
	spf=pass (google.com: domain of jagan@amarulasolutions.com designates
	209.85.220.41 as permitted sender)
	smtp.mailfrom=jagan@amarulasolutions.com;
	dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com
Received: from mail-sor-f41.google.com (mail-sor-f41.google.com.
	[209.85.220.41]) by mx.google.com with SMTPS id
	g30-20020aa79f1e000000b005056c5beb0fsor908329pfr.78.2022.04.08.09.22.17
	for <linux-amarula@amarulasolutions.com>
	(Google Transport Security); Fri, 08 Apr 2022 09:22:17 -0700 (PDT)
Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com
	designates 209.85.220.41 as permitted sender)
	client-ip=209.85.220.41;
X-Received: by 2002:a05:6a00:23c1:b0:4fa:efcb:9c81 with SMTP id
	g1-20020a056a0023c100b004faefcb9c81mr20124474pfc.75.1649434936743;
	Fri, 08 Apr 2022 09:22:16 -0700 (PDT)
Received: from j-ThinkPad-E14-Gen-2.domain.name ([45.249.78.214])
	by smtp.gmail.com with ESMTPSA id
	n18-20020a056a0007d200b004fdac35672fsm24929863pfu.68.2022.04.08.09.22.08
	(version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);
	Fri, 08 Apr 2022 09:22:16 -0700 (PDT)
From: Jagan Teki <jagan@amarulasolutions.com>
To: Andrzej Hajda <andrzej.hajda@intel.com>, Inki Dae <inki.dae@samsung.com>,
	Marek Szyprowski <m.szyprowski@samsung.com>,
	Joonyoung Shim <jy0922.shim@samsung.com>,
	Seung-Woo Kim <sw0312.kim@samsung.com>,
	Kyungmin Park <kyungmin.park@samsung.com>,
	Frieder Schrempf <frieder.schrempf@kontron.de>,
	Fancy Fang <chen.fang@nxp.com>, Tim Harvey <tharvey@gateworks.com>,
	Michael Nazzareno Trimarchi <michael@amarulasolutions.com>,
	Adam Ford <aford173@gmail.com>, Neil Armstrong <narmstrong@baylibre.com>,
	Robert Foss <robert.foss@linaro.org>,
	Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
	Rob Herring <robh+dt@kernel.org>
Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
	linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	NXP Linux Team <linux-imx@nxp.com>,
	linux-amarula <linux-amarula@amarulasolutions.com>,
	Jagan Teki <jagan@amarulasolutions.com>
Subject: [PATCH 01/11] drm: bridge: Add Samsung DSIM bridge driver
Date: Fri,  8 Apr 2022 21:50:58 +0530
Message-Id: <20220408162108.184583-2-jagan@amarulasolutions.com>
X-Mailer: git-send-email 2.25.1
In-Reply-To: <20220408162108.184583-1-jagan@amarulasolutions.com>
References: <20220408162108.184583-1-jagan@amarulasolutions.com>
MIME-Version: 1.0
Content-Type: text/plain; charset="UTF-8"
X-Original-Sender: jagan@amarulasolutions.com
X-Original-Authentication-Results: mx.google.com;       dkim=pass
	header.i=@amarulasolutions.com header.s=google header.b=dP2QHqYn;
	spf=pass (google.com: domain of jagan@amarulasolutions.com designates
	209.85.220.41 as permitted sender)
	smtp.mailfrom=jagan@amarulasolutions.com;
	dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com
Precedence: list
Mailing-list: list linux-amarula@amarulasolutions.com;
	contact linux-amarula+owners@amarulasolutions.com
List-ID: <linux-amarula.amarulasolutions.com>
X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com
X-Google-Group-Id: 476853432473
List-Post: 
 <https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/post>,
	<mailto:linux-amarula@amarulasolutions.com>
List-Help: 
 <https://support.google.com/a/amarulasolutions.com/bin/topic.py?topic=25838>,
	<mailto:linux-amarula+help@amarulasolutions.com>
List-Archive: 
 <https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/>
List-Unsubscribe: 
 <mailto:googlegroups-manage+476853432473+unsubscribe@googlegroups.com>,
	<https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/subscribe>

Samsung MIPI DSIM controller is common DSI IP that can be used in various
SoCs like Exynos, i.MX8M Mini/Nano.

In order to access this DSI controller between various platform SoCs, the
ideal way to incorporate this in the drm stack is via the drm bridge driver.

This patch is trying to differentiate platform-specific and bridge driver
code and keep maintaining the exynos_drm_dsi.c code as platform-specific
glue code and samsung-dsim.c as a common bridge driver code.

- Exynos specific glue code is exynos specific te_irq, host_attach, and
  detach code along with conventional component_ops.

- Samsung DSIM is a bridge driver which is common across all platforms and
  the respective platform-specific glue will initialize at the end of the
  probe. The platform-specific operations and other glue calls will invoke
  on associate code areas.

Updated MAINTAINERS file for this bridge with exynos drm maintainers along
with Andrzej as he is the original author.

Tomasz Figa has been not included in MAINTAINERS as he is not available via
samsung.com.

v1:
* Don't maintain component_ops in bridge driver
* Don't maintain platform glue code in bridge driver
* Add platform-specific glue code and make a common bridge

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 MAINTAINERS                             |   12 +
 drivers/gpu/drm/bridge/Kconfig          |   12 +
 drivers/gpu/drm/bridge/Makefile         |    1 +
 drivers/gpu/drm/bridge/samsung-dsim.c   | 1676 ++++++++++++++++++++++
 drivers/gpu/drm/exynos/Kconfig          |    1 +
 drivers/gpu/drm/exynos/exynos_drm_dsi.c | 1704 +----------------------
 include/drm/bridge/samsung-dsim.h       |   95 ++
 7 files changed, 1852 insertions(+), 1649 deletions(-)
 create mode 100644 drivers/gpu/drm/bridge/samsung-dsim.c
 create mode 100644 include/drm/bridge/samsung-dsim.h

diff --git a/MAINTAINERS b/MAINTAINERS
index db7fe53643c2..281d0f351854 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6227,6 +6227,18 @@ T:	git git://anongit.freedesktop.org/drm/drm-misc
 F:	Documentation/devicetree/bindings/display/panel/samsung,lms397kf04.yaml
 F:	drivers/gpu/drm/panel/panel-samsung-db7430.c
 
+DRM DRIVER FOR SAMSUNG MIPI DSIM BRIDGE
+M:	Inki Dae <inki.dae@samsung.com>
+M:	Joonyoung Shim <jy0922.shim@samsung.com>
+M:	Seung-Woo Kim <sw0312.kim@samsung.com>
+M:	Kyungmin Park <kyungmin.park@samsung.com>
+M:	Andrzej Hajda <andrzej.hajda@intel.com>
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+T:	git git://anongit.freedesktop.org/drm/drm-misc
+F:	drivers/gpu/drm/bridge/samsung-dsim.c
+F:	include/drm/bridge/samsung-dsim.h
+
 DRM DRIVER FOR SAMSUNG S6D27A1 PANELS
 M:	Markuss Broks <markuss.broks@gmail.com>
 S:	Maintained
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index e4cbf31797c5..10f839154e63 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -202,6 +202,18 @@ config DRM_PARADE_PS8640
 	  The PS8640 is a high-performance and low-power
 	  MIPI DSI to eDP converter
 
+config DRM_SAMSUNG_DSIM
+	tristate "Samsung MIPI DSIM bridge driver"
+	depends on COMMON_CLK
+	depends on OF && HAS_IOMEM
+	select DRM_KMS_HELPER
+	select DRM_MIPI_DSI
+	select DRM_PANEL_BRIDGE
+	help
+	  The Samsung MIPI DSIM bridge controller driver.
+	  This MIPI DSIM bridge can be found it on Exynos SoCs and
+	  NXP's i.MX8M Mini/Nano.
+
 config DRM_SIL_SII8620
 	tristate "Silicon Image SII8620 HDMI/MHL bridge"
 	depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 425844c30495..d1d2e6414fc5 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW) += megachips-stdpxxxx-ge-b850v
 obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
 obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
 obj-$(CONFIG_DRM_PARADE_PS8640) += parade-ps8640.o
+obj-$(CONFIG_DRM_SAMSUNG_DSIM) += samsung-dsim.o
 obj-$(CONFIG_DRM_SIL_SII8620) += sil-sii8620.o
 obj-$(CONFIG_DRM_SII902X) += sii902x.o
 obj-$(CONFIG_DRM_SII9234) += sii9234.o
diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
new file mode 100644
index 000000000000..ee5d7e5518a6
--- /dev/null
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -0,0 +1,1676 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Samsung MIPI DSIM bridge driver.
+ *
+ * Copyright (C) 2021 Amarula Solutions(India)
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * Based on exynos_drm_dsi from
+ * Tomasz Figa <t.figa@samsung.com>
+ */
+
+#include <asm/unaligned.h>
+
+#include <drm/bridge/samsung-dsim.h>
+#include <drm/drm_print.h>
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
+#include <linux/irq.h>
+#include <linux/of_device.h>
+#include <linux/phy/phy.h>
+#include <linux/regulator/consumer.h>
+
+#include <video/mipi_display.h>
+
+/* returns true iff both arguments logically differs */
+#define NEQV(a, b) (!(a) ^ !(b))
+
+/* DSIM_STATUS */
+#define DSIM_STOP_STATE_DAT(x)		(((x) & 0xf) << 0)
+#define DSIM_STOP_STATE_CLK		(1 << 8)
+#define DSIM_TX_READY_HS_CLK		(1 << 10)
+#define DSIM_PLL_STABLE			(1 << 31)
+
+/* DSIM_SWRST */
+#define DSIM_FUNCRST			(1 << 16)
+#define DSIM_SWRST			(1 << 0)
+
+/* DSIM_TIMEOUT */
+#define DSIM_LPDR_TIMEOUT(x)		((x) << 0)
+#define DSIM_BTA_TIMEOUT(x)		((x) << 16)
+
+/* DSIM_CLKCTRL */
+#define DSIM_ESC_PRESCALER(x)		(((x) & 0xffff) << 0)
+#define DSIM_ESC_PRESCALER_MASK		(0xffff << 0)
+#define DSIM_LANE_ESC_CLK_EN_CLK	(1 << 19)
+#define DSIM_LANE_ESC_CLK_EN_DATA(x)	(((x) & 0xf) << 20)
+#define DSIM_LANE_ESC_CLK_EN_DATA_MASK	(0xf << 20)
+#define DSIM_BYTE_CLKEN			(1 << 24)
+#define DSIM_BYTE_CLK_SRC(x)		(((x) & 0x3) << 25)
+#define DSIM_BYTE_CLK_SRC_MASK		(0x3 << 25)
+#define DSIM_PLL_BYPASS			(1 << 27)
+#define DSIM_ESC_CLKEN			(1 << 28)
+#define DSIM_TX_REQUEST_HSCLK		(1 << 31)
+
+/* DSIM_CONFIG */
+#define DSIM_LANE_EN_CLK		(1 << 0)
+#define DSIM_LANE_EN(x)			(((x) & 0xf) << 1)
+#define DSIM_NUM_OF_DATA_LANE(x)	(((x) & 0x3) << 5)
+#define DSIM_SUB_PIX_FORMAT(x)		(((x) & 0x7) << 8)
+#define DSIM_MAIN_PIX_FORMAT_MASK	(0x7 << 12)
+#define DSIM_MAIN_PIX_FORMAT_RGB888	(0x7 << 12)
+#define DSIM_MAIN_PIX_FORMAT_RGB666	(0x6 << 12)
+#define DSIM_MAIN_PIX_FORMAT_RGB666_P	(0x5 << 12)
+#define DSIM_MAIN_PIX_FORMAT_RGB565	(0x4 << 12)
+#define DSIM_SUB_VC			(((x) & 0x3) << 16)
+#define DSIM_MAIN_VC			(((x) & 0x3) << 18)
+#define DSIM_HSA_MODE			(1 << 20)
+#define DSIM_HBP_MODE			(1 << 21)
+#define DSIM_HFP_MODE			(1 << 22)
+#define DSIM_HSE_MODE			(1 << 23)
+#define DSIM_AUTO_MODE			(1 << 24)
+#define DSIM_VIDEO_MODE			(1 << 25)
+#define DSIM_BURST_MODE			(1 << 26)
+#define DSIM_SYNC_INFORM		(1 << 27)
+#define DSIM_EOT_DISABLE		(1 << 28)
+#define DSIM_MFLUSH_VS			(1 << 29)
+/* This flag is valid only for exynos3250/3472/5260/5430 */
+#define DSIM_CLKLANE_STOP		(1 << 30)
+
+/* DSIM_ESCMODE */
+#define DSIM_TX_TRIGGER_RST		(1 << 4)
+#define DSIM_TX_LPDT_LP			(1 << 6)
+#define DSIM_CMD_LPDT_LP		(1 << 7)
+#define DSIM_FORCE_BTA			(1 << 16)
+#define DSIM_FORCE_STOP_STATE		(1 << 20)
+#define DSIM_STOP_STATE_CNT(x)		(((x) & 0x7ff) << 21)
+#define DSIM_STOP_STATE_CNT_MASK	(0x7ff << 21)
+
+/* DSIM_MDRESOL */
+#define DSIM_MAIN_STAND_BY		(1 << 31)
+#define DSIM_MAIN_VRESOL(x, num_bits)	(((x) & ((1 << (num_bits)) - 1)) << 16)
+#define DSIM_MAIN_HRESOL(x, num_bits)	(((x) & ((1 << (num_bits)) - 1)) << 0)
+
+/* DSIM_MVPORCH */
+#define DSIM_CMD_ALLOW(x)		((x) << 28)
+#define DSIM_STABLE_VFP(x)		((x) << 16)
+#define DSIM_MAIN_VBP(x)		((x) << 0)
+#define DSIM_CMD_ALLOW_MASK		(0xf << 28)
+#define DSIM_STABLE_VFP_MASK		(0x7ff << 16)
+#define DSIM_MAIN_VBP_MASK		(0x7ff << 0)
+
+/* DSIM_MHPORCH */
+#define DSIM_MAIN_HFP(x)		((x) << 16)
+#define DSIM_MAIN_HBP(x)		((x) << 0)
+#define DSIM_MAIN_HFP_MASK		((0xffff) << 16)
+#define DSIM_MAIN_HBP_MASK		((0xffff) << 0)
+
+/* DSIM_MSYNC */
+#define DSIM_MAIN_VSA(x)		((x) << 22)
+#define DSIM_MAIN_HSA(x)		((x) << 0)
+#define DSIM_MAIN_VSA_MASK		((0x3ff) << 22)
+#define DSIM_MAIN_HSA_MASK		((0xffff) << 0)
+
+/* DSIM_SDRESOL */
+#define DSIM_SUB_STANDY(x)		((x) << 31)
+#define DSIM_SUB_VRESOL(x)		((x) << 16)
+#define DSIM_SUB_HRESOL(x)		((x) << 0)
+#define DSIM_SUB_STANDY_MASK		((0x1) << 31)
+#define DSIM_SUB_VRESOL_MASK		((0x7ff) << 16)
+#define DSIM_SUB_HRESOL_MASK		((0x7ff) << 0)
+
+/* DSIM_INTSRC */
+#define DSIM_INT_PLL_STABLE		(1 << 31)
+#define DSIM_INT_SW_RST_RELEASE		(1 << 30)
+#define DSIM_INT_SFR_FIFO_EMPTY		(1 << 29)
+#define DSIM_INT_SFR_HDR_FIFO_EMPTY	(1 << 28)
+#define DSIM_INT_BTA			(1 << 25)
+#define DSIM_INT_FRAME_DONE		(1 << 24)
+#define DSIM_INT_RX_TIMEOUT		(1 << 21)
+#define DSIM_INT_BTA_TIMEOUT		(1 << 20)
+#define DSIM_INT_RX_DONE		(1 << 18)
+#define DSIM_INT_RX_TE			(1 << 17)
+#define DSIM_INT_RX_ACK			(1 << 16)
+#define DSIM_INT_RX_ECC_ERR		(1 << 15)
+#define DSIM_INT_RX_CRC_ERR		(1 << 14)
+
+/* DSIM_FIFOCTRL */
+#define DSIM_RX_DATA_FULL		(1 << 25)
+#define DSIM_RX_DATA_EMPTY		(1 << 24)
+#define DSIM_SFR_HEADER_FULL		(1 << 23)
+#define DSIM_SFR_HEADER_EMPTY		(1 << 22)
+#define DSIM_SFR_PAYLOAD_FULL		(1 << 21)
+#define DSIM_SFR_PAYLOAD_EMPTY		(1 << 20)
+#define DSIM_I80_HEADER_FULL		(1 << 19)
+#define DSIM_I80_HEADER_EMPTY		(1 << 18)
+#define DSIM_I80_PAYLOAD_FULL		(1 << 17)
+#define DSIM_I80_PAYLOAD_EMPTY		(1 << 16)
+#define DSIM_SD_HEADER_FULL		(1 << 15)
+#define DSIM_SD_HEADER_EMPTY		(1 << 14)
+#define DSIM_SD_PAYLOAD_FULL		(1 << 13)
+#define DSIM_SD_PAYLOAD_EMPTY		(1 << 12)
+#define DSIM_MD_HEADER_FULL		(1 << 11)
+#define DSIM_MD_HEADER_EMPTY		(1 << 10)
+#define DSIM_MD_PAYLOAD_FULL		(1 << 9)
+#define DSIM_MD_PAYLOAD_EMPTY		(1 << 8)
+#define DSIM_RX_FIFO			(1 << 4)
+#define DSIM_SFR_FIFO			(1 << 3)
+#define DSIM_I80_FIFO			(1 << 2)
+#define DSIM_SD_FIFO			(1 << 1)
+#define DSIM_MD_FIFO			(1 << 0)
+
+/* DSIM_PHYACCHR */
+#define DSIM_AFC_EN			(1 << 14)
+#define DSIM_AFC_CTL(x)			(((x) & 0x7) << 5)
+
+/* DSIM_PLLCTRL */
+#define DSIM_FREQ_BAND(x)		((x) << 24)
+#define DSIM_PLL_EN			(1 << 23)
+#define DSIM_PLL_P(x)			((x) << 13)
+#define DSIM_PLL_M(x)			((x) << 4)
+#define DSIM_PLL_S(x)			((x) << 1)
+
+/* DSIM_PHYCTRL */
+#define DSIM_PHYCTRL_ULPS_EXIT(x)	(((x) & 0x1ff) << 0)
+#define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP	(1 << 30)
+#define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP	(1 << 14)
+
+/* DSIM_PHYTIMING */
+#define DSIM_PHYTIMING_LPX(x)		((x) << 8)
+#define DSIM_PHYTIMING_HS_EXIT(x)	((x) << 0)
+
+/* DSIM_PHYTIMING1 */
+#define DSIM_PHYTIMING1_CLK_PREPARE(x)	((x) << 24)
+#define DSIM_PHYTIMING1_CLK_ZERO(x)	((x) << 16)
+#define DSIM_PHYTIMING1_CLK_POST(x)	((x) << 8)
+#define DSIM_PHYTIMING1_CLK_TRAIL(x)	((x) << 0)
+
+/* DSIM_PHYTIMING2 */
+#define DSIM_PHYTIMING2_HS_PREPARE(x)	((x) << 16)
+#define DSIM_PHYTIMING2_HS_ZERO(x)	((x) << 8)
+#define DSIM_PHYTIMING2_HS_TRAIL(x)	((x) << 0)
+
+#define DSI_MAX_BUS_WIDTH		4
+#define DSI_NUM_VIRTUAL_CHANNELS	4
+#define DSI_TX_FIFO_SIZE		2048
+#define DSI_RX_FIFO_SIZE		256
+#define DSI_XFER_TIMEOUT_MS		100
+#define DSI_RX_FIFO_EMPTY		0x30800002
+
+#define OLD_SCLK_MIPI_CLK_NAME		"pll_clk"
+
+static const char *const clk_names[5] = {
+	"bus_clk",
+	"sclk_mipi",
+	"phyclk_mipidphy0_bitclkdiv8",
+	"phyclk_mipidphy0_rxclkesc0",
+	"sclk_rgb_vclk_to_dsim0"
+};
+
+enum samsung_dsim_transfer_type {
+	EXYNOS_DSI_TX,
+	EXYNOS_DSI_RX,
+};
+
+enum reg_idx {
+	DSIM_STATUS_REG,	/* Status register */
+	DSIM_SWRST_REG,		/* Software reset register */
+	DSIM_CLKCTRL_REG,	/* Clock control register */
+	DSIM_TIMEOUT_REG,	/* Time out register */
+	DSIM_CONFIG_REG,	/* Configuration register */
+	DSIM_ESCMODE_REG,	/* Escape mode register */
+	DSIM_MDRESOL_REG,
+	DSIM_MVPORCH_REG,	/* Main display Vporch register */
+	DSIM_MHPORCH_REG,	/* Main display Hporch register */
+	DSIM_MSYNC_REG,		/* Main display sync area register */
+	DSIM_INTSRC_REG,	/* Interrupt source register */
+	DSIM_INTMSK_REG,	/* Interrupt mask register */
+	DSIM_PKTHDR_REG,	/* Packet Header FIFO register */
+	DSIM_PAYLOAD_REG,	/* Payload FIFO register */
+	DSIM_RXFIFO_REG,	/* Read FIFO register */
+	DSIM_FIFOCTRL_REG,	/* FIFO status and control register */
+	DSIM_PLLCTRL_REG,	/* PLL control register */
+	DSIM_PHYCTRL_REG,
+	DSIM_PHYTIMING_REG,
+	DSIM_PHYTIMING1_REG,
+	DSIM_PHYTIMING2_REG,
+	NUM_REGS
+};
+
+static const unsigned int exynos_reg_ofs[] = {
+	[DSIM_STATUS_REG] =  0x00,
+	[DSIM_SWRST_REG] =  0x04,
+	[DSIM_CLKCTRL_REG] =  0x08,
+	[DSIM_TIMEOUT_REG] =  0x0c,
+	[DSIM_CONFIG_REG] =  0x10,
+	[DSIM_ESCMODE_REG] =  0x14,
+	[DSIM_MDRESOL_REG] =  0x18,
+	[DSIM_MVPORCH_REG] =  0x1c,
+	[DSIM_MHPORCH_REG] =  0x20,
+	[DSIM_MSYNC_REG] =  0x24,
+	[DSIM_INTSRC_REG] =  0x2c,
+	[DSIM_INTMSK_REG] =  0x30,
+	[DSIM_PKTHDR_REG] =  0x34,
+	[DSIM_PAYLOAD_REG] =  0x38,
+	[DSIM_RXFIFO_REG] =  0x3c,
+	[DSIM_FIFOCTRL_REG] =  0x44,
+	[DSIM_PLLCTRL_REG] =  0x4c,
+	[DSIM_PHYCTRL_REG] =  0x5c,
+	[DSIM_PHYTIMING_REG] =  0x64,
+	[DSIM_PHYTIMING1_REG] =  0x68,
+	[DSIM_PHYTIMING2_REG] =  0x6c,
+};
+
+static const unsigned int exynos5433_reg_ofs[] = {
+	[DSIM_STATUS_REG] = 0x04,
+	[DSIM_SWRST_REG] = 0x0C,
+	[DSIM_CLKCTRL_REG] = 0x10,
+	[DSIM_TIMEOUT_REG] = 0x14,
+	[DSIM_CONFIG_REG] = 0x18,
+	[DSIM_ESCMODE_REG] = 0x1C,
+	[DSIM_MDRESOL_REG] = 0x20,
+	[DSIM_MVPORCH_REG] = 0x24,
+	[DSIM_MHPORCH_REG] = 0x28,
+	[DSIM_MSYNC_REG] = 0x2C,
+	[DSIM_INTSRC_REG] = 0x34,
+	[DSIM_INTMSK_REG] = 0x38,
+	[DSIM_PKTHDR_REG] = 0x3C,
+	[DSIM_PAYLOAD_REG] = 0x40,
+	[DSIM_RXFIFO_REG] = 0x44,
+	[DSIM_FIFOCTRL_REG] = 0x4C,
+	[DSIM_PLLCTRL_REG] = 0x94,
+	[DSIM_PHYCTRL_REG] = 0xA4,
+	[DSIM_PHYTIMING_REG] = 0xB4,
+	[DSIM_PHYTIMING1_REG] = 0xB8,
+	[DSIM_PHYTIMING2_REG] = 0xBC,
+};
+
+enum reg_value_idx {
+	RESET_TYPE,
+	PLL_TIMER,
+	STOP_STATE_CNT,
+	PHYCTRL_ULPS_EXIT,
+	PHYCTRL_VREG_LP,
+	PHYCTRL_SLEW_UP,
+	PHYTIMING_LPX,
+	PHYTIMING_HS_EXIT,
+	PHYTIMING_CLK_PREPARE,
+	PHYTIMING_CLK_ZERO,
+	PHYTIMING_CLK_POST,
+	PHYTIMING_CLK_TRAIL,
+	PHYTIMING_HS_PREPARE,
+	PHYTIMING_HS_ZERO,
+	PHYTIMING_HS_TRAIL
+};
+
+static const unsigned int reg_values[] = {
+	[RESET_TYPE] = DSIM_SWRST,
+	[PLL_TIMER] = 500,
+	[STOP_STATE_CNT] = 0xf,
+	[PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af),
+	[PHYCTRL_VREG_LP] = 0,
+	[PHYCTRL_SLEW_UP] = 0,
+	[PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06),
+	[PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b),
+	[PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07),
+	[PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27),
+	[PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d),
+	[PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08),
+	[PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09),
+	[PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d),
+	[PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b),
+};
+
+static const unsigned int exynos5422_reg_values[] = {
+	[RESET_TYPE] = DSIM_SWRST,
+	[PLL_TIMER] = 500,
+	[STOP_STATE_CNT] = 0xf,
+	[PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf),
+	[PHYCTRL_VREG_LP] = 0,
+	[PHYCTRL_SLEW_UP] = 0,
+	[PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08),
+	[PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d),
+	[PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
+	[PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30),
+	[PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
+	[PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a),
+	[PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c),
+	[PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11),
+	[PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d),
+};
+
+static const unsigned int exynos5433_reg_values[] = {
+	[RESET_TYPE] = DSIM_FUNCRST,
+	[PLL_TIMER] = 22200,
+	[STOP_STATE_CNT] = 0xa,
+	[PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190),
+	[PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP,
+	[PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP,
+	[PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07),
+	[PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c),
+	[PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
+	[PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d),
+	[PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
+	[PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09),
+	[PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b),
+	[PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10),
+	[PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c),
+};
+
+static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = {
+	.reg_ofs = exynos_reg_ofs,
+	.plltmr_reg = 0x50,
+	.has_freqband = 1,
+	.has_clklane_stop = 1,
+	.num_clks = 2,
+	.max_freq = 1000,
+	.wait_for_reset = 1,
+	.num_bits_resol = 11,
+	.reg_values = reg_values,
+};
+
+static const struct samsung_dsim_driver_data exynos4_dsi_driver_data = {
+	.reg_ofs = exynos_reg_ofs,
+	.plltmr_reg = 0x50,
+	.has_freqband = 1,
+	.has_clklane_stop = 1,
+	.num_clks = 2,
+	.max_freq = 1000,
+	.wait_for_reset = 1,
+	.num_bits_resol = 11,
+	.reg_values = reg_values,
+};
+
+static const struct samsung_dsim_driver_data exynos5_dsi_driver_data = {
+	.reg_ofs = exynos_reg_ofs,
+	.plltmr_reg = 0x58,
+	.num_clks = 2,
+	.max_freq = 1000,
+	.wait_for_reset = 1,
+	.num_bits_resol = 11,
+	.reg_values = reg_values,
+};
+
+static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = {
+	.reg_ofs = exynos5433_reg_ofs,
+	.plltmr_reg = 0xa0,
+	.has_clklane_stop = 1,
+	.num_clks = 5,
+	.max_freq = 1500,
+	.wait_for_reset = 0,
+	.num_bits_resol = 12,
+	.reg_values = exynos5433_reg_values,
+};
+
+static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = {
+	.reg_ofs = exynos5433_reg_ofs,
+	.plltmr_reg = 0xa0,
+	.has_clklane_stop = 1,
+	.num_clks = 2,
+	.max_freq = 1500,
+	.wait_for_reset = 1,
+	.num_bits_resol = 12,
+	.reg_values = exynos5422_reg_values,
+};
+
+static const struct of_device_id samsung_dsim_of_match[] = {
+	{
+		.compatible = "samsung,exynos3250-mipi-dsi",
+		.data = &exynos3_dsi_driver_data
+	},
+	{
+		.compatible = "samsung,exynos4210-mipi-dsi",
+		.data = &exynos4_dsi_driver_data
+	},
+	{
+		.compatible = "samsung,exynos5410-mipi-dsi",
+		.data = &exynos5_dsi_driver_data
+	},
+	{
+		.compatible = "samsung,exynos5422-mipi-dsi",
+		.data = &exynos5422_dsi_driver_data
+	},
+	{
+		.compatible = "samsung,exynos5433-mipi-dsi",
+		.data = &exynos5433_dsi_driver_data
+	},
+	{ /* sentinel. */ }
+};
+
+static inline struct samsung_dsim *host_to_dsi(struct mipi_dsi_host *h)
+{
+	return container_of(h, struct samsung_dsim, dsi_host);
+}
+
+static inline struct samsung_dsim *bridge_to_dsi(struct drm_bridge *b)
+{
+	return container_of(b, struct samsung_dsim, bridge);
+}
+
+static inline void samsung_dsim_write(struct samsung_dsim *dsi,
+				      enum reg_idx idx, u32 val)
+{
+	writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
+}
+
+static inline u32 samsung_dsim_read(struct samsung_dsim *dsi, enum reg_idx idx)
+{
+	return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
+}
+
+static void samsung_dsim_wait_for_reset(struct samsung_dsim *dsi)
+{
+	if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
+		return;
+
+	dev_err(dsi->dev, "timeout waiting for reset\n");
+}
+
+static void samsung_dsim_reset(struct samsung_dsim *dsi)
+{
+	u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE];
+
+	reinit_completion(&dsi->completed);
+	samsung_dsim_write(dsi, DSIM_SWRST_REG, reset_val);
+}
+
+#ifndef MHZ
+#define MHZ	(1000*1000)
+#endif
+
+static unsigned long samsung_dsim_pll_find_pms(struct samsung_dsim *dsi,
+					       unsigned long fin,
+					       unsigned long fout,
+					       u8 *p, u16 *m, u8 *s)
+{
+	const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
+	unsigned long best_freq = 0;
+	u32 min_delta = 0xffffffff;
+	u8 p_min, p_max;
+	u8 _p, best_p;
+	u16 _m, best_m;
+	u8 _s, best_s;
+
+	p_min = DIV_ROUND_UP(fin, (12 * MHZ));
+	p_max = fin / (6 * MHZ);
+
+	for (_p = p_min; _p <= p_max; ++_p) {
+		for (_s = 0; _s <= 5; ++_s) {
+			u64 tmp;
+			u32 delta;
+
+			tmp = (u64)fout * (_p << _s);
+			do_div(tmp, fin);
+			_m = tmp;
+			if (_m < 41 || _m > 125)
+				continue;
+
+			tmp = (u64)_m * fin;
+			do_div(tmp, _p);
+			if (tmp < 500 * MHZ ||
+					tmp > driver_data->max_freq * MHZ)
+				continue;
+
+			tmp = (u64)_m * fin;
+			do_div(tmp, _p << _s);
+
+			delta = abs(fout - tmp);
+			if (delta < min_delta) {
+				best_p = _p;
+				best_m = _m;
+				best_s = _s;
+				min_delta = delta;
+				best_freq = tmp;
+			}
+		}
+	}
+
+	if (best_freq) {
+		*p = best_p;
+		*m = best_m;
+		*s = best_s;
+	}
+
+	return best_freq;
+}
+
+static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi,
+					  unsigned long freq)
+{
+	const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
+	unsigned long fin, fout;
+	int timeout;
+	u8 p, s;
+	u16 m;
+	u32 reg;
+
+	fin = dsi->pll_clk_rate;
+	fout = samsung_dsim_pll_find_pms(dsi, fin, freq, &p, &m, &s);
+	if (!fout) {
+		dev_err(dsi->dev,
+			"failed to find PLL PMS for requested frequency\n");
+		return 0;
+	}
+	dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s);
+
+	writel(driver_data->reg_values[PLL_TIMER],
+			dsi->reg_base + driver_data->plltmr_reg);
+
+	reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s);
+
+	if (driver_data->has_freqband) {
+		static const unsigned long freq_bands[] = {
+			100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
+			270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
+			510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
+			770 * MHZ, 870 * MHZ, 950 * MHZ,
+		};
+		int band;
+
+		for (band = 0; band < ARRAY_SIZE(freq_bands); ++band)
+			if (fout < freq_bands[band])
+				break;
+
+		dev_dbg(dsi->dev, "band %d\n", band);
+
+		reg |= DSIM_FREQ_BAND(band);
+	}
+
+	samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg);
+
+	timeout = 1000;
+	do {
+		if (timeout-- == 0) {
+			dev_err(dsi->dev, "PLL failed to stabilize\n");
+			return 0;
+		}
+		reg = samsung_dsim_read(dsi, DSIM_STATUS_REG);
+	} while ((reg & DSIM_PLL_STABLE) == 0);
+
+	return fout;
+}
+
+static int samsung_dsim_enable_clock(struct samsung_dsim *dsi)
+{
+	unsigned long hs_clk, byte_clk, esc_clk;
+	unsigned long esc_div;
+	u32 reg;
+
+	hs_clk = samsung_dsim_set_pll(dsi, dsi->burst_clk_rate);
+	if (!hs_clk) {
+		dev_err(dsi->dev, "failed to configure DSI PLL\n");
+		return -EFAULT;
+	}
+
+	byte_clk = hs_clk / 8;
+	esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate);
+	esc_clk = byte_clk / esc_div;
+
+	if (esc_clk > 20 * MHZ) {
+		++esc_div;
+		esc_clk = byte_clk / esc_div;
+	}
+
+	dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n",
+		hs_clk, byte_clk, esc_clk);
+
+	reg = samsung_dsim_read(dsi, DSIM_CLKCTRL_REG);
+	reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK
+			| DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS
+			| DSIM_BYTE_CLK_SRC_MASK);
+	reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN
+			| DSIM_ESC_PRESCALER(esc_div)
+			| DSIM_LANE_ESC_CLK_EN_CLK
+			| DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1)
+			| DSIM_BYTE_CLK_SRC(0)
+			| DSIM_TX_REQUEST_HSCLK;
+	samsung_dsim_write(dsi, DSIM_CLKCTRL_REG, reg);
+
+	return 0;
+}
+
+static void samsung_dsim_set_phy_ctrl(struct samsung_dsim *dsi)
+{
+	const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
+	const unsigned int *reg_values = driver_data->reg_values;
+	u32 reg;
+
+	if (driver_data->has_freqband)
+		return;
+
+	/* B D-PHY: D-PHY Master & Slave Analog Block control */
+	reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] |
+		reg_values[PHYCTRL_SLEW_UP];
+	samsung_dsim_write(dsi, DSIM_PHYCTRL_REG, reg);
+
+	/*
+	 * T LPX: Transmitted length of any Low-Power state period
+	 * T HS-EXIT: Time that the transmitter drives LP-11 following a HS
+	 *	burst
+	 */
+	reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT];
+	samsung_dsim_write(dsi, DSIM_PHYTIMING_REG, reg);
+
+	/*
+	 * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00
+	 *	Line state immediately before the HS-0 Line state starting the
+	 *	HS transmission
+	 * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to
+	 *	transmitting the Clock.
+	 * T CLK_POST: Time that the transmitter continues to send HS clock
+	 *	after the last associated Data Lane has transitioned to LP Mode
+	 *	Interval is defined as the period from the end of T HS-TRAIL to
+	 *	the beginning of T CLK-TRAIL
+	 * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after
+	 *	the last payload clock bit of a HS transmission burst
+	 */
+	reg = reg_values[PHYTIMING_CLK_PREPARE] |
+		reg_values[PHYTIMING_CLK_ZERO] |
+		reg_values[PHYTIMING_CLK_POST] |
+		reg_values[PHYTIMING_CLK_TRAIL];
+
+	samsung_dsim_write(dsi, DSIM_PHYTIMING1_REG, reg);
+
+	/*
+	 * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00
+	 *	Line state immediately before the HS-0 Line state starting the
+	 *	HS transmission
+	 * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to
+	 *	transmitting the Sync sequence.
+	 * T HS-TRAIL: Time that the transmitter drives the flipped differential
+	 *	state after last payload data bit of a HS transmission burst
+	 */
+	reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] |
+		reg_values[PHYTIMING_HS_TRAIL];
+	samsung_dsim_write(dsi, DSIM_PHYTIMING2_REG, reg);
+}
+
+static void samsung_dsim_disable_clock(struct samsung_dsim *dsi)
+{
+	u32 reg;
+
+	reg = samsung_dsim_read(dsi, DSIM_CLKCTRL_REG);
+	reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK
+			| DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN);
+	samsung_dsim_write(dsi, DSIM_CLKCTRL_REG, reg);
+
+	reg = samsung_dsim_read(dsi, DSIM_PLLCTRL_REG);
+	reg &= ~DSIM_PLL_EN;
+	samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg);
+}
+
+static void samsung_dsim_enable_lane(struct samsung_dsim *dsi, u32 lane)
+{
+	u32 reg = samsung_dsim_read(dsi, DSIM_CONFIG_REG);
+
+	reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK |
+			DSIM_LANE_EN(lane));
+	samsung_dsim_write(dsi, DSIM_CONFIG_REG, reg);
+}
+
+static int samsung_dsim_init_link(struct samsung_dsim *dsi)
+{
+	const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
+	int timeout;
+	u32 reg;
+	u32 lanes_mask;
+
+	/* Initialize FIFO pointers */
+	reg = samsung_dsim_read(dsi, DSIM_FIFOCTRL_REG);
+	reg &= ~0x1f;
+	samsung_dsim_write(dsi, DSIM_FIFOCTRL_REG, reg);
+
+	usleep_range(9000, 11000);
+
+	reg |= 0x1f;
+	samsung_dsim_write(dsi, DSIM_FIFOCTRL_REG, reg);
+	usleep_range(9000, 11000);
+
+	/* DSI configuration */
+	reg = 0;
+
+	/*
+	 * The first bit of mode_flags specifies display configuration.
+	 * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video
+	 * mode, otherwise it will support command mode.
+	 */
+	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
+		reg |= DSIM_VIDEO_MODE;
+
+		/*
+		 * The user manual describes that following bits are ignored in
+		 * command mode.
+		 */
+		if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
+			reg |= DSIM_MFLUSH_VS;
+		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
+			reg |= DSIM_SYNC_INFORM;
+		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
+			reg |= DSIM_BURST_MODE;
+		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT)
+			reg |= DSIM_AUTO_MODE;
+		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE)
+			reg |= DSIM_HSE_MODE;
+		if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP))
+			reg |= DSIM_HFP_MODE;
+		if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP))
+			reg |= DSIM_HBP_MODE;
+		if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HSA))
+			reg |= DSIM_HSA_MODE;
+	}
+
+	if (!(dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET))
+		reg |= DSIM_EOT_DISABLE;
+
+	switch (dsi->format) {
+	case MIPI_DSI_FMT_RGB888:
+		reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
+		break;
+	case MIPI_DSI_FMT_RGB666:
+		reg |= DSIM_MAIN_PIX_FORMAT_RGB666;
+		break;
+	case MIPI_DSI_FMT_RGB666_PACKED:
+		reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P;
+		break;
+	case MIPI_DSI_FMT_RGB565:
+		reg |= DSIM_MAIN_PIX_FORMAT_RGB565;
+		break;
+	default:
+		dev_err(dsi->dev, "invalid pixel format\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Use non-continuous clock mode if the periparal wants and
+	 * host controller supports
+	 *
+	 * In non-continous clock mode, host controller will turn off
+	 * the HS clock between high-speed transmissions to reduce
+	 * power consumption.
+	 */
+	if (driver_data->has_clklane_stop &&
+			dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
+		reg |= DSIM_CLKLANE_STOP;
+	}
+	samsung_dsim_write(dsi, DSIM_CONFIG_REG, reg);
+
+	lanes_mask = BIT(dsi->lanes) - 1;
+	samsung_dsim_enable_lane(dsi, lanes_mask);
+
+	/* Check clock and data lane state are stop state */
+	timeout = 100;
+	do {
+		if (timeout-- == 0) {
+			dev_err(dsi->dev, "waiting for bus lanes timed out\n");
+			return -EFAULT;
+		}
+
+		reg = samsung_dsim_read(dsi, DSIM_STATUS_REG);
+		if ((reg & DSIM_STOP_STATE_DAT(lanes_mask))
+		    != DSIM_STOP_STATE_DAT(lanes_mask))
+			continue;
+	} while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK)));
+
+	reg = samsung_dsim_read(dsi, DSIM_ESCMODE_REG);
+	reg &= ~DSIM_STOP_STATE_CNT_MASK;
+	reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]);
+	samsung_dsim_write(dsi, DSIM_ESCMODE_REG, reg);
+
+	reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff);
+	samsung_dsim_write(dsi, DSIM_TIMEOUT_REG, reg);
+
+	return 0;
+}
+
+static void samsung_dsim_set_display_mode(struct samsung_dsim *dsi)
+{
+	struct drm_display_mode *m = &dsi->mode;
+	unsigned int num_bits_resol = dsi->driver_data->num_bits_resol;
+	u32 reg;
+
+	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
+		reg = DSIM_CMD_ALLOW(0xf)
+			| DSIM_STABLE_VFP(m->vsync_start - m->vdisplay)
+			| DSIM_MAIN_VBP(m->vtotal - m->vsync_end);
+		samsung_dsim_write(dsi, DSIM_MVPORCH_REG, reg);
+
+		reg = DSIM_MAIN_HFP(m->hsync_start - m->hdisplay)
+			| DSIM_MAIN_HBP(m->htotal - m->hsync_end);
+		samsung_dsim_write(dsi, DSIM_MHPORCH_REG, reg);
+
+		reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start)
+			| DSIM_MAIN_HSA(m->hsync_end - m->hsync_start);
+		samsung_dsim_write(dsi, DSIM_MSYNC_REG, reg);
+	}
+	reg =  DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) |
+		DSIM_MAIN_VRESOL(m->vdisplay, num_bits_resol);
+
+	samsung_dsim_write(dsi, DSIM_MDRESOL_REG, reg);
+
+	dev_dbg(dsi->dev, "LCD size = %dx%d\n", m->hdisplay, m->vdisplay);
+}
+
+static void samsung_dsim_set_display_enable(struct samsung_dsim *dsi, bool enable)
+{
+	u32 reg;
+
+	reg = samsung_dsim_read(dsi, DSIM_MDRESOL_REG);
+	if (enable)
+		reg |= DSIM_MAIN_STAND_BY;
+	else
+		reg &= ~DSIM_MAIN_STAND_BY;
+	samsung_dsim_write(dsi, DSIM_MDRESOL_REG, reg);
+}
+
+static int samsung_dsim_wait_for_hdr_fifo(struct samsung_dsim *dsi)
+{
+	int timeout = 2000;
+
+	do {
+		u32 reg = samsung_dsim_read(dsi, DSIM_FIFOCTRL_REG);
+
+		if (!(reg & DSIM_SFR_HEADER_FULL))
+			return 0;
+
+		if (!cond_resched())
+			usleep_range(950, 1050);
+	} while (--timeout);
+
+	return -ETIMEDOUT;
+}
+
+static void samsung_dsim_set_cmd_lpm(struct samsung_dsim *dsi, bool lpm)
+{
+	u32 v = samsung_dsim_read(dsi, DSIM_ESCMODE_REG);
+
+	if (lpm)
+		v |= DSIM_CMD_LPDT_LP;
+	else
+		v &= ~DSIM_CMD_LPDT_LP;
+
+	samsung_dsim_write(dsi, DSIM_ESCMODE_REG, v);
+}
+
+static void samsung_dsim_force_bta(struct samsung_dsim *dsi)
+{
+	u32 v = samsung_dsim_read(dsi, DSIM_ESCMODE_REG);
+
+	v |= DSIM_FORCE_BTA;
+	samsung_dsim_write(dsi, DSIM_ESCMODE_REG, v);
+}
+
+static void samsung_dsim_send_to_fifo(struct samsung_dsim *dsi,
+				      struct samsung_dsim_transfer *xfer)
+{
+	struct device *dev = dsi->dev;
+	struct mipi_dsi_packet *pkt = &xfer->packet;
+	const u8 *payload = pkt->payload + xfer->tx_done;
+	u16 length = pkt->payload_length - xfer->tx_done;
+	bool first = !xfer->tx_done;
+	u32 reg;
+
+	dev_dbg(dev, "< xfer %pK: tx len %u, done %u, rx len %u, done %u\n",
+		xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done);
+
+	if (length > DSI_TX_FIFO_SIZE)
+		length = DSI_TX_FIFO_SIZE;
+
+	xfer->tx_done += length;
+
+	/* Send payload */
+	while (length >= 4) {
+		reg = get_unaligned_le32(payload);
+		samsung_dsim_write(dsi, DSIM_PAYLOAD_REG, reg);
+		payload += 4;
+		length -= 4;
+	}
+
+	reg = 0;
+	switch (length) {
+	case 3:
+		reg |= payload[2] << 16;
+		fallthrough;
+	case 2:
+		reg |= payload[1] << 8;
+		fallthrough;
+	case 1:
+		reg |= payload[0];
+		samsung_dsim_write(dsi, DSIM_PAYLOAD_REG, reg);
+		break;
+	}
+
+	/* Send packet header */
+	if (!first)
+		return;
+
+	reg = get_unaligned_le32(pkt->header);
+	if (samsung_dsim_wait_for_hdr_fifo(dsi)) {
+		dev_err(dev, "waiting for header FIFO timed out\n");
+		return;
+	}
+
+	if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM,
+		 dsi->state & DSIM_STATE_CMD_LPM)) {
+		samsung_dsim_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM);
+		dsi->state ^= DSIM_STATE_CMD_LPM;
+	}
+
+	samsung_dsim_write(dsi, DSIM_PKTHDR_REG, reg);
+
+	if (xfer->flags & MIPI_DSI_MSG_REQ_ACK)
+		samsung_dsim_force_bta(dsi);
+}
+
+static void samsung_dsim_read_from_fifo(struct samsung_dsim *dsi,
+					struct samsung_dsim_transfer *xfer)
+{
+	u8 *payload = xfer->rx_payload + xfer->rx_done;
+	bool first = !xfer->rx_done;
+	struct device *dev = dsi->dev;
+	u16 length;
+	u32 reg;
+
+	if (first) {
+		reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG);
+
+		switch (reg & 0x3f) {
+		case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
+		case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
+			if (xfer->rx_len >= 2) {
+				payload[1] = reg >> 16;
+				++xfer->rx_done;
+			}
+			fallthrough;
+		case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
+		case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
+			payload[0] = reg >> 8;
+			++xfer->rx_done;
+			xfer->rx_len = xfer->rx_done;
+			xfer->result = 0;
+			goto clear_fifo;
+		case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
+			dev_err(dev, "DSI Error Report: 0x%04x\n", (reg >> 8) & 0xffff);
+			xfer->result = 0;
+			goto clear_fifo;
+		}
+
+		length = (reg >> 8) & 0xffff;
+		if (length > xfer->rx_len) {
+			dev_err(dev,
+				"response too long (%u > %u bytes), stripping\n",
+				xfer->rx_len, length);
+			length = xfer->rx_len;
+		} else if (length < xfer->rx_len)
+			xfer->rx_len = length;
+	}
+
+	length = xfer->rx_len - xfer->rx_done;
+	xfer->rx_done += length;
+
+	/* Receive payload */
+	while (length >= 4) {
+		reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG);
+		payload[0] = (reg >>  0) & 0xff;
+		payload[1] = (reg >>  8) & 0xff;
+		payload[2] = (reg >> 16) & 0xff;
+		payload[3] = (reg >> 24) & 0xff;
+		payload += 4;
+		length -= 4;
+	}
+
+	if (length) {
+		reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG);
+		switch (length) {
+		case 3:
+			payload[2] = (reg >> 16) & 0xff;
+			fallthrough;
+		case 2:
+			payload[1] = (reg >> 8) & 0xff;
+			fallthrough;
+		case 1:
+			payload[0] = reg & 0xff;
+		}
+	}
+
+	if (xfer->rx_done == xfer->rx_len)
+		xfer->result = 0;
+
+clear_fifo:
+	length = DSI_RX_FIFO_SIZE / 4;
+	do {
+		reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG);
+		if (reg == DSI_RX_FIFO_EMPTY)
+			break;
+	} while (--length);
+}
+
+static void samsung_dsim_transfer_start(struct samsung_dsim *dsi)
+{
+	unsigned long flags;
+	struct samsung_dsim_transfer *xfer;
+	bool start = false;
+
+again:
+	spin_lock_irqsave(&dsi->transfer_lock, flags);
+
+	if (list_empty(&dsi->transfer_list)) {
+		spin_unlock_irqrestore(&dsi->transfer_lock, flags);
+		return;
+	}
+
+	xfer = list_first_entry(&dsi->transfer_list,
+				struct samsung_dsim_transfer, list);
+
+	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
+
+	if (xfer->packet.payload_length &&
+	    xfer->tx_done == xfer->packet.payload_length)
+		/* waiting for RX */
+		return;
+
+	samsung_dsim_send_to_fifo(dsi, xfer);
+
+	if (xfer->packet.payload_length || xfer->rx_len)
+		return;
+
+	xfer->result = 0;
+	complete(&xfer->completed);
+
+	spin_lock_irqsave(&dsi->transfer_lock, flags);
+
+	list_del_init(&xfer->list);
+	start = !list_empty(&dsi->transfer_list);
+
+	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
+
+	if (start)
+		goto again;
+}
+
+static bool samsung_dsim_transfer_finish(struct samsung_dsim *dsi)
+{
+	struct samsung_dsim_transfer *xfer;
+	unsigned long flags;
+	bool start = true;
+
+	spin_lock_irqsave(&dsi->transfer_lock, flags);
+
+	if (list_empty(&dsi->transfer_list)) {
+		spin_unlock_irqrestore(&dsi->transfer_lock, flags);
+		return false;
+	}
+
+	xfer = list_first_entry(&dsi->transfer_list,
+				struct samsung_dsim_transfer, list);
+
+	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
+
+	dev_dbg(dsi->dev,
+		"> xfer %pK, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n",
+		xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len,
+		xfer->rx_done);
+
+	if (xfer->tx_done != xfer->packet.payload_length)
+		return true;
+
+	if (xfer->rx_done != xfer->rx_len)
+		samsung_dsim_read_from_fifo(dsi, xfer);
+
+	if (xfer->rx_done != xfer->rx_len)
+		return true;
+
+	spin_lock_irqsave(&dsi->transfer_lock, flags);
+
+	list_del_init(&xfer->list);
+	start = !list_empty(&dsi->transfer_list);
+
+	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
+
+	if (!xfer->rx_len)
+		xfer->result = 0;
+	complete(&xfer->completed);
+
+	return start;
+}
+
+static void samsung_dsim_remove_transfer(struct samsung_dsim *dsi,
+					 struct samsung_dsim_transfer *xfer)
+{
+	unsigned long flags;
+	bool start;
+
+	spin_lock_irqsave(&dsi->transfer_lock, flags);
+
+	if (!list_empty(&dsi->transfer_list) &&
+	    xfer == list_first_entry(&dsi->transfer_list,
+				     struct samsung_dsim_transfer, list)) {
+		list_del_init(&xfer->list);
+		start = !list_empty(&dsi->transfer_list);
+		spin_unlock_irqrestore(&dsi->transfer_lock, flags);
+		if (start)
+			samsung_dsim_transfer_start(dsi);
+		return;
+	}
+
+	list_del_init(&xfer->list);
+
+	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
+}
+
+static int samsung_dsim_transfer(struct samsung_dsim *dsi,
+				 struct samsung_dsim_transfer *xfer)
+{
+	unsigned long flags;
+	bool stopped;
+
+	xfer->tx_done = 0;
+	xfer->rx_done = 0;
+	xfer->result = -ETIMEDOUT;
+	init_completion(&xfer->completed);
+
+	spin_lock_irqsave(&dsi->transfer_lock, flags);
+
+	stopped = list_empty(&dsi->transfer_list);
+	list_add_tail(&xfer->list, &dsi->transfer_list);
+
+	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
+
+	if (stopped)
+		samsung_dsim_transfer_start(dsi);
+
+	wait_for_completion_timeout(&xfer->completed,
+				    msecs_to_jiffies(DSI_XFER_TIMEOUT_MS));
+	if (xfer->result == -ETIMEDOUT) {
+		struct mipi_dsi_packet *pkt = &xfer->packet;
+
+		samsung_dsim_remove_transfer(dsi, xfer);
+		dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 4, pkt->header,
+			(int)pkt->payload_length, pkt->payload);
+		return -ETIMEDOUT;
+	}
+
+	/* Also covers hardware timeout condition */
+	return xfer->result;
+}
+
+static irqreturn_t samsung_dsim_irq(int irq, void *dev_id)
+{
+	struct samsung_dsim *dsi = dev_id;
+	u32 status;
+
+	status = samsung_dsim_read(dsi, DSIM_INTSRC_REG);
+	if (!status) {
+		static unsigned long j;
+
+		if (printk_timed_ratelimit(&j, 500))
+			dev_warn(dsi->dev, "spurious interrupt\n");
+		return IRQ_HANDLED;
+	}
+	samsung_dsim_write(dsi, DSIM_INTSRC_REG, status);
+
+	if (status & DSIM_INT_SW_RST_RELEASE) {
+		u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |
+			DSIM_INT_SFR_HDR_FIFO_EMPTY | DSIM_INT_RX_ECC_ERR |
+			DSIM_INT_SW_RST_RELEASE);
+		samsung_dsim_write(dsi, DSIM_INTMSK_REG, mask);
+		complete(&dsi->completed);
+		return IRQ_HANDLED;
+	}
+
+	if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |
+			DSIM_INT_PLL_STABLE)))
+		return IRQ_HANDLED;
+
+	if (samsung_dsim_transfer_finish(dsi))
+		samsung_dsim_transfer_start(dsi);
+
+	return IRQ_HANDLED;
+}
+
+static void samsung_dsim_enable_irq(struct samsung_dsim *dsi)
+{
+	const struct samsung_dsim_plat_data *pdata = dsi->plat_data;
+
+	enable_irq(dsi->irq);
+
+	if (pdata && pdata->irq_ops && pdata->irq_ops->enable)
+		pdata->irq_ops->enable(dsi);
+}
+
+static void samsung_dsim_disable_irq(struct samsung_dsim *dsi)
+{
+	const struct samsung_dsim_plat_data *pdata = dsi->plat_data;
+
+	if (pdata && pdata->irq_ops && pdata->irq_ops->disable)
+		pdata->irq_ops->disable(dsi);
+
+	disable_irq(dsi->irq);
+}
+
+static int samsung_dsim_init(struct samsung_dsim *dsi)
+{
+	const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
+
+	samsung_dsim_reset(dsi);
+	samsung_dsim_enable_irq(dsi);
+
+	if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST)
+		samsung_dsim_enable_lane(dsi, BIT(dsi->lanes) - 1);
+
+	samsung_dsim_enable_clock(dsi);
+	if (driver_data->wait_for_reset)
+		samsung_dsim_wait_for_reset(dsi);
+	samsung_dsim_set_phy_ctrl(dsi);
+	samsung_dsim_init_link(dsi);
+
+	return 0;
+}
+
+static void samsung_dsim_atomic_pre_enable(struct drm_bridge *bridge,
+					   struct drm_bridge_state *old_bridge_state)
+{
+	struct samsung_dsim *dsi = bridge_to_dsi(bridge);
+	int ret;
+
+	if (dsi->state & DSIM_STATE_ENABLED)
+		return;
+
+	ret = pm_runtime_resume_and_get(dsi->dev);
+	if (ret < 0) {
+		dev_err(dsi->dev, "failed to enable DSI device.\n");
+		return;
+	}
+
+	dsi->state |= DSIM_STATE_ENABLED;
+}
+
+static void samsung_dsim_atomic_enable(struct drm_bridge *bridge,
+				       struct drm_bridge_state *old_bridge_state)
+{
+	struct samsung_dsim *dsi = bridge_to_dsi(bridge);
+
+	samsung_dsim_set_display_mode(dsi);
+	samsung_dsim_set_display_enable(dsi, true);
+
+	dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE;
+}
+
+static void samsung_dsim_atomic_disable(struct drm_bridge *bridge,
+					struct drm_bridge_state *old_bridge_state)
+{
+	struct samsung_dsim *dsi = bridge_to_dsi(bridge);
+
+	if (!(dsi->state & DSIM_STATE_ENABLED))
+		return;
+
+	dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE;
+}
+
+static void samsung_dsim_atomic_post_disable(struct drm_bridge *bridge,
+					     struct drm_bridge_state *old_bridge_state)
+{
+	struct samsung_dsim *dsi = bridge_to_dsi(bridge);
+
+	samsung_dsim_set_display_enable(dsi, false);
+
+	dsi->state &= ~DSIM_STATE_ENABLED;
+	pm_runtime_put_sync(dsi->dev);
+}
+
+static void samsung_dsim_mode_set(struct drm_bridge *bridge,
+				  const struct drm_display_mode *mode,
+				  const struct drm_display_mode *adjusted_mode)
+{
+	struct samsung_dsim *dsi = bridge_to_dsi(bridge);
+
+	drm_mode_copy(&dsi->mode, adjusted_mode);
+}
+
+static int samsung_dsim_attach(struct drm_bridge *bridge,
+			       enum drm_bridge_attach_flags flags)
+{
+	struct samsung_dsim *dsi = bridge_to_dsi(bridge);
+
+	return drm_bridge_attach(bridge->encoder, dsi->out_bridge, NULL, flags);
+}
+
+static const struct drm_bridge_funcs samsung_dsim_bridge_funcs = {
+	.atomic_duplicate_state		= drm_atomic_helper_bridge_duplicate_state,
+	.atomic_destroy_state		= drm_atomic_helper_bridge_destroy_state,
+	.atomic_reset			= drm_atomic_helper_bridge_reset,
+	.atomic_pre_enable		= samsung_dsim_atomic_pre_enable,
+	.atomic_enable			= samsung_dsim_atomic_enable,
+	.atomic_disable			= samsung_dsim_atomic_disable,
+	.atomic_post_disable		= samsung_dsim_atomic_post_disable,
+	.mode_set			= samsung_dsim_mode_set,
+	.attach				= samsung_dsim_attach,
+};
+
+MODULE_DEVICE_TABLE(of, samsung_dsim_of_match);
+
+static int samsung_dsim_host_attach(struct mipi_dsi_host *host,
+				    struct mipi_dsi_device *device)
+{
+	struct samsung_dsim *dsi = host_to_dsi(host);
+	const struct samsung_dsim_plat_data *pdata = dsi->plat_data;
+	struct device *dev = dsi->dev;
+	int ret;
+
+	dsi->out_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0);
+	if (IS_ERR(dsi->out_bridge)) {
+		ret = PTR_ERR(dsi->out_bridge);
+		DRM_DEV_ERROR(dev, "failed to find the bridge: %d\n", ret);
+		return ret;
+	}
+
+	DRM_DEV_INFO(dev, "Attached %s device\n", device->name);
+
+	drm_bridge_add(&dsi->bridge);
+
+	if (pdata && pdata->host_ops && pdata->host_ops->attach) {
+		ret = pdata->host_ops->attach(dsi, device);
+		if (ret < 0)
+			return ret;
+	}
+
+	dsi->lanes = device->lanes;
+	dsi->format = device->format;
+	dsi->mode_flags = device->mode_flags;
+
+	return 0;
+}
+
+static int samsung_dsim_host_detach(struct mipi_dsi_host *host,
+				    struct mipi_dsi_device *device)
+{
+	struct samsung_dsim *dsi = host_to_dsi(host);
+	const struct samsung_dsim_plat_data *pdata = dsi->plat_data;
+	int ret;
+
+	if (dsi->out_bridge->funcs->detach)
+		dsi->out_bridge->funcs->detach(dsi->out_bridge);
+
+	if (pdata && pdata->host_ops && pdata->host_ops->detach) {
+		ret = pdata->host_ops->detach(dsi, device);
+		if (ret < 0)
+			return ret;
+	}
+
+	drm_bridge_remove(&dsi->bridge);
+
+	return 0;
+}
+
+static ssize_t samsung_dsim_host_transfer(struct mipi_dsi_host *host,
+					  const struct mipi_dsi_msg *msg)
+{
+	struct samsung_dsim *dsi = host_to_dsi(host);
+	struct samsung_dsim_transfer xfer;
+	int ret;
+
+	if (!(dsi->state & DSIM_STATE_ENABLED))
+		return -EINVAL;
+
+	if (!(dsi->state & DSIM_STATE_INITIALIZED)) {
+		ret = samsung_dsim_init(dsi);
+		if (ret)
+			return ret;
+		dsi->state |= DSIM_STATE_INITIALIZED;
+	}
+
+	ret = mipi_dsi_create_packet(&xfer.packet, msg);
+	if (ret < 0)
+		return ret;
+
+	xfer.rx_len = msg->rx_len;
+	xfer.rx_payload = msg->rx_buf;
+	xfer.flags = msg->flags;
+
+	ret = samsung_dsim_transfer(dsi, &xfer);
+	return (ret < 0) ? ret : xfer.rx_done;
+}
+
+static const struct mipi_dsi_host_ops samsung_dsim_ops = {
+	.attach = samsung_dsim_host_attach,
+	.detach = samsung_dsim_host_detach,
+	.transfer = samsung_dsim_host_transfer,
+};
+
+static int samsung_dsim_of_read_u32(const struct device_node *np,
+				    const char *propname, u32 *out_value)
+{
+	int ret = of_property_read_u32(np, propname, out_value);
+
+	if (ret < 0)
+		pr_err("%pOF: failed to get '%s' property\n", np, propname);
+
+	return ret;
+}
+
+static int samsung_dsim_parse_dt(struct samsung_dsim *dsi)
+{
+	struct device *dev = dsi->dev;
+	struct device_node *node = dev->of_node;
+	int ret;
+
+	ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency",
+				       &dsi->pll_clk_rate);
+	if (ret < 0)
+		return ret;
+
+	ret = samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency",
+				       &dsi->burst_clk_rate);
+	if (ret < 0)
+		return ret;
+
+	ret = samsung_dsim_of_read_u32(node, "samsung,esc-clock-frequency",
+				       &dsi->esc_clk_rate);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+__weak const struct samsung_dsim_plat_data *
+samsung_dsim_plat_probe(struct samsung_dsim *priv)
+{
+	return NULL;
+}
+
+__weak void samsung_dsim_plat_remove(struct samsung_dsim *priv)
+{
+}
+
+static int samsung_dsim_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct samsung_dsim *dsi;
+	int ret, i;
+
+	dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
+	if (!dsi)
+		return -ENOMEM;
+
+	init_completion(&dsi->completed);
+	spin_lock_init(&dsi->transfer_lock);
+	INIT_LIST_HEAD(&dsi->transfer_list);
+
+	dsi->dsi_host.ops = &samsung_dsim_ops;
+	dsi->dsi_host.dev = dev;
+
+	dsi->dev = dev;
+	dsi->driver_data = of_device_get_match_data(dev);
+
+	dsi->supplies[0].supply = "vddcore";
+	dsi->supplies[1].supply = "vddio";
+	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies),
+				      dsi->supplies);
+	if (ret)
+		return dev_err_probe(dev, ret, "failed to get regulators\n");
+
+	dsi->clks = devm_kcalloc(dev, dsi->driver_data->num_clks,
+				 sizeof(*dsi->clks), GFP_KERNEL);
+	if (!dsi->clks)
+		return -ENOMEM;
+
+	for (i = 0; i < dsi->driver_data->num_clks; i++) {
+		dsi->clks[i] = devm_clk_get(dev, clk_names[i]);
+		if (IS_ERR(dsi->clks[i])) {
+			if (strcmp(clk_names[i], "sclk_mipi") == 0) {
+				dsi->clks[i] = devm_clk_get(dev, OLD_SCLK_MIPI_CLK_NAME);
+				if (!IS_ERR(dsi->clks[i]))
+					continue;
+			}
+
+			dev_info(dev, "failed to get the clock: %s\n", clk_names[i]);
+			return PTR_ERR(dsi->clks[i]);
+		}
+	}
+
+	dsi->reg_base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(dsi->reg_base))
+		return PTR_ERR(dsi->reg_base);
+
+	dsi->phy = devm_phy_get(dev, "dsim");
+	if (IS_ERR(dsi->phy)) {
+		dev_info(dev, "failed to get dsim phy\n");
+		return PTR_ERR(dsi->phy);
+	}
+
+	dsi->irq = platform_get_irq(pdev, 0);
+	if (dsi->irq < 0)
+		return dsi->irq;
+
+	ret = devm_request_threaded_irq(dev, dsi->irq, NULL,
+					samsung_dsim_irq,
+					IRQF_ONESHOT | IRQF_NO_AUTOEN,
+					dev_name(dev), dsi);
+	if (ret) {
+		dev_err(dev, "failed to request dsi irq\n");
+		return ret;
+	}
+
+	ret = samsung_dsim_parse_dt(dsi);
+	if (ret)
+		return ret;
+
+	platform_set_drvdata(pdev, dsi);
+
+	pm_runtime_enable(dev);
+
+	dsi->bridge.funcs = &samsung_dsim_bridge_funcs;
+	dsi->bridge.of_node = dev->of_node;
+	dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
+
+	dsi->plat_data = samsung_dsim_plat_probe(dsi);
+	if (IS_ERR(dsi->plat_data)) {
+		ret = PTR_ERR(dsi->plat_data);
+		goto err_disable_runtime;
+	}
+
+	return 0;
+
+err_disable_runtime:
+	pm_runtime_disable(dev);
+
+	return ret;
+}
+
+static int samsung_dsim_remove(struct platform_device *pdev)
+{
+	struct samsung_dsim *dsi = platform_get_drvdata(pdev);
+
+	pm_runtime_disable(&pdev->dev);
+
+	samsung_dsim_plat_remove(dsi);
+
+	return 0;
+}
+
+static int __maybe_unused samsung_dsim_suspend(struct device *dev)
+{
+	struct samsung_dsim *dsi = dev_get_drvdata(dev);
+	const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
+	int ret, i;
+
+	usleep_range(10000, 20000);
+
+	if (dsi->state & DSIM_STATE_INITIALIZED) {
+		dsi->state &= ~DSIM_STATE_INITIALIZED;
+
+		samsung_dsim_disable_clock(dsi);
+
+		samsung_dsim_disable_irq(dsi);
+	}
+
+	dsi->state &= ~DSIM_STATE_CMD_LPM;
+
+	phy_power_off(dsi->phy);
+
+	for (i = driver_data->num_clks - 1; i > -1; i--)
+		clk_disable_unprepare(dsi->clks[i]);
+
+	ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
+	if (ret < 0)
+		dev_err(dsi->dev, "cannot disable regulators %d\n", ret);
+
+	return 0;
+}
+
+static int __maybe_unused samsung_dsim_resume(struct device *dev)
+{
+	struct samsung_dsim *dsi = dev_get_drvdata(dev);
+	const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
+	int ret, i;
+
+	ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
+	if (ret < 0) {
+		dev_err(dsi->dev, "cannot enable regulators %d\n", ret);
+		return ret;
+	}
+
+	for (i = 0; i < driver_data->num_clks; i++) {
+		ret = clk_prepare_enable(dsi->clks[i]);
+		if (ret < 0)
+			goto err_clk;
+	}
+
+	ret = phy_power_on(dsi->phy);
+	if (ret < 0) {
+		dev_err(dsi->dev, "cannot enable phy %d\n", ret);
+		goto err_clk;
+	}
+
+	return 0;
+
+err_clk:
+	while (--i > -1)
+		clk_disable_unprepare(dsi->clks[i]);
+	regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
+
+	return ret;
+}
+
+static const struct dev_pm_ops samsung_dsim_pm_ops = {
+	SET_RUNTIME_PM_OPS(samsung_dsim_suspend, samsung_dsim_resume, NULL)
+	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+				pm_runtime_force_resume)
+};
+
+struct platform_driver dsi_driver = {
+	.probe = samsung_dsim_probe,
+	.remove = samsung_dsim_remove,
+	.driver = {
+		   .name = "samsung-dsim",
+		   .owner = THIS_MODULE,
+		   .pm = &samsung_dsim_pm_ops,
+		   .of_match_table = samsung_dsim_of_match,
+	},
+};
+
+MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>");
+MODULE_DESCRIPTION("Samsung MIPI DSIM controller bridge");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
index f27cfd2a9726..784d379e3dd2 100644
--- a/drivers/gpu/drm/exynos/Kconfig
+++ b/drivers/gpu/drm/exynos/Kconfig
@@ -58,6 +58,7 @@ config DRM_EXYNOS_DSI
 	depends on DRM_EXYNOS_FIMD || DRM_EXYNOS5433_DECON || DRM_EXYNOS7_DECON
 	select DRM_MIPI_DSI
 	select DRM_PANEL
+	select DRM_SAMSUNG_DSIM
 	default n
 	help
 	  This enables support for Exynos MIPI-DSI device.
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 5fe262f31065..97167c5ffc78 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -1,1338 +1,72 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Samsung SoC MIPI DSI Master driver.
+ * Samsung MIPI DSIM glue for Exynos SoCs.
  *
  * Copyright (c) 2014 Samsung Electronics Co., Ltd
  *
  * Contacts: Tomasz Figa <t.figa@samsung.com>
-*/
+ */
 
-#include <linux/clk.h>
-#include <linux/delay.h>
 #include <linux/component.h>
-#include <linux/gpio/consumer.h>
-#include <linux/irq.h>
-#include <linux/of_device.h>
-#include <linux/of_graph.h>
-#include <linux/phy/phy.h>
-#include <linux/regulator/consumer.h>
 
-#include <asm/unaligned.h>
-
-#include <video/mipi_display.h>
-#include <video/videomode.h>
-
-#include <drm/drm_atomic_helper.h>
-#include <drm/drm_bridge.h>
-#include <drm/drm_mipi_dsi.h>
-#include <drm/drm_print.h>
+#include <drm/bridge/samsung-dsim.h>
 #include <drm/drm_probe_helper.h>
 #include <drm/drm_simple_kms_helper.h>
 
 #include "exynos_drm_crtc.h"
 #include "exynos_drm_drv.h"
 
-/* returns true iff both arguments logically differs */
-#define NEQV(a, b) (!(a) ^ !(b))
-
-/* DSIM_STATUS */
-#define DSIM_STOP_STATE_DAT(x)		(((x) & 0xf) << 0)
-#define DSIM_STOP_STATE_CLK		(1 << 8)
-#define DSIM_TX_READY_HS_CLK		(1 << 10)
-#define DSIM_PLL_STABLE			(1 << 31)
-
-/* DSIM_SWRST */
-#define DSIM_FUNCRST			(1 << 16)
-#define DSIM_SWRST			(1 << 0)
-
-/* DSIM_TIMEOUT */
-#define DSIM_LPDR_TIMEOUT(x)		((x) << 0)
-#define DSIM_BTA_TIMEOUT(x)		((x) << 16)
-
-/* DSIM_CLKCTRL */
-#define DSIM_ESC_PRESCALER(x)		(((x) & 0xffff) << 0)
-#define DSIM_ESC_PRESCALER_MASK		(0xffff << 0)
-#define DSIM_LANE_ESC_CLK_EN_CLK	(1 << 19)
-#define DSIM_LANE_ESC_CLK_EN_DATA(x)	(((x) & 0xf) << 20)
-#define DSIM_LANE_ESC_CLK_EN_DATA_MASK	(0xf << 20)
-#define DSIM_BYTE_CLKEN			(1 << 24)
-#define DSIM_BYTE_CLK_SRC(x)		(((x) & 0x3) << 25)
-#define DSIM_BYTE_CLK_SRC_MASK		(0x3 << 25)
-#define DSIM_PLL_BYPASS			(1 << 27)
-#define DSIM_ESC_CLKEN			(1 << 28)
-#define DSIM_TX_REQUEST_HSCLK		(1 << 31)
-
-/* DSIM_CONFIG */
-#define DSIM_LANE_EN_CLK		(1 << 0)
-#define DSIM_LANE_EN(x)			(((x) & 0xf) << 1)
-#define DSIM_NUM_OF_DATA_LANE(x)	(((x) & 0x3) << 5)
-#define DSIM_SUB_PIX_FORMAT(x)		(((x) & 0x7) << 8)
-#define DSIM_MAIN_PIX_FORMAT_MASK	(0x7 << 12)
-#define DSIM_MAIN_PIX_FORMAT_RGB888	(0x7 << 12)
-#define DSIM_MAIN_PIX_FORMAT_RGB666	(0x6 << 12)
-#define DSIM_MAIN_PIX_FORMAT_RGB666_P	(0x5 << 12)
-#define DSIM_MAIN_PIX_FORMAT_RGB565	(0x4 << 12)
-#define DSIM_SUB_VC			(((x) & 0x3) << 16)
-#define DSIM_MAIN_VC			(((x) & 0x3) << 18)
-#define DSIM_HSA_MODE			(1 << 20)
-#define DSIM_HBP_MODE			(1 << 21)
-#define DSIM_HFP_MODE			(1 << 22)
-#define DSIM_HSE_MODE			(1 << 23)
-#define DSIM_AUTO_MODE			(1 << 24)
-#define DSIM_VIDEO_MODE			(1 << 25)
-#define DSIM_BURST_MODE			(1 << 26)
-#define DSIM_SYNC_INFORM		(1 << 27)
-#define DSIM_EOT_DISABLE		(1 << 28)
-#define DSIM_MFLUSH_VS			(1 << 29)
-/* This flag is valid only for exynos3250/3472/5260/5430 */
-#define DSIM_CLKLANE_STOP		(1 << 30)
-
-/* DSIM_ESCMODE */
-#define DSIM_TX_TRIGGER_RST		(1 << 4)
-#define DSIM_TX_LPDT_LP			(1 << 6)
-#define DSIM_CMD_LPDT_LP		(1 << 7)
-#define DSIM_FORCE_BTA			(1 << 16)
-#define DSIM_FORCE_STOP_STATE		(1 << 20)
-#define DSIM_STOP_STATE_CNT(x)		(((x) & 0x7ff) << 21)
-#define DSIM_STOP_STATE_CNT_MASK	(0x7ff << 21)
-
-/* DSIM_MDRESOL */
-#define DSIM_MAIN_STAND_BY		(1 << 31)
-#define DSIM_MAIN_VRESOL(x, num_bits)	(((x) & ((1 << (num_bits)) - 1)) << 16)
-#define DSIM_MAIN_HRESOL(x, num_bits)	(((x) & ((1 << (num_bits)) - 1)) << 0)
-
-/* DSIM_MVPORCH */
-#define DSIM_CMD_ALLOW(x)		((x) << 28)
-#define DSIM_STABLE_VFP(x)		((x) << 16)
-#define DSIM_MAIN_VBP(x)		((x) << 0)
-#define DSIM_CMD_ALLOW_MASK		(0xf << 28)
-#define DSIM_STABLE_VFP_MASK		(0x7ff << 16)
-#define DSIM_MAIN_VBP_MASK		(0x7ff << 0)
-
-/* DSIM_MHPORCH */
-#define DSIM_MAIN_HFP(x)		((x) << 16)
-#define DSIM_MAIN_HBP(x)		((x) << 0)
-#define DSIM_MAIN_HFP_MASK		((0xffff) << 16)
-#define DSIM_MAIN_HBP_MASK		((0xffff) << 0)
-
-/* DSIM_MSYNC */
-#define DSIM_MAIN_VSA(x)		((x) << 22)
-#define DSIM_MAIN_HSA(x)		((x) << 0)
-#define DSIM_MAIN_VSA_MASK		((0x3ff) << 22)
-#define DSIM_MAIN_HSA_MASK		((0xffff) << 0)
-
-/* DSIM_SDRESOL */
-#define DSIM_SUB_STANDY(x)		((x) << 31)
-#define DSIM_SUB_VRESOL(x)		((x) << 16)
-#define DSIM_SUB_HRESOL(x)		((x) << 0)
-#define DSIM_SUB_STANDY_MASK		((0x1) << 31)
-#define DSIM_SUB_VRESOL_MASK		((0x7ff) << 16)
-#define DSIM_SUB_HRESOL_MASK		((0x7ff) << 0)
-
-/* DSIM_INTSRC */
-#define DSIM_INT_PLL_STABLE		(1 << 31)
-#define DSIM_INT_SW_RST_RELEASE		(1 << 30)
-#define DSIM_INT_SFR_FIFO_EMPTY		(1 << 29)
-#define DSIM_INT_SFR_HDR_FIFO_EMPTY	(1 << 28)
-#define DSIM_INT_BTA			(1 << 25)
-#define DSIM_INT_FRAME_DONE		(1 << 24)
-#define DSIM_INT_RX_TIMEOUT		(1 << 21)
-#define DSIM_INT_BTA_TIMEOUT		(1 << 20)
-#define DSIM_INT_RX_DONE		(1 << 18)
-#define DSIM_INT_RX_TE			(1 << 17)
-#define DSIM_INT_RX_ACK			(1 << 16)
-#define DSIM_INT_RX_ECC_ERR		(1 << 15)
-#define DSIM_INT_RX_CRC_ERR		(1 << 14)
-
-/* DSIM_FIFOCTRL */
-#define DSIM_RX_DATA_FULL		(1 << 25)
-#define DSIM_RX_DATA_EMPTY		(1 << 24)
-#define DSIM_SFR_HEADER_FULL		(1 << 23)
-#define DSIM_SFR_HEADER_EMPTY		(1 << 22)
-#define DSIM_SFR_PAYLOAD_FULL		(1 << 21)
-#define DSIM_SFR_PAYLOAD_EMPTY		(1 << 20)
-#define DSIM_I80_HEADER_FULL		(1 << 19)
-#define DSIM_I80_HEADER_EMPTY		(1 << 18)
-#define DSIM_I80_PAYLOAD_FULL		(1 << 17)
-#define DSIM_I80_PAYLOAD_EMPTY		(1 << 16)
-#define DSIM_SD_HEADER_FULL		(1 << 15)
-#define DSIM_SD_HEADER_EMPTY		(1 << 14)
-#define DSIM_SD_PAYLOAD_FULL		(1 << 13)
-#define DSIM_SD_PAYLOAD_EMPTY		(1 << 12)
-#define DSIM_MD_HEADER_FULL		(1 << 11)
-#define DSIM_MD_HEADER_EMPTY		(1 << 10)
-#define DSIM_MD_PAYLOAD_FULL		(1 << 9)
-#define DSIM_MD_PAYLOAD_EMPTY		(1 << 8)
-#define DSIM_RX_FIFO			(1 << 4)
-#define DSIM_SFR_FIFO			(1 << 3)
-#define DSIM_I80_FIFO			(1 << 2)
-#define DSIM_SD_FIFO			(1 << 1)
-#define DSIM_MD_FIFO			(1 << 0)
-
-/* DSIM_PHYACCHR */
-#define DSIM_AFC_EN			(1 << 14)
-#define DSIM_AFC_CTL(x)			(((x) & 0x7) << 5)
-
-/* DSIM_PLLCTRL */
-#define DSIM_FREQ_BAND(x)		((x) << 24)
-#define DSIM_PLL_EN			(1 << 23)
-#define DSIM_PLL_P(x)			((x) << 13)
-#define DSIM_PLL_M(x)			((x) << 4)
-#define DSIM_PLL_S(x)			((x) << 1)
-
-/* DSIM_PHYCTRL */
-#define DSIM_PHYCTRL_ULPS_EXIT(x)	(((x) & 0x1ff) << 0)
-#define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP	(1 << 30)
-#define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP	(1 << 14)
-
-/* DSIM_PHYTIMING */
-#define DSIM_PHYTIMING_LPX(x)		((x) << 8)
-#define DSIM_PHYTIMING_HS_EXIT(x)	((x) << 0)
-
-/* DSIM_PHYTIMING1 */
-#define DSIM_PHYTIMING1_CLK_PREPARE(x)	((x) << 24)
-#define DSIM_PHYTIMING1_CLK_ZERO(x)	((x) << 16)
-#define DSIM_PHYTIMING1_CLK_POST(x)	((x) << 8)
-#define DSIM_PHYTIMING1_CLK_TRAIL(x)	((x) << 0)
-
-/* DSIM_PHYTIMING2 */
-#define DSIM_PHYTIMING2_HS_PREPARE(x)	((x) << 16)
-#define DSIM_PHYTIMING2_HS_ZERO(x)	((x) << 8)
-#define DSIM_PHYTIMING2_HS_TRAIL(x)	((x) << 0)
-
-#define DSI_MAX_BUS_WIDTH		4
-#define DSI_NUM_VIRTUAL_CHANNELS	4
-#define DSI_TX_FIFO_SIZE		2048
-#define DSI_RX_FIFO_SIZE		256
-#define DSI_XFER_TIMEOUT_MS		100
-#define DSI_RX_FIFO_EMPTY		0x30800002
-
-#define OLD_SCLK_MIPI_CLK_NAME "pll_clk"
-
-static const char *const clk_names[5] = { "bus_clk", "sclk_mipi",
-	"phyclk_mipidphy0_bitclkdiv8", "phyclk_mipidphy0_rxclkesc0",
-	"sclk_rgb_vclk_to_dsim0" };
-
-enum exynos_dsi_transfer_type {
-	EXYNOS_DSI_TX,
-	EXYNOS_DSI_RX,
-};
-
-struct exynos_dsi_transfer {
-	struct list_head list;
-	struct completion completed;
-	int result;
-	struct mipi_dsi_packet packet;
-	u16 flags;
-	u16 tx_done;
-
-	u8 *rx_payload;
-	u16 rx_len;
-	u16 rx_done;
-};
-
-#define DSIM_STATE_ENABLED		BIT(0)
-#define DSIM_STATE_INITIALIZED		BIT(1)
-#define DSIM_STATE_CMD_LPM		BIT(2)
-#define DSIM_STATE_VIDOUT_AVAILABLE	BIT(3)
-
-struct exynos_dsi_driver_data {
-	const unsigned int *reg_ofs;
-	unsigned int plltmr_reg;
-	unsigned int has_freqband:1;
-	unsigned int has_clklane_stop:1;
-	unsigned int num_clks;
-	unsigned int max_freq;
-	unsigned int wait_for_reset;
-	unsigned int num_bits_resol;
-	const unsigned int *reg_values;
-};
-
 struct exynos_dsi {
 	struct drm_encoder encoder;
-	struct mipi_dsi_host dsi_host;
-	struct drm_bridge bridge;
-	struct drm_bridge *out_bridge;
-	struct device *dev;
-	struct drm_display_mode mode;
+	struct samsung_dsim *priv;
 
-	void __iomem *reg_base;
-	struct phy *phy;
-	struct clk **clks;
-	struct regulator_bulk_data supplies[2];
-	int irq;
 	struct gpio_desc *te_gpio;
 
-	u32 pll_clk_rate;
-	u32 burst_clk_rate;
-	u32 esc_clk_rate;
-	u32 lanes;
-	u32 mode_flags;
-	u32 format;
-
-	int state;
-	struct drm_property *brightness;
-	struct completion completed;
-
-	spinlock_t transfer_lock; /* protects transfer_list */
-	struct list_head transfer_list;
-
-	const struct exynos_dsi_driver_data *driver_data;
-};
-
-#define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host)
-
-static inline struct exynos_dsi *bridge_to_dsi(struct drm_bridge *b)
-{
-	return container_of(b, struct exynos_dsi, bridge);
-}
-
-enum reg_idx {
-	DSIM_STATUS_REG,	/* Status register */
-	DSIM_SWRST_REG,		/* Software reset register */
-	DSIM_CLKCTRL_REG,	/* Clock control register */
-	DSIM_TIMEOUT_REG,	/* Time out register */
-	DSIM_CONFIG_REG,	/* Configuration register */
-	DSIM_ESCMODE_REG,	/* Escape mode register */
-	DSIM_MDRESOL_REG,
-	DSIM_MVPORCH_REG,	/* Main display Vporch register */
-	DSIM_MHPORCH_REG,	/* Main display Hporch register */
-	DSIM_MSYNC_REG,		/* Main display sync area register */
-	DSIM_INTSRC_REG,	/* Interrupt source register */
-	DSIM_INTMSK_REG,	/* Interrupt mask register */
-	DSIM_PKTHDR_REG,	/* Packet Header FIFO register */
-	DSIM_PAYLOAD_REG,	/* Payload FIFO register */
-	DSIM_RXFIFO_REG,	/* Read FIFO register */
-	DSIM_FIFOCTRL_REG,	/* FIFO status and control register */
-	DSIM_PLLCTRL_REG,	/* PLL control register */
-	DSIM_PHYCTRL_REG,
-	DSIM_PHYTIMING_REG,
-	DSIM_PHYTIMING1_REG,
-	DSIM_PHYTIMING2_REG,
-	NUM_REGS
-};
-
-static inline void exynos_dsi_write(struct exynos_dsi *dsi, enum reg_idx idx,
-				    u32 val)
-{
-
-	writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
-}
-
-static inline u32 exynos_dsi_read(struct exynos_dsi *dsi, enum reg_idx idx)
-{
-	return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
-}
-
-static const unsigned int exynos_reg_ofs[] = {
-	[DSIM_STATUS_REG] =  0x00,
-	[DSIM_SWRST_REG] =  0x04,
-	[DSIM_CLKCTRL_REG] =  0x08,
-	[DSIM_TIMEOUT_REG] =  0x0c,
-	[DSIM_CONFIG_REG] =  0x10,
-	[DSIM_ESCMODE_REG] =  0x14,
-	[DSIM_MDRESOL_REG] =  0x18,
-	[DSIM_MVPORCH_REG] =  0x1c,
-	[DSIM_MHPORCH_REG] =  0x20,
-	[DSIM_MSYNC_REG] =  0x24,
-	[DSIM_INTSRC_REG] =  0x2c,
-	[DSIM_INTMSK_REG] =  0x30,
-	[DSIM_PKTHDR_REG] =  0x34,
-	[DSIM_PAYLOAD_REG] =  0x38,
-	[DSIM_RXFIFO_REG] =  0x3c,
-	[DSIM_FIFOCTRL_REG] =  0x44,
-	[DSIM_PLLCTRL_REG] =  0x4c,
-	[DSIM_PHYCTRL_REG] =  0x5c,
-	[DSIM_PHYTIMING_REG] =  0x64,
-	[DSIM_PHYTIMING1_REG] =  0x68,
-	[DSIM_PHYTIMING2_REG] =  0x6c,
-};
-
-static const unsigned int exynos5433_reg_ofs[] = {
-	[DSIM_STATUS_REG] = 0x04,
-	[DSIM_SWRST_REG] = 0x0C,
-	[DSIM_CLKCTRL_REG] = 0x10,
-	[DSIM_TIMEOUT_REG] = 0x14,
-	[DSIM_CONFIG_REG] = 0x18,
-	[DSIM_ESCMODE_REG] = 0x1C,
-	[DSIM_MDRESOL_REG] = 0x20,
-	[DSIM_MVPORCH_REG] = 0x24,
-	[DSIM_MHPORCH_REG] = 0x28,
-	[DSIM_MSYNC_REG] = 0x2C,
-	[DSIM_INTSRC_REG] = 0x34,
-	[DSIM_INTMSK_REG] = 0x38,
-	[DSIM_PKTHDR_REG] = 0x3C,
-	[DSIM_PAYLOAD_REG] = 0x40,
-	[DSIM_RXFIFO_REG] = 0x44,
-	[DSIM_FIFOCTRL_REG] = 0x4C,
-	[DSIM_PLLCTRL_REG] = 0x94,
-	[DSIM_PHYCTRL_REG] = 0xA4,
-	[DSIM_PHYTIMING_REG] = 0xB4,
-	[DSIM_PHYTIMING1_REG] = 0xB8,
-	[DSIM_PHYTIMING2_REG] = 0xBC,
-};
-
-enum reg_value_idx {
-	RESET_TYPE,
-	PLL_TIMER,
-	STOP_STATE_CNT,
-	PHYCTRL_ULPS_EXIT,
-	PHYCTRL_VREG_LP,
-	PHYCTRL_SLEW_UP,
-	PHYTIMING_LPX,
-	PHYTIMING_HS_EXIT,
-	PHYTIMING_CLK_PREPARE,
-	PHYTIMING_CLK_ZERO,
-	PHYTIMING_CLK_POST,
-	PHYTIMING_CLK_TRAIL,
-	PHYTIMING_HS_PREPARE,
-	PHYTIMING_HS_ZERO,
-	PHYTIMING_HS_TRAIL
-};
-
-static const unsigned int reg_values[] = {
-	[RESET_TYPE] = DSIM_SWRST,
-	[PLL_TIMER] = 500,
-	[STOP_STATE_CNT] = 0xf,
-	[PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af),
-	[PHYCTRL_VREG_LP] = 0,
-	[PHYCTRL_SLEW_UP] = 0,
-	[PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06),
-	[PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b),
-	[PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07),
-	[PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27),
-	[PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d),
-	[PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08),
-	[PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09),
-	[PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d),
-	[PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b),
+	struct samsung_dsim_plat_data pdata;
 };
 
-static const unsigned int exynos5422_reg_values[] = {
-	[RESET_TYPE] = DSIM_SWRST,
-	[PLL_TIMER] = 500,
-	[STOP_STATE_CNT] = 0xf,
-	[PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf),
-	[PHYCTRL_VREG_LP] = 0,
-	[PHYCTRL_SLEW_UP] = 0,
-	[PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08),
-	[PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d),
-	[PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
-	[PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30),
-	[PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
-	[PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a),
-	[PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c),
-	[PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11),
-	[PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d),
-};
-
-static const unsigned int exynos5433_reg_values[] = {
-	[RESET_TYPE] = DSIM_FUNCRST,
-	[PLL_TIMER] = 22200,
-	[STOP_STATE_CNT] = 0xa,
-	[PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190),
-	[PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP,
-	[PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP,
-	[PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07),
-	[PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c),
-	[PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
-	[PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d),
-	[PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
-	[PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09),
-	[PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b),
-	[PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10),
-	[PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c),
-};
-
-static const struct exynos_dsi_driver_data exynos3_dsi_driver_data = {
-	.reg_ofs = exynos_reg_ofs,
-	.plltmr_reg = 0x50,
-	.has_freqband = 1,
-	.has_clklane_stop = 1,
-	.num_clks = 2,
-	.max_freq = 1000,
-	.wait_for_reset = 1,
-	.num_bits_resol = 11,
-	.reg_values = reg_values,
-};
-
-static const struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
-	.reg_ofs = exynos_reg_ofs,
-	.plltmr_reg = 0x50,
-	.has_freqband = 1,
-	.has_clklane_stop = 1,
-	.num_clks = 2,
-	.max_freq = 1000,
-	.wait_for_reset = 1,
-	.num_bits_resol = 11,
-	.reg_values = reg_values,
-};
-
-static const struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
-	.reg_ofs = exynos_reg_ofs,
-	.plltmr_reg = 0x58,
-	.num_clks = 2,
-	.max_freq = 1000,
-	.wait_for_reset = 1,
-	.num_bits_resol = 11,
-	.reg_values = reg_values,
-};
-
-static const struct exynos_dsi_driver_data exynos5433_dsi_driver_data = {
-	.reg_ofs = exynos5433_reg_ofs,
-	.plltmr_reg = 0xa0,
-	.has_clklane_stop = 1,
-	.num_clks = 5,
-	.max_freq = 1500,
-	.wait_for_reset = 0,
-	.num_bits_resol = 12,
-	.reg_values = exynos5433_reg_values,
-};
-
-static const struct exynos_dsi_driver_data exynos5422_dsi_driver_data = {
-	.reg_ofs = exynos5433_reg_ofs,
-	.plltmr_reg = 0xa0,
-	.has_clklane_stop = 1,
-	.num_clks = 2,
-	.max_freq = 1500,
-	.wait_for_reset = 1,
-	.num_bits_resol = 12,
-	.reg_values = exynos5422_reg_values,
-};
-
-static const struct of_device_id exynos_dsi_of_match[] = {
-	{ .compatible = "samsung,exynos3250-mipi-dsi",
-	  .data = &exynos3_dsi_driver_data },
-	{ .compatible = "samsung,exynos4210-mipi-dsi",
-	  .data = &exynos4_dsi_driver_data },
-	{ .compatible = "samsung,exynos5410-mipi-dsi",
-	  .data = &exynos5_dsi_driver_data },
-	{ .compatible = "samsung,exynos5422-mipi-dsi",
-	  .data = &exynos5422_dsi_driver_data },
-	{ .compatible = "samsung,exynos5433-mipi-dsi",
-	  .data = &exynos5433_dsi_driver_data },
-	{ }
-};
-
-static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi)
-{
-	if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
-		return;
-
-	dev_err(dsi->dev, "timeout waiting for reset\n");
-}
-
-static void exynos_dsi_reset(struct exynos_dsi *dsi)
-{
-	u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE];
-
-	reinit_completion(&dsi->completed);
-	exynos_dsi_write(dsi, DSIM_SWRST_REG, reset_val);
-}
-
-#ifndef MHZ
-#define MHZ	(1000*1000)
-#endif
-
-static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi,
-		unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s)
+static void exynos_dsi_enable_irq(void *priv)
 {
-	const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
-	unsigned long best_freq = 0;
-	u32 min_delta = 0xffffffff;
-	u8 p_min, p_max;
-	u8 _p, best_p;
-	u16 _m, best_m;
-	u8 _s, best_s;
-
-	p_min = DIV_ROUND_UP(fin, (12 * MHZ));
-	p_max = fin / (6 * MHZ);
-
-	for (_p = p_min; _p <= p_max; ++_p) {
-		for (_s = 0; _s <= 5; ++_s) {
-			u64 tmp;
-			u32 delta;
-
-			tmp = (u64)fout * (_p << _s);
-			do_div(tmp, fin);
-			_m = tmp;
-			if (_m < 41 || _m > 125)
-				continue;
-
-			tmp = (u64)_m * fin;
-			do_div(tmp, _p);
-			if (tmp < 500 * MHZ ||
-					tmp > driver_data->max_freq * MHZ)
-				continue;
-
-			tmp = (u64)_m * fin;
-			do_div(tmp, _p << _s);
-
-			delta = abs(fout - tmp);
-			if (delta < min_delta) {
-				best_p = _p;
-				best_m = _m;
-				best_s = _s;
-				min_delta = delta;
-				best_freq = tmp;
-			}
-		}
-	}
-
-	if (best_freq) {
-		*p = best_p;
-		*m = best_m;
-		*s = best_s;
-	}
-
-	return best_freq;
-}
-
-static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
-					unsigned long freq)
-{
-	const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
-	unsigned long fin, fout;
-	int timeout;
-	u8 p, s;
-	u16 m;
-	u32 reg;
-
-	fin = dsi->pll_clk_rate;
-	fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s);
-	if (!fout) {
-		dev_err(dsi->dev,
-			"failed to find PLL PMS for requested frequency\n");
-		return 0;
-	}
-	dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s);
-
-	writel(driver_data->reg_values[PLL_TIMER],
-			dsi->reg_base + driver_data->plltmr_reg);
-
-	reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s);
-
-	if (driver_data->has_freqband) {
-		static const unsigned long freq_bands[] = {
-			100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
-			270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
-			510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
-			770 * MHZ, 870 * MHZ, 950 * MHZ,
-		};
-		int band;
-
-		for (band = 0; band < ARRAY_SIZE(freq_bands); ++band)
-			if (fout < freq_bands[band])
-				break;
-
-		dev_dbg(dsi->dev, "band %d\n", band);
-
-		reg |= DSIM_FREQ_BAND(band);
-	}
-
-	exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg);
-
-	timeout = 1000;
-	do {
-		if (timeout-- == 0) {
-			dev_err(dsi->dev, "PLL failed to stabilize\n");
-			return 0;
-		}
-		reg = exynos_dsi_read(dsi, DSIM_STATUS_REG);
-	} while ((reg & DSIM_PLL_STABLE) == 0);
-
-	return fout;
-}
-
-static int exynos_dsi_enable_clock(struct exynos_dsi *dsi)
-{
-	unsigned long hs_clk, byte_clk, esc_clk;
-	unsigned long esc_div;
-	u32 reg;
-
-	hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate);
-	if (!hs_clk) {
-		dev_err(dsi->dev, "failed to configure DSI PLL\n");
-		return -EFAULT;
-	}
-
-	byte_clk = hs_clk / 8;
-	esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate);
-	esc_clk = byte_clk / esc_div;
-
-	if (esc_clk > 20 * MHZ) {
-		++esc_div;
-		esc_clk = byte_clk / esc_div;
-	}
-
-	dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n",
-		hs_clk, byte_clk, esc_clk);
-
-	reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG);
-	reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK
-			| DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS
-			| DSIM_BYTE_CLK_SRC_MASK);
-	reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN
-			| DSIM_ESC_PRESCALER(esc_div)
-			| DSIM_LANE_ESC_CLK_EN_CLK
-			| DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1)
-			| DSIM_BYTE_CLK_SRC(0)
-			| DSIM_TX_REQUEST_HSCLK;
-	exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg);
-
-	return 0;
-}
-
-static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi)
-{
-	const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
-	const unsigned int *reg_values = driver_data->reg_values;
-	u32 reg;
-
-	if (driver_data->has_freqband)
-		return;
-
-	/* B D-PHY: D-PHY Master & Slave Analog Block control */
-	reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] |
-		reg_values[PHYCTRL_SLEW_UP];
-	exynos_dsi_write(dsi, DSIM_PHYCTRL_REG, reg);
-
-	/*
-	 * T LPX: Transmitted length of any Low-Power state period
-	 * T HS-EXIT: Time that the transmitter drives LP-11 following a HS
-	 *	burst
-	 */
-	reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT];
-	exynos_dsi_write(dsi, DSIM_PHYTIMING_REG, reg);
-
-	/*
-	 * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00
-	 *	Line state immediately before the HS-0 Line state starting the
-	 *	HS transmission
-	 * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to
-	 *	transmitting the Clock.
-	 * T CLK_POST: Time that the transmitter continues to send HS clock
-	 *	after the last associated Data Lane has transitioned to LP Mode
-	 *	Interval is defined as the period from the end of T HS-TRAIL to
-	 *	the beginning of T CLK-TRAIL
-	 * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after
-	 *	the last payload clock bit of a HS transmission burst
-	 */
-	reg = reg_values[PHYTIMING_CLK_PREPARE] |
-		reg_values[PHYTIMING_CLK_ZERO] |
-		reg_values[PHYTIMING_CLK_POST] |
-		reg_values[PHYTIMING_CLK_TRAIL];
-
-	exynos_dsi_write(dsi, DSIM_PHYTIMING1_REG, reg);
-
-	/*
-	 * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00
-	 *	Line state immediately before the HS-0 Line state starting the
-	 *	HS transmission
-	 * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to
-	 *	transmitting the Sync sequence.
-	 * T HS-TRAIL: Time that the transmitter drives the flipped differential
-	 *	state after last payload data bit of a HS transmission burst
-	 */
-	reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] |
-		reg_values[PHYTIMING_HS_TRAIL];
-	exynos_dsi_write(dsi, DSIM_PHYTIMING2_REG, reg);
-}
-
-static void exynos_dsi_disable_clock(struct exynos_dsi *dsi)
-{
-	u32 reg;
-
-	reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG);
-	reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK
-			| DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN);
-	exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg);
-
-	reg = exynos_dsi_read(dsi, DSIM_PLLCTRL_REG);
-	reg &= ~DSIM_PLL_EN;
-	exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg);
-}
-
-static void exynos_dsi_enable_lane(struct exynos_dsi *dsi, u32 lane)
-{
-	u32 reg = exynos_dsi_read(dsi, DSIM_CONFIG_REG);
-	reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK |
-			DSIM_LANE_EN(lane));
-	exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg);
-}
-
-static int exynos_dsi_init_link(struct exynos_dsi *dsi)
-{
-	const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
-	int timeout;
-	u32 reg;
-	u32 lanes_mask;
-
-	/* Initialize FIFO pointers */
-	reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG);
-	reg &= ~0x1f;
-	exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg);
-
-	usleep_range(9000, 11000);
-
-	reg |= 0x1f;
-	exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg);
-	usleep_range(9000, 11000);
-
-	/* DSI configuration */
-	reg = 0;
-
-	/*
-	 * The first bit of mode_flags specifies display configuration.
-	 * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video
-	 * mode, otherwise it will support command mode.
-	 */
-	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
-		reg |= DSIM_VIDEO_MODE;
-
-		/*
-		 * The user manual describes that following bits are ignored in
-		 * command mode.
-		 */
-		if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
-			reg |= DSIM_MFLUSH_VS;
-		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
-			reg |= DSIM_SYNC_INFORM;
-		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
-			reg |= DSIM_BURST_MODE;
-		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT)
-			reg |= DSIM_AUTO_MODE;
-		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE)
-			reg |= DSIM_HSE_MODE;
-		if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP))
-			reg |= DSIM_HFP_MODE;
-		if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP))
-			reg |= DSIM_HBP_MODE;
-		if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HSA))
-			reg |= DSIM_HSA_MODE;
-	}
-
-	if (!(dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET))
-		reg |= DSIM_EOT_DISABLE;
-
-	switch (dsi->format) {
-	case MIPI_DSI_FMT_RGB888:
-		reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
-		break;
-	case MIPI_DSI_FMT_RGB666:
-		reg |= DSIM_MAIN_PIX_FORMAT_RGB666;
-		break;
-	case MIPI_DSI_FMT_RGB666_PACKED:
-		reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P;
-		break;
-	case MIPI_DSI_FMT_RGB565:
-		reg |= DSIM_MAIN_PIX_FORMAT_RGB565;
-		break;
-	default:
-		dev_err(dsi->dev, "invalid pixel format\n");
-		return -EINVAL;
-	}
-
-	/*
-	 * Use non-continuous clock mode if the periparal wants and
-	 * host controller supports
-	 *
-	 * In non-continous clock mode, host controller will turn off
-	 * the HS clock between high-speed transmissions to reduce
-	 * power consumption.
-	 */
-	if (driver_data->has_clklane_stop &&
-			dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
-		reg |= DSIM_CLKLANE_STOP;
-	}
-	exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg);
-
-	lanes_mask = BIT(dsi->lanes) - 1;
-	exynos_dsi_enable_lane(dsi, lanes_mask);
-
-	/* Check clock and data lane state are stop state */
-	timeout = 100;
-	do {
-		if (timeout-- == 0) {
-			dev_err(dsi->dev, "waiting for bus lanes timed out\n");
-			return -EFAULT;
-		}
-
-		reg = exynos_dsi_read(dsi, DSIM_STATUS_REG);
-		if ((reg & DSIM_STOP_STATE_DAT(lanes_mask))
-		    != DSIM_STOP_STATE_DAT(lanes_mask))
-			continue;
-	} while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK)));
-
-	reg = exynos_dsi_read(dsi, DSIM_ESCMODE_REG);
-	reg &= ~DSIM_STOP_STATE_CNT_MASK;
-	reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]);
-	exynos_dsi_write(dsi, DSIM_ESCMODE_REG, reg);
-
-	reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff);
-	exynos_dsi_write(dsi, DSIM_TIMEOUT_REG, reg);
-
-	return 0;
-}
-
-static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi)
-{
-	struct drm_display_mode *m = &dsi->mode;
-	unsigned int num_bits_resol = dsi->driver_data->num_bits_resol;
-	u32 reg;
-
-	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
-		reg = DSIM_CMD_ALLOW(0xf)
-			| DSIM_STABLE_VFP(m->vsync_start - m->vdisplay)
-			| DSIM_MAIN_VBP(m->vtotal - m->vsync_end);
-		exynos_dsi_write(dsi, DSIM_MVPORCH_REG, reg);
-
-		reg = DSIM_MAIN_HFP(m->hsync_start - m->hdisplay)
-			| DSIM_MAIN_HBP(m->htotal - m->hsync_end);
-		exynos_dsi_write(dsi, DSIM_MHPORCH_REG, reg);
-
-		reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start)
-			| DSIM_MAIN_HSA(m->hsync_end - m->hsync_start);
-		exynos_dsi_write(dsi, DSIM_MSYNC_REG, reg);
-	}
-	reg =  DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) |
-		DSIM_MAIN_VRESOL(m->vdisplay, num_bits_resol);
-
-	exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg);
-
-	dev_dbg(dsi->dev, "LCD size = %dx%d\n", m->hdisplay, m->vdisplay);
-}
-
-static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable)
-{
-	u32 reg;
-
-	reg = exynos_dsi_read(dsi, DSIM_MDRESOL_REG);
-	if (enable)
-		reg |= DSIM_MAIN_STAND_BY;
-	else
-		reg &= ~DSIM_MAIN_STAND_BY;
-	exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg);
-}
-
-static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi)
-{
-	int timeout = 2000;
-
-	do {
-		u32 reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG);
-
-		if (!(reg & DSIM_SFR_HEADER_FULL))
-			return 0;
-
-		if (!cond_resched())
-			usleep_range(950, 1050);
-	} while (--timeout);
-
-	return -ETIMEDOUT;
-}
-
-static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm)
-{
-	u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG);
-
-	if (lpm)
-		v |= DSIM_CMD_LPDT_LP;
-	else
-		v &= ~DSIM_CMD_LPDT_LP;
-
-	exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v);
-}
-
-static void exynos_dsi_force_bta(struct exynos_dsi *dsi)
-{
-	u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG);
-	v |= DSIM_FORCE_BTA;
-	exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v);
-}
-
-static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi,
-					struct exynos_dsi_transfer *xfer)
-{
-	struct device *dev = dsi->dev;
-	struct mipi_dsi_packet *pkt = &xfer->packet;
-	const u8 *payload = pkt->payload + xfer->tx_done;
-	u16 length = pkt->payload_length - xfer->tx_done;
-	bool first = !xfer->tx_done;
-	u32 reg;
-
-	dev_dbg(dev, "< xfer %pK: tx len %u, done %u, rx len %u, done %u\n",
-		xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done);
-
-	if (length > DSI_TX_FIFO_SIZE)
-		length = DSI_TX_FIFO_SIZE;
-
-	xfer->tx_done += length;
-
-	/* Send payload */
-	while (length >= 4) {
-		reg = get_unaligned_le32(payload);
-		exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg);
-		payload += 4;
-		length -= 4;
-	}
-
-	reg = 0;
-	switch (length) {
-	case 3:
-		reg |= payload[2] << 16;
-		fallthrough;
-	case 2:
-		reg |= payload[1] << 8;
-		fallthrough;
-	case 1:
-		reg |= payload[0];
-		exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg);
-		break;
-	}
-
-	/* Send packet header */
-	if (!first)
-		return;
-
-	reg = get_unaligned_le32(pkt->header);
-	if (exynos_dsi_wait_for_hdr_fifo(dsi)) {
-		dev_err(dev, "waiting for header FIFO timed out\n");
-		return;
-	}
-
-	if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM,
-		 dsi->state & DSIM_STATE_CMD_LPM)) {
-		exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM);
-		dsi->state ^= DSIM_STATE_CMD_LPM;
-	}
-
-	exynos_dsi_write(dsi, DSIM_PKTHDR_REG, reg);
-
-	if (xfer->flags & MIPI_DSI_MSG_REQ_ACK)
-		exynos_dsi_force_bta(dsi);
-}
-
-static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi,
-					struct exynos_dsi_transfer *xfer)
-{
-	u8 *payload = xfer->rx_payload + xfer->rx_done;
-	bool first = !xfer->rx_done;
-	struct device *dev = dsi->dev;
-	u16 length;
-	u32 reg;
-
-	if (first) {
-		reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
-
-		switch (reg & 0x3f) {
-		case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
-		case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
-			if (xfer->rx_len >= 2) {
-				payload[1] = reg >> 16;
-				++xfer->rx_done;
-			}
-			fallthrough;
-		case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
-		case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
-			payload[0] = reg >> 8;
-			++xfer->rx_done;
-			xfer->rx_len = xfer->rx_done;
-			xfer->result = 0;
-			goto clear_fifo;
-		case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
-			dev_err(dev, "DSI Error Report: 0x%04x\n",
-				(reg >> 8) & 0xffff);
-			xfer->result = 0;
-			goto clear_fifo;
-		}
-
-		length = (reg >> 8) & 0xffff;
-		if (length > xfer->rx_len) {
-			dev_err(dev,
-				"response too long (%u > %u bytes), stripping\n",
-				xfer->rx_len, length);
-			length = xfer->rx_len;
-		} else if (length < xfer->rx_len)
-			xfer->rx_len = length;
-	}
-
-	length = xfer->rx_len - xfer->rx_done;
-	xfer->rx_done += length;
-
-	/* Receive payload */
-	while (length >= 4) {
-		reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
-		payload[0] = (reg >>  0) & 0xff;
-		payload[1] = (reg >>  8) & 0xff;
-		payload[2] = (reg >> 16) & 0xff;
-		payload[3] = (reg >> 24) & 0xff;
-		payload += 4;
-		length -= 4;
-	}
-
-	if (length) {
-		reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
-		switch (length) {
-		case 3:
-			payload[2] = (reg >> 16) & 0xff;
-			fallthrough;
-		case 2:
-			payload[1] = (reg >> 8) & 0xff;
-			fallthrough;
-		case 1:
-			payload[0] = reg & 0xff;
-		}
-	}
-
-	if (xfer->rx_done == xfer->rx_len)
-		xfer->result = 0;
+	struct exynos_dsi *dsi = priv;
 
-clear_fifo:
-	length = DSI_RX_FIFO_SIZE / 4;
-	do {
-		reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
-		if (reg == DSI_RX_FIFO_EMPTY)
-			break;
-	} while (--length);
-}
-
-static void exynos_dsi_transfer_start(struct exynos_dsi *dsi)
-{
-	unsigned long flags;
-	struct exynos_dsi_transfer *xfer;
-	bool start = false;
-
-again:
-	spin_lock_irqsave(&dsi->transfer_lock, flags);
-
-	if (list_empty(&dsi->transfer_list)) {
-		spin_unlock_irqrestore(&dsi->transfer_lock, flags);
-		return;
-	}
-
-	xfer = list_first_entry(&dsi->transfer_list,
-					struct exynos_dsi_transfer, list);
-
-	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
-
-	if (xfer->packet.payload_length &&
-	    xfer->tx_done == xfer->packet.payload_length)
-		/* waiting for RX */
-		return;
-
-	exynos_dsi_send_to_fifo(dsi, xfer);
-
-	if (xfer->packet.payload_length || xfer->rx_len)
-		return;
-
-	xfer->result = 0;
-	complete(&xfer->completed);
-
-	spin_lock_irqsave(&dsi->transfer_lock, flags);
-
-	list_del_init(&xfer->list);
-	start = !list_empty(&dsi->transfer_list);
-
-	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
-
-	if (start)
-		goto again;
-}
-
-static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi)
-{
-	struct exynos_dsi_transfer *xfer;
-	unsigned long flags;
-	bool start = true;
-
-	spin_lock_irqsave(&dsi->transfer_lock, flags);
-
-	if (list_empty(&dsi->transfer_list)) {
-		spin_unlock_irqrestore(&dsi->transfer_lock, flags);
-		return false;
-	}
-
-	xfer = list_first_entry(&dsi->transfer_list,
-					struct exynos_dsi_transfer, list);
-
-	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
-
-	dev_dbg(dsi->dev,
-		"> xfer %pK, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n",
-		xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len,
-		xfer->rx_done);
-
-	if (xfer->tx_done != xfer->packet.payload_length)
-		return true;
-
-	if (xfer->rx_done != xfer->rx_len)
-		exynos_dsi_read_from_fifo(dsi, xfer);
-
-	if (xfer->rx_done != xfer->rx_len)
-		return true;
-
-	spin_lock_irqsave(&dsi->transfer_lock, flags);
-
-	list_del_init(&xfer->list);
-	start = !list_empty(&dsi->transfer_list);
-
-	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
-
-	if (!xfer->rx_len)
-		xfer->result = 0;
-	complete(&xfer->completed);
-
-	return start;
-}
-
-static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi,
-					struct exynos_dsi_transfer *xfer)
-{
-	unsigned long flags;
-	bool start;
-
-	spin_lock_irqsave(&dsi->transfer_lock, flags);
-
-	if (!list_empty(&dsi->transfer_list) &&
-	    xfer == list_first_entry(&dsi->transfer_list,
-				     struct exynos_dsi_transfer, list)) {
-		list_del_init(&xfer->list);
-		start = !list_empty(&dsi->transfer_list);
-		spin_unlock_irqrestore(&dsi->transfer_lock, flags);
-		if (start)
-			exynos_dsi_transfer_start(dsi);
-		return;
-	}
-
-	list_del_init(&xfer->list);
-
-	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
+	if (dsi->te_gpio)
+		enable_irq(gpiod_to_irq(dsi->te_gpio));
 }
 
-static int exynos_dsi_transfer(struct exynos_dsi *dsi,
-					struct exynos_dsi_transfer *xfer)
+static void exynos_dsi_disable_irq(void *priv)
 {
-	unsigned long flags;
-	bool stopped;
+	struct exynos_dsi *dsi = priv;
 
-	xfer->tx_done = 0;
-	xfer->rx_done = 0;
-	xfer->result = -ETIMEDOUT;
-	init_completion(&xfer->completed);
-
-	spin_lock_irqsave(&dsi->transfer_lock, flags);
-
-	stopped = list_empty(&dsi->transfer_list);
-	list_add_tail(&xfer->list, &dsi->transfer_list);
-
-	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
-
-	if (stopped)
-		exynos_dsi_transfer_start(dsi);
-
-	wait_for_completion_timeout(&xfer->completed,
-				    msecs_to_jiffies(DSI_XFER_TIMEOUT_MS));
-	if (xfer->result == -ETIMEDOUT) {
-		struct mipi_dsi_packet *pkt = &xfer->packet;
-		exynos_dsi_remove_transfer(dsi, xfer);
-		dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 4, pkt->header,
-			(int)pkt->payload_length, pkt->payload);
-		return -ETIMEDOUT;
-	}
-
-	/* Also covers hardware timeout condition */
-	return xfer->result;
+	if (dsi->te_gpio)
+		disable_irq(gpiod_to_irq(dsi->te_gpio));
 }
 
-static irqreturn_t exynos_dsi_irq(int irq, void *dev_id)
-{
-	struct exynos_dsi *dsi = dev_id;
-	u32 status;
-
-	status = exynos_dsi_read(dsi, DSIM_INTSRC_REG);
-	if (!status) {
-		static unsigned long int j;
-		if (printk_timed_ratelimit(&j, 500))
-			dev_warn(dsi->dev, "spurious interrupt\n");
-		return IRQ_HANDLED;
-	}
-	exynos_dsi_write(dsi, DSIM_INTSRC_REG, status);
-
-	if (status & DSIM_INT_SW_RST_RELEASE) {
-		u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |
-			DSIM_INT_SFR_HDR_FIFO_EMPTY | DSIM_INT_RX_ECC_ERR |
-			DSIM_INT_SW_RST_RELEASE);
-		exynos_dsi_write(dsi, DSIM_INTMSK_REG, mask);
-		complete(&dsi->completed);
-		return IRQ_HANDLED;
-	}
-
-	if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |
-			DSIM_INT_PLL_STABLE)))
-		return IRQ_HANDLED;
-
-	if (exynos_dsi_transfer_finish(dsi))
-		exynos_dsi_transfer_start(dsi);
-
-	return IRQ_HANDLED;
-}
+static const struct samsung_dsim_irq_ops samsung_dsim_exynos_host_irq = {
+	.enable = exynos_dsi_enable_irq,
+	.disable = exynos_dsi_disable_irq,
+};
 
 static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id)
 {
 	struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id;
+	struct samsung_dsim *priv = dsi->priv;
 	struct drm_encoder *encoder = &dsi->encoder;
 
-	if (dsi->state & DSIM_STATE_VIDOUT_AVAILABLE)
+	if (priv->state & DSIM_STATE_VIDOUT_AVAILABLE)
 		exynos_drm_crtc_te_handler(encoder->crtc);
 
 	return IRQ_HANDLED;
 }
 
-static void exynos_dsi_enable_irq(struct exynos_dsi *dsi)
-{
-	enable_irq(dsi->irq);
-
-	if (dsi->te_gpio)
-		enable_irq(gpiod_to_irq(dsi->te_gpio));
-}
-
-static void exynos_dsi_disable_irq(struct exynos_dsi *dsi)
-{
-	if (dsi->te_gpio)
-		disable_irq(gpiod_to_irq(dsi->te_gpio));
-
-	disable_irq(dsi->irq);
-}
-
-static int exynos_dsi_init(struct exynos_dsi *dsi)
-{
-	const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
-
-	exynos_dsi_reset(dsi);
-	exynos_dsi_enable_irq(dsi);
-
-	if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST)
-		exynos_dsi_enable_lane(dsi, BIT(dsi->lanes) - 1);
-
-	exynos_dsi_enable_clock(dsi);
-	if (driver_data->wait_for_reset)
-		exynos_dsi_wait_for_reset(dsi);
-	exynos_dsi_set_phy_ctrl(dsi);
-	exynos_dsi_init_link(dsi);
-
-	return 0;
-}
-
-static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi,
-				      struct device *panel)
+static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi, struct device *panel)
 {
-	int ret;
+	struct samsung_dsim *priv = dsi->priv;
 	int te_gpio_irq;
+	int ret;
 
-	dsi->te_gpio = devm_gpiod_get_optional(dsi->dev, "te", GPIOD_IN);
+	dsi->te_gpio = devm_gpiod_get_optional(priv->dev, "te", GPIOD_IN);
 	if (IS_ERR(dsi->te_gpio)) {
-		dev_err(dsi->dev, "gpio request failed with %ld\n",
+		dev_err(priv->dev, "gpio request failed with %ld\n",
 				PTR_ERR(dsi->te_gpio));
 		return PTR_ERR(dsi->te_gpio);
 	}
@@ -1342,7 +76,7 @@ static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi,
 	ret = request_threaded_irq(te_gpio_irq, exynos_dsi_te_irq_handler, NULL,
 				   IRQF_TRIGGER_RISING | IRQF_NO_AUTOEN, "TE", dsi);
 	if (ret) {
-		dev_err(dsi->dev, "request interrupt failed with %d\n", ret);
+		dev_err(priv->dev, "request interrupt failed with %d\n", ret);
 		gpiod_put(dsi->te_gpio);
 		return ret;
 	}
@@ -1358,111 +92,15 @@ static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi)
 	}
 }
 
-static void exynos_dsi_atomic_pre_enable(struct drm_bridge *bridge,
-					 struct drm_bridge_state *old_bridge_state)
-{
-	struct exynos_dsi *dsi = bridge_to_dsi(bridge);
-	int ret;
-
-	if (dsi->state & DSIM_STATE_ENABLED)
-		return;
-
-	ret = pm_runtime_resume_and_get(dsi->dev);
-	if (ret < 0) {
-		dev_err(dsi->dev, "failed to enable DSI device.\n");
-		return;
-	}
-
-	dsi->state |= DSIM_STATE_ENABLED;
-}
-
-static void exynos_dsi_atomic_enable(struct drm_bridge *bridge,
-				     struct drm_bridge_state *old_bridge_state)
-{
-	struct exynos_dsi *dsi = bridge_to_dsi(bridge);
-
-	exynos_dsi_set_display_mode(dsi);
-	exynos_dsi_set_display_enable(dsi, true);
-
-	dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE;
-
-	return;
-}
-
-static void exynos_dsi_atomic_disable(struct drm_bridge *bridge,
-				      struct drm_bridge_state *old_bridge_state)
-{
-	struct exynos_dsi *dsi = bridge_to_dsi(bridge);
-
-	if (!(dsi->state & DSIM_STATE_ENABLED))
-		return;
-
-	dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE;
-}
-
-static void exynos_dsi_atomic_post_disable(struct drm_bridge *bridge,
-					   struct drm_bridge_state *old_bridge_state)
-{
-	struct exynos_dsi *dsi = bridge_to_dsi(bridge);
-
-	exynos_dsi_set_display_enable(dsi, false);
-
-	dsi->state &= ~DSIM_STATE_ENABLED;
-	pm_runtime_put_sync(dsi->dev);
-}
-
-static void exynos_dsi_mode_set(struct drm_bridge *bridge,
-				const struct drm_display_mode *mode,
-				const struct drm_display_mode *adjusted_mode)
-{
-	struct exynos_dsi *dsi = bridge_to_dsi(bridge);
-
-	drm_mode_copy(&dsi->mode, adjusted_mode);
-}
-
-static int exynos_dsi_attach(struct drm_bridge *bridge,
-			     enum drm_bridge_attach_flags flags)
+static int exynos_dsi_host_attach(void *priv, struct mipi_dsi_device *device)
 {
-	struct exynos_dsi *dsi = bridge_to_dsi(bridge);
-
-	return drm_bridge_attach(bridge->encoder, dsi->out_bridge, NULL, flags);
-}
-
-static const struct drm_bridge_funcs exynos_dsi_bridge_funcs = {
-	.atomic_duplicate_state		= drm_atomic_helper_bridge_duplicate_state,
-	.atomic_destroy_state		= drm_atomic_helper_bridge_destroy_state,
-	.atomic_reset			= drm_atomic_helper_bridge_reset,
-	.atomic_pre_enable		= exynos_dsi_atomic_pre_enable,
-	.atomic_enable			= exynos_dsi_atomic_enable,
-	.atomic_disable			= exynos_dsi_atomic_disable,
-	.atomic_post_disable		= exynos_dsi_atomic_post_disable,
-	.mode_set			= exynos_dsi_mode_set,
-	.attach				= exynos_dsi_attach,
-};
-
-MODULE_DEVICE_TABLE(of, exynos_dsi_of_match);
-
-static int exynos_dsi_host_attach(struct mipi_dsi_host *host,
-				  struct mipi_dsi_device *device)
-{
-	struct exynos_dsi *dsi = host_to_dsi(host);
-	struct device *dev = dsi->dev;
+	struct exynos_dsi *dsi = priv;
+	struct samsung_dsim *_priv = dsi->priv;
 	struct drm_encoder *encoder = &dsi->encoder;
 	struct drm_device *drm = encoder->dev;
 	int ret;
 
-	dsi->out_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0);
-	if (IS_ERR(dsi->out_bridge)) {
-		ret = PTR_ERR(dsi->out_bridge);
-		DRM_DEV_ERROR(dev, "failed to find the bridge: %d\n", ret);
-		return ret;
-	}
-
-	DRM_DEV_INFO(dev, "Attached %s device\n", device->name);
-
-	drm_bridge_add(&dsi->bridge);
-
-	drm_bridge_attach(encoder, &dsi->bridge, NULL, 0);
+	drm_bridge_attach(encoder, &_priv->bridge, NULL, 0);
 
 	/*
 	 * This is a temporary solution and should be made by more generic way.
@@ -1478,11 +116,11 @@ static int exynos_dsi_host_attach(struct mipi_dsi_host *host,
 
 	mutex_lock(&drm->mode_config.mutex);
 
-	dsi->lanes = device->lanes;
-	dsi->format = device->format;
-	dsi->mode_flags = device->mode_flags;
+	_priv->lanes = device->lanes;
+	_priv->format = device->format;
+	_priv->mode_flags = device->mode_flags;
 	exynos_drm_crtc_get_by_type(drm, EXYNOS_DISPLAY_TYPE_LCD)->i80_mode =
-			!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO);
+			!(_priv->mode_flags & MIPI_DSI_MODE_VIDEO);
 
 	mutex_unlock(&drm->mode_config.mutex);
 
@@ -1492,99 +130,28 @@ static int exynos_dsi_host_attach(struct mipi_dsi_host *host,
 	return 0;
 }
 
-static int exynos_dsi_host_detach(struct mipi_dsi_host *host,
-				  struct mipi_dsi_device *device)
+static int exynos_dsi_host_detach(void *priv, struct mipi_dsi_device *device)
 {
-	struct exynos_dsi *dsi = host_to_dsi(host);
+	struct exynos_dsi *dsi = priv;
 	struct drm_device *drm = dsi->encoder.dev;
 
-	if (dsi->out_bridge->funcs->detach)
-		dsi->out_bridge->funcs->detach(dsi->out_bridge);
-
 	if (drm->mode_config.poll_enabled)
 		drm_kms_helper_hotplug_event(drm);
 
 	exynos_dsi_unregister_te_irq(dsi);
 
-	drm_bridge_remove(&dsi->bridge);
-
 	return 0;
 }
 
-static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host,
-					 const struct mipi_dsi_msg *msg)
-{
-	struct exynos_dsi *dsi = host_to_dsi(host);
-	struct exynos_dsi_transfer xfer;
-	int ret;
-
-	if (!(dsi->state & DSIM_STATE_ENABLED))
-		return -EINVAL;
-
-	if (!(dsi->state & DSIM_STATE_INITIALIZED)) {
-		ret = exynos_dsi_init(dsi);
-		if (ret)
-			return ret;
-		dsi->state |= DSIM_STATE_INITIALIZED;
-	}
-
-	ret = mipi_dsi_create_packet(&xfer.packet, msg);
-	if (ret < 0)
-		return ret;
-
-	xfer.rx_len = msg->rx_len;
-	xfer.rx_payload = msg->rx_buf;
-	xfer.flags = msg->flags;
-
-	ret = exynos_dsi_transfer(dsi, &xfer);
-	return (ret < 0) ? ret : xfer.rx_done;
-}
-
-static const struct mipi_dsi_host_ops exynos_dsi_ops = {
+static const struct samsung_dsim_host_ops samsung_dsim_exynos_host_ops = {
 	.attach = exynos_dsi_host_attach,
 	.detach = exynos_dsi_host_detach,
-	.transfer = exynos_dsi_host_transfer,
 };
 
-static int exynos_dsi_of_read_u32(const struct device_node *np,
-				  const char *propname, u32 *out_value)
-{
-	int ret = of_property_read_u32(np, propname, out_value);
-
-	if (ret < 0)
-		pr_err("%pOF: failed to get '%s' property\n", np, propname);
-
-	return ret;
-}
-
-static int exynos_dsi_parse_dt(struct exynos_dsi *dsi)
-{
-	struct device *dev = dsi->dev;
-	struct device_node *node = dev->of_node;
-	int ret;
-
-	ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency",
-				     &dsi->pll_clk_rate);
-	if (ret < 0)
-		return ret;
-
-	ret = exynos_dsi_of_read_u32(node, "samsung,burst-clock-frequency",
-				     &dsi->burst_clk_rate);
-	if (ret < 0)
-		return ret;
-
-	ret = exynos_dsi_of_read_u32(node, "samsung,esc-clock-frequency",
-				     &dsi->esc_clk_rate);
-	if (ret < 0)
-		return ret;
-
-	return 0;
-}
-
-static int exynos_dsi_bind(struct device *dev, struct device *master,
-				void *data)
+static int exynos_dsi_bind(struct device *dev, struct device *master, void *data)
 {
 	struct exynos_dsi *dsi = dev_get_drvdata(dev);
+	struct samsung_dsim *priv = dsi->priv;
 	struct drm_encoder *encoder = &dsi->encoder;
 	struct drm_device *drm_dev = data;
 	int ret;
@@ -1595,17 +162,17 @@ static int exynos_dsi_bind(struct device *dev, struct device *master,
 	if (ret < 0)
 		return ret;
 
-	return mipi_dsi_host_register(&dsi->dsi_host);
+	return mipi_dsi_host_register(&priv->dsi_host);
 }
 
-static void exynos_dsi_unbind(struct device *dev, struct device *master,
-				void *data)
+static void exynos_dsi_unbind(struct device *dev, struct device *master, void *data)
 {
 	struct exynos_dsi *dsi = dev_get_drvdata(dev);
+	struct samsung_dsim *priv = dsi->priv;
 
-	exynos_dsi_atomic_disable(&dsi->bridge, NULL);
+	priv->bridge.funcs->atomic_disable(&priv->bridge, NULL);
 
-	mipi_dsi_host_unregister(&dsi->dsi_host);
+	mipi_dsi_host_unregister(&priv->dsi_host);
 }
 
 static const struct component_ops exynos_dsi_component_ops = {
@@ -1613,192 +180,31 @@ static const struct component_ops exynos_dsi_component_ops = {
 	.unbind	= exynos_dsi_unbind,
 };
 
-static int exynos_dsi_probe(struct platform_device *pdev)
+const struct samsung_dsim_plat_data *samsung_dsim_plat_probe(struct samsung_dsim *priv)
 {
-	struct device *dev = &pdev->dev;
 	struct exynos_dsi *dsi;
-	int ret, i;
+	int ret;
 
-	dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
+	dsi = devm_kzalloc(priv->dev, sizeof(*dsi), GFP_KERNEL);
 	if (!dsi)
-		return -ENOMEM;
+		return ERR_PTR(-ENOMEM);
 
-	init_completion(&dsi->completed);
-	spin_lock_init(&dsi->transfer_lock);
-	INIT_LIST_HEAD(&dsi->transfer_list);
+	dsi->pdata.host_ops = &samsung_dsim_exynos_host_ops;
+	dsi->pdata.irq_ops = &samsung_dsim_exynos_host_irq;
+	dsi->priv = priv;
 
-	dsi->dsi_host.ops = &exynos_dsi_ops;
-	dsi->dsi_host.dev = dev;
-
-	dsi->dev = dev;
-	dsi->driver_data = of_device_get_match_data(dev);
-
-	dsi->supplies[0].supply = "vddcore";
-	dsi->supplies[1].supply = "vddio";
-	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies),
-				      dsi->supplies);
+	ret = component_add(priv->dev, &exynos_dsi_component_ops);
 	if (ret)
-		return dev_err_probe(dev, ret, "failed to get regulators\n");
-
-	dsi->clks = devm_kcalloc(dev,
-			dsi->driver_data->num_clks, sizeof(*dsi->clks),
-			GFP_KERNEL);
-	if (!dsi->clks)
-		return -ENOMEM;
-
-	for (i = 0; i < dsi->driver_data->num_clks; i++) {
-		dsi->clks[i] = devm_clk_get(dev, clk_names[i]);
-		if (IS_ERR(dsi->clks[i])) {
-			if (strcmp(clk_names[i], "sclk_mipi") == 0) {
-				dsi->clks[i] = devm_clk_get(dev,
-							OLD_SCLK_MIPI_CLK_NAME);
-				if (!IS_ERR(dsi->clks[i]))
-					continue;
-			}
-
-			dev_info(dev, "failed to get the clock: %s\n",
-					clk_names[i]);
-			return PTR_ERR(dsi->clks[i]);
-		}
-	}
-
-	dsi->reg_base = devm_platform_ioremap_resource(pdev, 0);
-	if (IS_ERR(dsi->reg_base))
-		return PTR_ERR(dsi->reg_base);
+		return ERR_PTR(ret);
 
-	dsi->phy = devm_phy_get(dev, "dsim");
-	if (IS_ERR(dsi->phy)) {
-		dev_info(dev, "failed to get dsim phy\n");
-		return PTR_ERR(dsi->phy);
-	}
-
-	dsi->irq = platform_get_irq(pdev, 0);
-	if (dsi->irq < 0)
-		return dsi->irq;
-
-	ret = devm_request_threaded_irq(dev, dsi->irq, NULL,
-					exynos_dsi_irq,
-					IRQF_ONESHOT | IRQF_NO_AUTOEN,
-					dev_name(dev), dsi);
-	if (ret) {
-		dev_err(dev, "failed to request dsi irq\n");
-		return ret;
-	}
-
-	ret = exynos_dsi_parse_dt(dsi);
-	if (ret)
-		return ret;
-
-	platform_set_drvdata(pdev, dsi);
-
-	pm_runtime_enable(dev);
-
-	dsi->bridge.funcs = &exynos_dsi_bridge_funcs;
-	dsi->bridge.of_node = dev->of_node;
-	dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
-
-	ret = component_add(dev, &exynos_dsi_component_ops);
-	if (ret)
-		goto err_disable_runtime;
-
-	return 0;
-
-err_disable_runtime:
-	pm_runtime_disable(dev);
-
-	return ret;
-}
-
-static int exynos_dsi_remove(struct platform_device *pdev)
-{
-	pm_runtime_disable(&pdev->dev);
-
-	component_del(&pdev->dev, &exynos_dsi_component_ops);
-
-	return 0;
-}
-
-static int __maybe_unused exynos_dsi_suspend(struct device *dev)
-{
-	struct exynos_dsi *dsi = dev_get_drvdata(dev);
-	const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
-	int ret, i;
-
-	usleep_range(10000, 20000);
-
-	if (dsi->state & DSIM_STATE_INITIALIZED) {
-		dsi->state &= ~DSIM_STATE_INITIALIZED;
-
-		exynos_dsi_disable_clock(dsi);
-
-		exynos_dsi_disable_irq(dsi);
-	}
-
-	dsi->state &= ~DSIM_STATE_CMD_LPM;
-
-	phy_power_off(dsi->phy);
-
-	for (i = driver_data->num_clks - 1; i > -1; i--)
-		clk_disable_unprepare(dsi->clks[i]);
-
-	ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
-	if (ret < 0)
-		dev_err(dsi->dev, "cannot disable regulators %d\n", ret);
-
-	return 0;
+	return &dsi->pdata;
 }
 
-static int __maybe_unused exynos_dsi_resume(struct device *dev)
+void samsung_dsim_plat_remove(struct samsung_dsim *priv)
 {
-	struct exynos_dsi *dsi = dev_get_drvdata(dev);
-	const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
-	int ret, i;
-
-	ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
-	if (ret < 0) {
-		dev_err(dsi->dev, "cannot enable regulators %d\n", ret);
-		return ret;
-	}
-
-	for (i = 0; i < driver_data->num_clks; i++) {
-		ret = clk_prepare_enable(dsi->clks[i]);
-		if (ret < 0)
-			goto err_clk;
-	}
-
-	ret = phy_power_on(dsi->phy);
-	if (ret < 0) {
-		dev_err(dsi->dev, "cannot enable phy %d\n", ret);
-		goto err_clk;
-	}
-
-	return 0;
-
-err_clk:
-	while (--i > -1)
-		clk_disable_unprepare(dsi->clks[i]);
-	regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
-
-	return ret;
+	component_del(priv->dev, &exynos_dsi_component_ops);
 }
 
-static const struct dev_pm_ops exynos_dsi_pm_ops = {
-	SET_RUNTIME_PM_OPS(exynos_dsi_suspend, exynos_dsi_resume, NULL)
-	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
-				pm_runtime_force_resume)
-};
-
-struct platform_driver dsi_driver = {
-	.probe = exynos_dsi_probe,
-	.remove = exynos_dsi_remove,
-	.driver = {
-		   .name = "exynos-dsi",
-		   .owner = THIS_MODULE,
-		   .pm = &exynos_dsi_pm_ops,
-		   .of_match_table = exynos_dsi_of_match,
-	},
-};
-
 MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>");
 MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>");
 MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master");
diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung-dsim.h
new file mode 100644
index 000000000000..59a43f9c4477
--- /dev/null
+++ b/include/drm/bridge/samsung-dsim.h
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 Amarula Solutions(India)
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#ifndef __SAMSUNG_DSIM__
+#define __SAMSUNG_DSIM__
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_of.h>
+#include <drm/drm_mipi_dsi.h>
+
+#define DSIM_STATE_ENABLED		BIT(0)
+#define DSIM_STATE_INITIALIZED		BIT(1)
+#define DSIM_STATE_CMD_LPM		BIT(2)
+#define DSIM_STATE_VIDOUT_AVAILABLE	BIT(3)
+
+struct samsung_dsim_transfer {
+	struct list_head list;
+	struct completion completed;
+	int result;
+	struct mipi_dsi_packet packet;
+	u16 flags;
+	u16 tx_done;
+
+	u8 *rx_payload;
+	u16 rx_len;
+	u16 rx_done;
+};
+
+struct samsung_dsim_driver_data {
+	const unsigned int *reg_ofs;
+	unsigned int plltmr_reg;
+	unsigned int has_freqband:1;
+	unsigned int has_clklane_stop:1;
+	unsigned int num_clks;
+	unsigned int max_freq;
+	unsigned int wait_for_reset;
+	unsigned int num_bits_resol;
+	const unsigned int *reg_values;
+};
+
+struct samsung_dsim_host_ops {
+	int (*attach)(void *priv, struct mipi_dsi_device *device);
+	int (*detach)(void *priv, struct mipi_dsi_device *device);
+};
+
+struct samsung_dsim_irq_ops {
+	void (*enable)(void *priv);
+	void (*disable)(void *priv);
+};
+
+struct samsung_dsim_plat_data {
+	const struct samsung_dsim_host_ops *host_ops;
+	const struct samsung_dsim_irq_ops *irq_ops;
+
+	void *priv;
+};
+
+struct samsung_dsim {
+	struct mipi_dsi_host dsi_host;
+	struct drm_bridge bridge;
+	struct drm_bridge *out_bridge;
+	struct device *dev;
+	struct drm_display_mode mode;
+
+	void __iomem *reg_base;
+	struct phy *phy;
+	struct clk **clks;
+	struct regulator_bulk_data supplies[2];
+	int irq;
+
+	u32 pll_clk_rate;
+	u32 burst_clk_rate;
+	u32 esc_clk_rate;
+	u32 lanes;
+	u32 mode_flags;
+	u32 format;
+
+	int state;
+	struct drm_property *brightness;
+	struct completion completed;
+
+	spinlock_t transfer_lock; /* protects transfer_list */
+	struct list_head transfer_list;
+
+	const struct samsung_dsim_driver_data *driver_data;
+	const struct samsung_dsim_plat_data *plat_data;
+};
+
+const struct samsung_dsim_plat_data *samsung_dsim_plat_probe(struct samsung_dsim *priv);
+void samsung_dsim_plat_remove(struct samsung_dsim *priv);
+
+#endif /* __SAMSUNG_DSIM__ */

From patchwork Fri Apr  8 16:20:59 2022
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
X-Patchwork-Submitter: Jagan Teki <jagan@amarulasolutions.com>
X-Patchwork-Id: 1903
Return-Path: 
 <linux-amarula+bncBD7MFH7A7EEBBQWCYGJAMGQEMOXAQAI@amarulasolutions.com>
X-Original-To: linux-amarula@patchwork.amarulasolutions.com
Delivered-To: linux-amarula@patchwork.amarulasolutions.com
Received: from mail-pf1-f198.google.com (mail-pf1-f198.google.com
	[209.85.210.198])
	by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 569373F066
	for <linux-amarula@patchwork.amarulasolutions.com>;
	Fri,  8 Apr 2022 18:22:27 +0200 (CEST)
Received: by mail-pf1-f198.google.com with SMTP id
	y37-20020a056a001ca500b004fe3eccd4e4sf5399189pfw.16
	for <linux-amarula@patchwork.amarulasolutions.com>;
	Fri, 08 Apr 2022 09:22:27 -0700 (PDT)
ARC-Seal: i=2; a=rsa-sha256; t=1649434946; cv=pass;
	d=google.com; s=arc-20160816;
	b=zvLnarKqAGIS8uFLxvt9kPvVjvgQ3KWXhfis8MCsAk9eSNRHFQyJs8jE+71255HTCE
	s5/ffX00RZygjlqRbIq7ba+2mQXZ5aq1pWn7M2qa0FMBoDjVDjuL79B8F0uXnvY++2na
	/jzW95xQsVEE4+kD2n2BYFpsZHPK5SkSv9TL3n4YDXTJUUMJz/Tn9FXJCwT8kymwzylg
	D3pX5MrzZjO7cW8eEU8/6jrBNn1KpWlLWF9yMJzQx2jZ/rU03eHqVszFu8l8hLFflq61
	rt3edzTrR7XZTvWCGm6YkWajWB4rLtzliIYWpC4toIgYsOzH56kzq7hXDQ/KRya8t7QX
	8wxw==
ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com;
	s=arc-20160816;
	h=list-unsubscribe:list-archive:list-help:list-post:list-id
	:mailing-list:precedence:mime-version:references:in-reply-to
	:message-id:date:subject:cc:to:from:dkim-signature;
	bh=k0HQsEDABWBBswInwDqoLlEV174g3hE+mgMyX+w8Y/U=;
	b=UhDD5UEc2Ui8Ekxptrg4Fs5xUTmZuzYy1U5dN3fkyutAa5oTQuB4/wLG/eRCvrtgUc
	pF3s3QaaofMG06eX9r8s0MqPKUvb8p4XCwGlXiGlq/L4ro29mXN31viCi3aD2PA+Gwt+
	vzo/1pZi4nl3uuxwUbkL74ZgiJjsxsvPk+rFntrPKpa57V3I58Uck0Y954/h+NbbxIId
	F0fqaBVm9akyrsNeu8X+o3tjPzc7Nn6G18Z8PEBOflbIufD/FB6YIqtBcL9mFlqss6fj
	Jw0WAcDxw8kvnmjf5GRRZCV5drdFC6S8IoaHGPsfkOnL3qM26BC24QmfxYVPCuwWdsz/
	4CFA==
ARC-Authentication-Results: i=2; mx.google.com;
	dkim=pass header.i=@amarulasolutions.com header.s=google
	header.b=aBaLEom+;
	spf=pass (google.com: domain of jagan@amarulasolutions.com designates
	209.85.220.41 as permitted sender)
	smtp.mailfrom=jagan@amarulasolutions.com;
	dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
	d=amarulasolutions.com; s=google;
	h=from:to:cc:subject:date:message-id:in-reply-to:references
	:mime-version:x-original-sender:x-original-authentication-results
	:precedence:mailing-list:list-id:list-post:list-help:list-archive
	:list-unsubscribe;
	bh=k0HQsEDABWBBswInwDqoLlEV174g3hE+mgMyX+w8Y/U=;
	b=UoJBkG9gcQqhnc8HqmfklKGamgjN9Zlw5/PQ71o/PVzVHHFJtgwdlscFdUOpvOR1h+
	+sioTMsdGnWfIqAbgFL7qSm/zlwKjz1GflUURMYLuG/nRLA6u7aYufkxqygFXDk+J5ix
	AsMzJoOds7oAvBXQqHJULTFcVMhmcOq7ob43E=
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
	d=1e100.net; s=20210112;
	h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to
	:references:mime-version:x-original-sender
	:x-original-authentication-results:precedence:mailing-list:list-id
	:x-spam-checked-in-group:list-post:list-help:list-archive
	:list-unsubscribe;
	bh=k0HQsEDABWBBswInwDqoLlEV174g3hE+mgMyX+w8Y/U=;
	b=ChjuodLeh4NPm+XCTLC6Qk82A4tPJouLGWQFwpa5rLExffM5MP//BW6J7y4cj7CGbN
	DWv0ihE4bjN6NwcihfSrD2tf6OztAbKznvZdoNI8nH8Lyzt8K7LsuIBoifjwe5Fy/ip5
	/mdIaW/DByOMetLgZOYzEUHYEgOjI5esBVCWLu4ZB5dg5rqSHKrMKUeMvlY0UXGzjCsp
	7ncT6Vt2w3UQBArUbIvtIlE6IK6A1YZyDruVdz86J7fenC5iyCxYA7oj30JXjOUvAdA6
	nSXXz50CnNkwKx22fU84+DPnznVK/9yNeoTx4IwlSEzocWk7Nd1l1UD3+bXovKPlkWHw
	M/KQ==
X-Gm-Message-State: AOAM530i7szbOJqJ+Jpaad5QbTqH1Oar1+V9z0QV2c6+Z043b8JaMMCz
	oQA+IFBSO0ihpPuUfbXzqU5sXCYC
X-Google-Smtp-Source: 
 ABdhPJy688hb8gftmQm2lCUstxfEVUjVQOhk/pzdLxJqQgLj9PD9bu0CHVwf8FEM7fM/ApRQi9JOtA==
X-Received: by 2002:a05:6a00:1506:b0:4fb:2d19:b6ab with SMTP id
	q6-20020a056a00150600b004fb2d19b6abmr20273138pfu.86.1649434946142;
	Fri, 08 Apr 2022 09:22:26 -0700 (PDT)
X-BeenThere: linux-amarula@amarulasolutions.com
Received: by 2002:a17:90a:3fcc:b0:1ca:3b18:c791 with SMTP id
	u12-20020a17090a3fcc00b001ca3b18c791ls2106295pjm.2.gmail;
	Fri, 08 Apr 2022 09:22:25 -0700 (PDT)
X-Received: by 2002:a17:90b:38c7:b0:1c7:6afb:fac6 with SMTP id
	nn7-20020a17090b38c700b001c76afbfac6mr22590703pjb.198.1649434945401;
	Fri, 08 Apr 2022 09:22:25 -0700 (PDT)
ARC-Seal: i=1; a=rsa-sha256; t=1649434945; cv=none;
	d=google.com; s=arc-20160816;
	b=CLKk21gvnCxrpRbt8cyOYXoN/3KPz6D3nkcis5obVP3gAY986x0pVmNXtxGx143Dt2
	il+IOtNBRA4ZFGFwBCwvrAYCcS8XgPBKjRRvwkyk5D6QKb7jY+WzSYZGA5s+tkrMl0xa
	yIkuU7A05+1U1NGVLzt/b3nVIatVk6zxPm8ThiSu5Wo1p8TiN5l3DmeWppUn7bvAkAhR
	0U7x9LtRMeJmW/6h8FKJNra/0Nio2qvX7MFiGgvVjVDQdeUPEsCZoDJ7cNt+t/4NQiAF
	9W3iS1mmOMlNJrdZD1jqFKDs3oF4S2mvbGilofuwsyzH9QtSLE1aakJlYVYYag6A/9s5
	5ynQ==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com;
	s=arc-20160816;
	h=content-transfer-encoding:mime-version:references:in-reply-to
	:message-id:date:subject:cc:to:from:dkim-signature;
	bh=F25FQfPSS7j5Jl6aKgoVhvmm2u3Vlj8tvVo3HS+kjyo=;
	b=ZyvEAWECdsANumw8A7Oub+UQkI8c4A4VpHSQtXY0eelA2pLqUTdeTknAiz3waRkk17
	SGo9ieZmwoKM1m1YzpM5O0vXxD6xTYRoWjoGLIQC43o+KH36x8g7Xu4j3A/ennlaW8oD
	8OsDlsX9oJOPoRvgM7MoDpP1VPgOgpeyTNpVZEDPvRjkqRSVQd0PXUY+A8T8FsJkTheJ
	OKcFPp83QL+4/cTufPe315czytQ5vw3wSKKfMvM6+5lXDTag2J/ZwmbisnIYlXylcSwD
	ls7xhyweRhbUe2G3oSdmHtn5oSt6c38qSsygdiL4OgWLUC73EEQbL/Xa7lsuikGiau7d
	RiWA==
ARC-Authentication-Results: i=1; mx.google.com;
	dkim=pass header.i=@amarulasolutions.com header.s=google
	header.b=aBaLEom+;
	spf=pass (google.com: domain of jagan@amarulasolutions.com designates
	209.85.220.41 as permitted sender)
	smtp.mailfrom=jagan@amarulasolutions.com;
	dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com
Received: from mail-sor-f41.google.com (mail-sor-f41.google.com.
	[209.85.220.41]) by mx.google.com with SMTPS id
	a11-20020a170902b58b00b00156bb47295bsor741718pls.56.2022.04.08.09.22.25
	for <linux-amarula@amarulasolutions.com>
	(Google Transport Security); Fri, 08 Apr 2022 09:22:25 -0700 (PDT)
Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com
	designates 209.85.220.41 as permitted sender)
	client-ip=209.85.220.41;
X-Received: by 2002:a17:902:6acc:b0:149:8f60:a526 with SMTP id
	i12-20020a1709026acc00b001498f60a526mr20139884plt.25.1649434945090;
	Fri, 08 Apr 2022 09:22:25 -0700 (PDT)
Received: from j-ThinkPad-E14-Gen-2.domain.name ([45.249.78.214])
	by smtp.gmail.com with ESMTPSA id
	n18-20020a056a0007d200b004fdac35672fsm24929863pfu.68.2022.04.08.09.22.17
	(version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);
	Fri, 08 Apr 2022 09:22:24 -0700 (PDT)
From: Jagan Teki <jagan@amarulasolutions.com>
To: Andrzej Hajda <andrzej.hajda@intel.com>, Inki Dae <inki.dae@samsung.com>,
	Marek Szyprowski <m.szyprowski@samsung.com>,
	Joonyoung Shim <jy0922.shim@samsung.com>,
	Seung-Woo Kim <sw0312.kim@samsung.com>,
	Kyungmin Park <kyungmin.park@samsung.com>,
	Frieder Schrempf <frieder.schrempf@kontron.de>,
	Fancy Fang <chen.fang@nxp.com>, Tim Harvey <tharvey@gateworks.com>,
	Michael Nazzareno Trimarchi <michael@amarulasolutions.com>,
	Adam Ford <aford173@gmail.com>, Neil Armstrong <narmstrong@baylibre.com>,
	Robert Foss <robert.foss@linaro.org>,
	Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
	Rob Herring <robh+dt@kernel.org>
Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
	linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	NXP Linux Team <linux-imx@nxp.com>,
	linux-amarula <linux-amarula@amarulasolutions.com>,
	Jagan Teki <jagan@amarulasolutions.com>
Subject: [PATCH 02/11] drm: bridge: samsung-dsim: Handle platform init via
	driver_data
Date: Fri,  8 Apr 2022 21:50:59 +0530
Message-Id: <20220408162108.184583-3-jagan@amarulasolutions.com>
X-Mailer: git-send-email 2.25.1
In-Reply-To: <20220408162108.184583-1-jagan@amarulasolutions.com>
References: <20220408162108.184583-1-jagan@amarulasolutions.com>
MIME-Version: 1.0
X-Original-Sender: jagan@amarulasolutions.com
X-Original-Authentication-Results: mx.google.com;       dkim=pass
	header.i=@amarulasolutions.com header.s=google header.b=aBaLEom+;
	spf=pass (google.com: domain of jagan@amarulasolutions.com designates
	209.85.220.41 as permitted sender)
	smtp.mailfrom=jagan@amarulasolutions.com;
	dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com
Content-Type: text/plain; charset="UTF-8"
Precedence: list
Mailing-list: list linux-amarula@amarulasolutions.com;
	contact linux-amarula+owners@amarulasolutions.com
List-ID: <linux-amarula.amarulasolutions.com>
X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com
X-Google-Group-Id: 476853432473
List-Post: 
 <https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/post>,
	<mailto:linux-amarula@amarulasolutions.com>
List-Help: 
 <https://support.google.com/a/amarulasolutions.com/bin/topic.py?topic=25838>,
	<mailto:linux-amarula+help@amarulasolutions.com>
List-Archive: 
 <https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/>
List-Unsubscribe: 
 <mailto:googlegroups-manage+476853432473+unsubscribe@googlegroups.com>,
	<https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/subscribe>

In order to make a common Samsung DSIM bridge driver some platform specific
glue code needs to maintain separately as it is hard to maintain platform
specific glue and conventional component_ops on the drm bridge drivers side.

This patch is trying to support that glue code initialization and invocation
in the form of platform_init flag in driver_data.

So, the platforms which enable platform_init flags will handle all platform
specific initialization via samsung_dsim_plat_probe.

The Platform probe is responsible to
- initialize samsung_dsim_plat_data and install hooks
- initialize component_ops
- preserve samsung_dsim structure pointer

v1:
* use platform_init instead of exynos_specific
* handle component_ops in glue code

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/gpu/drm/bridge/samsung-dsim.c | 20 ++++++++++++++++----
 include/drm/bridge/samsung-dsim.h     |  1 +
 2 files changed, 17 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index ee5d7e5518a6..0e6a5d1c7e4e 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -370,6 +370,7 @@ static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = {
 	.wait_for_reset = 1,
 	.num_bits_resol = 11,
 	.reg_values = reg_values,
+	.platform_init = true,
 };
 
 static const struct samsung_dsim_driver_data exynos4_dsi_driver_data = {
@@ -382,6 +383,7 @@ static const struct samsung_dsim_driver_data exynos4_dsi_driver_data = {
 	.wait_for_reset = 1,
 	.num_bits_resol = 11,
 	.reg_values = reg_values,
+	.platform_init = true,
 };
 
 static const struct samsung_dsim_driver_data exynos5_dsi_driver_data = {
@@ -392,6 +394,7 @@ static const struct samsung_dsim_driver_data exynos5_dsi_driver_data = {
 	.wait_for_reset = 1,
 	.num_bits_resol = 11,
 	.reg_values = reg_values,
+	.platform_init = true,
 };
 
 static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = {
@@ -403,6 +406,7 @@ static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = {
 	.wait_for_reset = 0,
 	.num_bits_resol = 12,
 	.reg_values = exynos5433_reg_values,
+	.platform_init = true,
 };
 
 static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = {
@@ -414,6 +418,7 @@ static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = {
 	.wait_for_reset = 1,
 	.num_bits_resol = 12,
 	.reg_values = exynos5422_reg_values,
+	.platform_init = true,
 };
 
 static const struct of_device_id samsung_dsim_of_match[] = {
@@ -1565,12 +1570,16 @@ static int samsung_dsim_probe(struct platform_device *pdev)
 	dsi->bridge.of_node = dev->of_node;
 	dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
 
-	dsi->plat_data = samsung_dsim_plat_probe(dsi);
-	if (IS_ERR(dsi->plat_data)) {
+	if (dsi->driver_data->platform_init) {
+		dsi->plat_data = samsung_dsim_plat_probe(dsi);
 		ret = PTR_ERR(dsi->plat_data);
-		goto err_disable_runtime;
+	} else {
+		ret = mipi_dsi_host_register(&dsi->dsi_host);
 	}
 
+	if (ret)
+		goto err_disable_runtime;
+
 	return 0;
 
 err_disable_runtime:
@@ -1585,7 +1594,10 @@ static int samsung_dsim_remove(struct platform_device *pdev)
 
 	pm_runtime_disable(&pdev->dev);
 
-	samsung_dsim_plat_remove(dsi);
+	if (dsi->driver_data->platform_init)
+		samsung_dsim_plat_remove(dsi);
+	else
+		mipi_dsi_host_unregister(&dsi->dsi_host);
 
 	return 0;
 }
diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung-dsim.h
index 59a43f9c4477..eca7eacb5910 100644
--- a/include/drm/bridge/samsung-dsim.h
+++ b/include/drm/bridge/samsung-dsim.h
@@ -39,6 +39,7 @@ struct samsung_dsim_driver_data {
 	unsigned int wait_for_reset;
 	unsigned int num_bits_resol;
 	const unsigned int *reg_values;
+	bool platform_init;
 };
 
 struct samsung_dsim_host_ops {

From patchwork Fri Apr  8 16:21:00 2022
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
X-Patchwork-Submitter: Jagan Teki <jagan@amarulasolutions.com>
X-Patchwork-Id: 1904
Return-Path: 
 <linux-amarula+bncBD7MFH7A7EEBBSWCYGJAMGQEKFB3PWY@amarulasolutions.com>
X-Original-To: linux-amarula@patchwork.amarulasolutions.com
Delivered-To: linux-amarula@patchwork.amarulasolutions.com
Received: from mail-pf1-f197.google.com (mail-pf1-f197.google.com
	[209.85.210.197])
	by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 389AB3F066
	for <linux-amarula@patchwork.amarulasolutions.com>;
	Fri,  8 Apr 2022 18:22:35 +0200 (CEST)
Received: by mail-pf1-f197.google.com with SMTP id
	d5-20020a62f805000000b0050566b4f4c0sf3229440pfh.11
	for <linux-amarula@patchwork.amarulasolutions.com>;
	Fri, 08 Apr 2022 09:22:35 -0700 (PDT)
ARC-Seal: i=2; a=rsa-sha256; t=1649434954; cv=pass;
	d=google.com; s=arc-20160816;
	b=uUIjLfIJCL7XLdOyvuSLCHSE2WYsr09lbVB4yFW8oP+Cm2kssOurgzrM9RIpKvlgto
	FfuIW6tIYLjTAkt1Ob+Isj5en69ni6FxpY+epo7/h2FXglx9rbjUPbVNAaAKptMXlFeW
	H/6mh5L4JTZdNOXbsTEIo+Kht3/5Yg/fR8MXySOgXsRhn80Aas08W3yjggldeRV222hY
	aUvQoj1Uv9a4XJ4EaUsyqq5zsmtE7gWTwvxAv5PPZse1qjAnZjoRXI91jfmS8YlA/MkX
	9btckEb7aFEOufN0OPYZD+5JzHqZAZZ0bswGf3ro9gK6ctkN4CA936P05FKjiee8hg0y
	OJZg==
ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com;
	s=arc-20160816;
	h=list-unsubscribe:list-archive:list-help:list-post:list-id
	:mailing-list:precedence:content-transfer-encoding:mime-version
	:references:in-reply-to:message-id:date:subject:cc:to:from
	:dkim-signature;
	bh=9swllQH3h1cV+oa2ojw1TfVC5g+dNgXrOxvYSgz/GhI=;
	b=sCEwtadOET3cnJ6VPAqEOSwbOput16p5iv4NM8/p6VyceQpRCh7AUAGQ+R7QK2p0JN
	OeSASyDauZuuoL86FjpiImVdJvGDzEPVR2CZyHr/60e2MrPKk2VDCK38UoftaeNTceot
	wibW/BjlsTAQMdTplmEGrycbd9GzAXwJcDrHn+fm0utqBxXs14tm9QPiNmh2MBglpNnN
	Oxp4A05onMDD8jCzhD8jB1C87CvPd6UAIKt3ULPnCB4KjehRb5AqQye3afeCmaL+5C9y
	R2dJS8i8dFOJ5jcmnYZZbTiWszITQ7kCC5O1sBTCIy83XIIMW2NLO68mAx80Q5Y/Us/G
	8MUg==
ARC-Authentication-Results: i=2; mx.google.com;
	dkim=pass header.i=@amarulasolutions.com header.s=google
	header.b=cEAopD5V;
	spf=pass (google.com: domain of jagan@amarulasolutions.com designates
	209.85.220.41 as permitted sender)
	smtp.mailfrom=jagan@amarulasolutions.com;
	dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
	d=amarulasolutions.com; s=google;
	h=from:to:cc:subject:date:message-id:in-reply-to:references
	:mime-version:content-transfer-encoding:x-original-sender
	:x-original-authentication-results:precedence:mailing-list:list-id
	:list-post:list-help:list-archive:list-unsubscribe;
	bh=9swllQH3h1cV+oa2ojw1TfVC5g+dNgXrOxvYSgz/GhI=;
	b=eSGLXK6Zw7X2uJpCb92lEPbmvjbutN2ZOACJ58wTlyoEFePj4LXJ+H42T7+C9Snujh
	cy9JGnlWsQNfvVCx8Kw2nTM+Uj2cBFPsYB/TqiLqGoq/3S13OegsblT3gorQoNrXWGTL
	wF27pOYXHH/bsWMK9byUPYbehDGHLWVlH7q7g=
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
	d=1e100.net; s=20210112;
	h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to
	:references:mime-version:content-transfer-encoding:x-original-sender
	:x-original-authentication-results:precedence:mailing-list:list-id
	:x-spam-checked-in-group:list-post:list-help:list-archive
	:list-unsubscribe;
	bh=9swllQH3h1cV+oa2ojw1TfVC5g+dNgXrOxvYSgz/GhI=;
	b=02wy91T699gKrcZhU4YiaxbiNZcb7m5zVR/hjMYbd1/WgYRfZA9tdEmS2SHO9hX5DM
	GuMuJJChL6Ncbrg298wiB4E3Lf9FOBwrlolIA7mP/YSdnoj/U2BsZvbdEMXNvskrefWS
	RkZpoylkKrAqEGuvCkzVcSP+AJiHWU97ZIJrb4oGklNSNKdV4gL1uymChGnVC15G2dDN
	v/ge9hLfKe+HQBGcPn8cP7NgYHUzRHDeoKTD8dRnmpRz/8q9RQhTwEc2c25SyeGl82/t
	VN744XZR4ysrbi8Rdr0Bn+Bol6R5N69xCJuXLs6JnmcSvf0yX4vMRSX6YPOYEtt4ICX3
	tTyw==
X-Gm-Message-State: AOAM532nnunTX7vVfqzs0fAUSeLIN3JKbQ/cq2Fy+o/hXkTZ8BIxxNW7
	uetmOwnMHr1ZDtH5EPJqsgfME7rr
X-Google-Smtp-Source: 
 ABdhPJxVIQwlbWuKF0x9rdtGKBbvD5adgaVQA6izqelfStvwT6/n2A0Vw5z1LiE7NWbFHLTxeU3SfQ==
X-Received: by 2002:a17:90b:38cf:b0:1c9:c3e3:817 with SMTP id
	nn15-20020a17090b38cf00b001c9c3e30817mr22938687pjb.73.1649434954089;
	Fri, 08 Apr 2022 09:22:34 -0700 (PDT)
X-BeenThere: linux-amarula@amarulasolutions.com
Received: by 2002:a17:902:d2cb:b0:156:b391:3ccb with SMTP id
	n11-20020a170902d2cb00b00156b3913ccbls2230625plc.0.gmail;
	Fri, 08 Apr 2022 09:22:33 -0700 (PDT)
X-Received: by 2002:a17:90b:1d84:b0:1c7:880b:9efc with SMTP id
	pf4-20020a17090b1d8400b001c7880b9efcmr22352962pjb.90.1649434953377;
	Fri, 08 Apr 2022 09:22:33 -0700 (PDT)
ARC-Seal: i=1; a=rsa-sha256; t=1649434953; cv=none;
	d=google.com; s=arc-20160816;
	b=I9TpCuISvEt43EDlaLGBwhc8UngCXEqqRhNvWNN1mtgX41ZwHMs7Oj2wpMhywLGq/+
	VyZ1qHxQlJrdEuaaYfIj9mCfcbQvGCrbioJ5xqLryz0RrCF9V5IY9d7OSctsUDteBKKn
	/So0D2MIcm6YjUfpJmHmcZm8tH++TXrQegbLns4h3NvftD7np0NWfE6PKg39XRppdUsS
	c5WY8kmzOjlfleXCTsnNW+2T5cy7deBcXXZ6IHLt6t1FNN594LpcAM843swZqhcgqv3P
	YKDHHtTTHS1AxxCrnjnY/HoYuGvQmvMyl30amre1MK5z9Y8t+2M1GxuBrJCFX80sz0lq
	6smg==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com;
	s=arc-20160816;
	h=content-transfer-encoding:mime-version:references:in-reply-to
	:message-id:date:subject:cc:to:from:dkim-signature;
	bh=gGzzNcZY8RobibNWD65GpD1P4b/cN9VaV+JKjs3w2tM=;
	b=jZ1eA7h0aMwGqlqnDwBIAB1vvgtQZLNyPQobgU7IZ+mDS7AJ/KxG9aqdoQLBJ159Tq
	UqdTuHrg7l8UrK0LJ4j8eSfYm6TA52g0E7OS180ksCvqIbDbkDdxeNNm0o5kZyMtNflA
	rqKR2dIUUqgpU+Pcw8hPW0pj+mMTfOPSrYD2RYs5D3DQn76fh5r3U/6jEz9XoAQMJPLu
	PAZpkFpeAWNf2n3AxEE+npLsFflO5FZPaT/8SU9enY1Sx1tb8m7GtH7nS+JTW341ou+q
	9JCW6z7S5ELqmpfIx3jM3y7sa93zr7dtxC8B9pCcDfvwjj41Wwre6gVpauRWprT03HDY
	lSXA==
ARC-Authentication-Results: i=1; mx.google.com;
	dkim=pass header.i=@amarulasolutions.com header.s=google
	header.b=cEAopD5V;
	spf=pass (google.com: domain of jagan@amarulasolutions.com designates
	209.85.220.41 as permitted sender)
	smtp.mailfrom=jagan@amarulasolutions.com;
	dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com
Received: from mail-sor-f41.google.com (mail-sor-f41.google.com.
	[209.85.220.41]) by mx.google.com with SMTPS id
	bd34-20020a056a0027a200b004fa8c620561sor921273pfb.57.2022.04.08.09.22.33
	for <linux-amarula@amarulasolutions.com>
	(Google Transport Security); Fri, 08 Apr 2022 09:22:33 -0700 (PDT)
Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com
	designates 209.85.220.41 as permitted sender)
	client-ip=209.85.220.41;
X-Received: by 2002:a05:6a00:238f:b0:4f7:78b1:2f6b with SMTP id
	f15-20020a056a00238f00b004f778b12f6bmr20311000pfc.17.1649434953099;
	Fri, 08 Apr 2022 09:22:33 -0700 (PDT)
Received: from j-ThinkPad-E14-Gen-2.domain.name ([45.249.78.214])
	by smtp.gmail.com with ESMTPSA id
	n18-20020a056a0007d200b004fdac35672fsm24929863pfu.68.2022.04.08.09.22.25
	(version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);
	Fri, 08 Apr 2022 09:22:32 -0700 (PDT)
From: Jagan Teki <jagan@amarulasolutions.com>
To: Andrzej Hajda <andrzej.hajda@intel.com>, Inki Dae <inki.dae@samsung.com>,
	Marek Szyprowski <m.szyprowski@samsung.com>,
	Joonyoung Shim <jy0922.shim@samsung.com>,
	Seung-Woo Kim <sw0312.kim@samsung.com>,
	Kyungmin Park <kyungmin.park@samsung.com>,
	Frieder Schrempf <frieder.schrempf@kontron.de>,
	Fancy Fang <chen.fang@nxp.com>, Tim Harvey <tharvey@gateworks.com>,
	Michael Nazzareno Trimarchi <michael@amarulasolutions.com>,
	Adam Ford <aford173@gmail.com>, Neil Armstrong <narmstrong@baylibre.com>,
	Robert Foss <robert.foss@linaro.org>,
	Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
	Rob Herring <robh+dt@kernel.org>
Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
	linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	NXP Linux Team <linux-imx@nxp.com>,
	linux-amarula <linux-amarula@amarulasolutions.com>,
	Jagan Teki <jagan@amarulasolutions.com>
Subject: [PATCH 03/11] drm: bridge: samsung-dsim: Mark PHY as optional
Date: Fri,  8 Apr 2022 21:51:00 +0530
Message-Id: <20220408162108.184583-4-jagan@amarulasolutions.com>
X-Mailer: git-send-email 2.25.1
In-Reply-To: <20220408162108.184583-1-jagan@amarulasolutions.com>
References: <20220408162108.184583-1-jagan@amarulasolutions.com>
MIME-Version: 1.0
Content-Type: text/plain; charset="UTF-8"
X-Original-Sender: jagan@amarulasolutions.com
X-Original-Authentication-Results: mx.google.com;       dkim=pass
	header.i=@amarulasolutions.com header.s=google header.b=cEAopD5V;
	spf=pass (google.com: domain of jagan@amarulasolutions.com designates
	209.85.220.41 as permitted sender)
	smtp.mailfrom=jagan@amarulasolutions.com;
	dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com
Precedence: list
Mailing-list: list linux-amarula@amarulasolutions.com;
	contact linux-amarula+owners@amarulasolutions.com
List-ID: <linux-amarula.amarulasolutions.com>
X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com
X-Google-Group-Id: 476853432473
List-Post: 
 <https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/post>,
	<mailto:linux-amarula@amarulasolutions.com>
List-Help: 
 <https://support.google.com/a/amarulasolutions.com/bin/topic.py?topic=25838>,
	<mailto:linux-amarula+help@amarulasolutions.com>
List-Archive: 
 <https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/>
List-Unsubscribe: 
 <mailto:googlegroups-manage+476853432473+unsubscribe@googlegroups.com>,
	<https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/subscribe>

In i.MX8M Mini/Nano SoC the DSI Phy requires a MIPI DPHY bit
to reset in order to activate the PHY and that can be done via
upstream i.MX8M blk-ctrl driver.

So, mark the phy get as optional.

v1:
* new patch

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/gpu/drm/bridge/samsung-dsim.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index 0e6a5d1c7e4e..ff05c8e01cff 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -1539,7 +1539,7 @@ static int samsung_dsim_probe(struct platform_device *pdev)
 	if (IS_ERR(dsi->reg_base))
 		return PTR_ERR(dsi->reg_base);
 
-	dsi->phy = devm_phy_get(dev, "dsim");
+	dsi->phy = devm_phy_optional_get(dev, "dsim");
 	if (IS_ERR(dsi->phy)) {
 		dev_info(dev, "failed to get dsim phy\n");
 		return PTR_ERR(dsi->phy);

From patchwork Fri Apr  8 16:21:01 2022
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
X-Patchwork-Submitter: Jagan Teki <jagan@amarulasolutions.com>
X-Patchwork-Id: 1905
Return-Path: 
 <linux-amarula+bncBD7MFH7A7EEBBUWCYGJAMGQESJBHX5A@amarulasolutions.com>
X-Original-To: linux-amarula@patchwork.amarulasolutions.com
Delivered-To: linux-amarula@patchwork.amarulasolutions.com
Received: from mail-pl1-f200.google.com (mail-pl1-f200.google.com
	[209.85.214.200])
	by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 798973F066
	for <linux-amarula@patchwork.amarulasolutions.com>;
	Fri,  8 Apr 2022 18:22:43 +0200 (CEST)
Received: by mail-pl1-f200.google.com with SMTP id
	a5-20020a170902ecc500b00156762be487sf4697643plh.10
	for <linux-amarula@patchwork.amarulasolutions.com>;
	Fri, 08 Apr 2022 09:22:43 -0700 (PDT)
ARC-Seal: i=2; a=rsa-sha256; t=1649434962; cv=pass;
	d=google.com; s=arc-20160816;
	b=QR6K9I6rWy8SrEraQ/k9biYyjZRuCK2HpvOyioaDTVebmJvZa9USjQjG/Y7qpZuCHo
	hFZ68/Q5aXVkGMIiiqpqrxT3cZCTSUPUVMrvz2zvZZUR0zcEcGE3LXDEvnhksyzl5xDl
	qcvSUqBRRKuuCHP5Lw7sc0iroczRy2lhhf44lVVLmmSsBEZ5Mv3priaeJH/q5ZNF5esi
	up5vrWLZ7FyrXzmmqIbQiHb+Ov4AGe53TnAZMz+lXnoovOaF7NOjtB70PC9Pw1PaxiNf
	1Srgt1Y/3PxHf+PpO3mPzuxNc5KaJ+1YTASnhKyIKXSgNgo4VpOhpe/lX8QqVRQ/T/y3
	s23A==
ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com;
	s=arc-20160816;
	h=list-unsubscribe:list-archive:list-help:list-post:list-id
	:mailing-list:precedence:mime-version:references:in-reply-to
	:message-id:date:subject:cc:to:from:dkim-signature;
	bh=K/jM7xGdy1ItY73okRpqqBtg+Iyu2bGJE5sY+pL2zho=;
	b=l0EGNz62kLWSsgv8jbHG97BYpzemMUpU/D+VszQnMfbsejZ87aFDILtGt0WgaeO0PD
	jG6DK+xo+kbDtZOETI8m9Ys0B6UXfaFgTSI4t7fQ/ADWSnLTLw6hNFt9cruBOCIde4zH
	UaosBXLPUFdxLhh0lMGH0j71ZaCZmITjBkStRPUtOKTHwz1BoBAQkygVh+rlaSQEr+km
	3STkL4IvcI2v1sSUXk+m0JYFia1s96dsIRuVqqdQtue8b3Q/vKE9EV9CxW1FLU+R9eGy
	7lR9XXpMRuUDraWgrd5lvgzMEvfB98VuAyRaj5pCyTCBESog/flmCLVBtH1R4T/SRcmC
	f43g==
ARC-Authentication-Results: i=2; mx.google.com;
	dkim=pass header.i=@amarulasolutions.com header.s=google
	header.b="qGFgE8d/";
	spf=pass (google.com: domain of jagan@amarulasolutions.com designates
	209.85.220.41 as permitted sender)
	smtp.mailfrom=jagan@amarulasolutions.com;
	dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
	d=amarulasolutions.com; s=google;
	h=from:to:cc:subject:date:message-id:in-reply-to:references
	:mime-version:x-original-sender:x-original-authentication-results
	:precedence:mailing-list:list-id:list-post:list-help:list-archive
	:list-unsubscribe;
	bh=K/jM7xGdy1ItY73okRpqqBtg+Iyu2bGJE5sY+pL2zho=;
	b=KrNQL2B1ly8oAWdNGF8t+h99LhW0IDgraVERV+tX0Rj6tQ7xDa84ymfiHXbEQrHFn4
	19zi6tTUFf43kve7W648llvCBYAfaF9HbLjlys2mdu6AHhn6oO25ixHR2KuEGOZN8Hm4
	ayRQiX7ap/COcFyd4dR0Ce/dMEBQPddDN5qmw=
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
	d=1e100.net; s=20210112;
	h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to
	:references:mime-version:x-original-sender
	:x-original-authentication-results:precedence:mailing-list:list-id
	:x-spam-checked-in-group:list-post:list-help:list-archive
	:list-unsubscribe;
	bh=K/jM7xGdy1ItY73okRpqqBtg+Iyu2bGJE5sY+pL2zho=;
	b=7YFk7+FBPY27ylDY4uciswpuZMpTOBuAXEKh0NqXhSk2r0ZolbIooJqImP1QWqnz0z
	KUDENepBuY4C9zES2L6ohEwUnbQoTUfZjSNQuQIoZejEz576HcSMJdf4hweg6Y02r+BI
	ZEJNWwLseMzCG9HxygjrEGILfTy8xZcMzNGJKmW4Xpfk+tT56PVJzfwhlxl790NuWW66
	8cpsGY142iQpZrL1zKk/5CtLDwxDL1WeC5FpyasZYf4RPD+lFHkQ0Oa7i+Tft/Quc/2L
	5/s+jc59wXk2vt2p1TGTKdvtcIj4nPE+4T6xWE06C+pSJcNBPz1gIOXlBozErtbzAXcl
	6mog==
X-Gm-Message-State: AOAM530X3XpB/oO97+vKnqZpi1KDk5w6Kzo6KDZpQbFxknSvWEi73xpw
	7KGiowSL7F/8JGjhb+cZmR3PJP7R
X-Google-Smtp-Source: 
 ABdhPJy+72Cix8iAlIOR5U0fotAdNhxfjuPa5Qy64Y+OhF17hOmwY9en/4pnKjRc1pEjh3B0fE/E5A==
X-Received: by 2002:a05:6a00:b47:b0:4fd:a5b5:a279 with SMTP id
	p7-20020a056a000b4700b004fda5b5a279mr20369344pfo.19.1649434962207;
	Fri, 08 Apr 2022 09:22:42 -0700 (PDT)
X-BeenThere: linux-amarula@amarulasolutions.com
Received: by 2002:a05:6a00:420a:b0:4fa:f605:3bb3 with SMTP id
	cd10-20020a056a00420a00b004faf6053bb3ls1445665pfb.1.gmail;
	Fri, 08 Apr 2022 09:22:41 -0700 (PDT)
X-Received: by 2002:a62:5b44:0:b0:4fd:e026:f4ba with SMTP id
	p65-20020a625b44000000b004fde026f4bamr20300570pfb.55.1649434961423;
	Fri, 08 Apr 2022 09:22:41 -0700 (PDT)
ARC-Seal: i=1; a=rsa-sha256; t=1649434961; cv=none;
	d=google.com; s=arc-20160816;
	b=dtT71yFl/Q0VNZMhwbhXkUYYoKcETRGhG9WdOGL1nGAx1tgyvf1Z8GwTCvWfiGGVms
	tUVVgbdSqFheJYV0R+co97S37QfoBZMJvKxQSKOE6TlkMm5QSIHq3fj2vfutuVEhFP1b
	53sF8WzRU1gVE/M6SZKkAeHBmpI5YuG6G0uTQCv41rw06sxQCPVfAIWZ/PdO/JE4TlNF
	K4dgRM4IcEwbD5XtVAc+Ap3RX+VScRSqwHBcSUq16kRdOptU/mFIP1H6rkwqWHFUMF1V
	CL/oNZuczcrSh7j+fiS00hMuB3Y5Aandpvw5Mwgey4d2kbpDa/+eeQBRWe/x+NAlzQlt
	mwBQ==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com;
	s=arc-20160816;
	h=content-transfer-encoding:mime-version:references:in-reply-to
	:message-id:date:subject:cc:to:from:dkim-signature;
	bh=cgQ5H26dXpBSM4rzqEEf72CNZpQ5iTR6sOekInJL9nA=;
	b=bMjCgUxAJhocYn0s1lbA8TU1baWtDrVD+X2t69vZ0N5q6I0rCfgxKSXJu/4R/NN0L+
	H7gnuYC527HAPV1wMI++DNjQ+rIr4psjUrp4vXxcM3Khu7DvJRyqI/xeL8sjg81vMwf1
	tv2YmoSk1BYU7aB00/rVAWd5+5LRDVOUV9fMHITSOJWxuGIJ9MQgjGUcMZpG7Oussa9L
	J0mWkTZ0I4V2Fwy38MGpjIA7mB0Nlbt9b/OBiR9WY0TOWjTZ1hGxbfSZH8OKWcBkNwjh
	4SqcOuEftqo+N0JUzVO6W46RZBXvyMRwyFrK0eInlNEqymQ7iEL4rFsO7rB90gaX2x7D
	iAIg==
ARC-Authentication-Results: i=1; mx.google.com;
	dkim=pass header.i=@amarulasolutions.com header.s=google
	header.b="qGFgE8d/";
	spf=pass (google.com: domain of jagan@amarulasolutions.com designates
	209.85.220.41 as permitted sender)
	smtp.mailfrom=jagan@amarulasolutions.com;
	dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com
Received: from mail-sor-f41.google.com (mail-sor-f41.google.com.
	[209.85.220.41]) by mx.google.com with SMTPS id
	z10-20020a63190a000000b00379066bb477sor995291pgl.48.2022.04.08.09.22.41
	for <linux-amarula@amarulasolutions.com>
	(Google Transport Security); Fri, 08 Apr 2022 09:22:41 -0700 (PDT)
Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com
	designates 209.85.220.41 as permitted sender)
	client-ip=209.85.220.41;
X-Received: by 2002:a63:c00e:0:b0:398:a2b7:be6 with SMTP id
	h14-20020a63c00e000000b00398a2b70be6mr1775772pgg.214.1649434961113;
	Fri, 08 Apr 2022 09:22:41 -0700 (PDT)
Received: from j-ThinkPad-E14-Gen-2.domain.name ([45.249.78.214])
	by smtp.gmail.com with ESMTPSA id
	n18-20020a056a0007d200b004fdac35672fsm24929863pfu.68.2022.04.08.09.22.33
	(version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);
	Fri, 08 Apr 2022 09:22:40 -0700 (PDT)
From: Jagan Teki <jagan@amarulasolutions.com>
To: Andrzej Hajda <andrzej.hajda@intel.com>, Inki Dae <inki.dae@samsung.com>,
	Marek Szyprowski <m.szyprowski@samsung.com>,
	Joonyoung Shim <jy0922.shim@samsung.com>,
	Seung-Woo Kim <sw0312.kim@samsung.com>,
	Kyungmin Park <kyungmin.park@samsung.com>,
	Frieder Schrempf <frieder.schrempf@kontron.de>,
	Fancy Fang <chen.fang@nxp.com>, Tim Harvey <tharvey@gateworks.com>,
	Michael Nazzareno Trimarchi <michael@amarulasolutions.com>,
	Adam Ford <aford173@gmail.com>, Neil Armstrong <narmstrong@baylibre.com>,
	Robert Foss <robert.foss@linaro.org>,
	Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
	Rob Herring <robh+dt@kernel.org>
Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
	linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	NXP Linux Team <linux-imx@nxp.com>,
	linux-amarula <linux-amarula@amarulasolutions.com>,
	Jagan Teki <jagan@amarulasolutions.com>
Subject: [PATCH 04/11] drm: bridge: samsung-dsim: Add DSI init in bridge
	pre_enable()
Date: Fri,  8 Apr 2022 21:51:01 +0530
Message-Id: <20220408162108.184583-5-jagan@amarulasolutions.com>
X-Mailer: git-send-email 2.25.1
In-Reply-To: <20220408162108.184583-1-jagan@amarulasolutions.com>
References: <20220408162108.184583-1-jagan@amarulasolutions.com>
MIME-Version: 1.0
X-Original-Sender: jagan@amarulasolutions.com
X-Original-Authentication-Results: mx.google.com;       dkim=pass
	header.i=@amarulasolutions.com header.s=google header.b="qGFgE8d/";
	spf=pass (google.com: domain of jagan@amarulasolutions.com designates
	209.85.220.41 as permitted sender)
	smtp.mailfrom=jagan@amarulasolutions.com;
	dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com
Content-Type: text/plain; charset="UTF-8"
Precedence: list
Mailing-list: list linux-amarula@amarulasolutions.com;
	contact linux-amarula+owners@amarulasolutions.com
List-ID: <linux-amarula.amarulasolutions.com>
X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com
X-Google-Group-Id: 476853432473
List-Post: 
 <https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/post>,
	<mailto:linux-amarula@amarulasolutions.com>
List-Help: 
 <https://support.google.com/a/amarulasolutions.com/bin/topic.py?topic=25838>,
	<mailto:linux-amarula+help@amarulasolutions.com>
List-Archive: 
 <https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/>
List-Unsubscribe: 
 <mailto:googlegroups-manage+476853432473+unsubscribe@googlegroups.com>,
	<https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/subscribe>

Host transfer() in DSI master will invoke only when the DSI commands
are sent from DSI devices like DSI Panel or DSI bridges and this
host transfer wouldn't invoke for I2C-based-DSI bridge drivers.

Handling DSI host initialization in transfer calls misses the
controller setup for I2C configured DSI bridges.

This patch adds the DSI initialization from transfer to bridge
pre_enable as the bridge pre_enable API is invoked by core as
it is common across all classes of DSI device drivers.

v1:
* keep DSI init in host transfer

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/gpu/drm/bridge/samsung-dsim.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index ff05c8e01cff..3e12b469dfa8 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -1290,6 +1290,13 @@ static void samsung_dsim_atomic_pre_enable(struct drm_bridge *bridge,
 	}
 
 	dsi->state |= DSIM_STATE_ENABLED;
+
+	if (!(dsi->state & DSIM_STATE_INITIALIZED)) {
+		ret = samsung_dsim_init(dsi);
+		if (ret)
+			return;
+		dsi->state |= DSIM_STATE_INITIALIZED;
+	}
 }
 
 static void samsung_dsim_atomic_enable(struct drm_bridge *bridge,

From patchwork Fri Apr  8 16:21:02 2022
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
X-Patchwork-Submitter: Jagan Teki <jagan@amarulasolutions.com>
X-Patchwork-Id: 1906
Return-Path: 
 <linux-amarula+bncBD7MFH7A7EEBBWOCYGJAMGQE6NTKHYA@amarulasolutions.com>
X-Original-To: linux-amarula@patchwork.amarulasolutions.com
Delivered-To: linux-amarula@patchwork.amarulasolutions.com
Received: from mail-pf1-f198.google.com (mail-pf1-f198.google.com
	[209.85.210.198])
	by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 454533F066
	for <linux-amarula@patchwork.amarulasolutions.com>;
	Fri,  8 Apr 2022 18:22:51 +0200 (CEST)
Received: by mail-pf1-f198.google.com with SMTP id
	h131-20020a628389000000b005056723a9dcsf3170049pfe.8
	for <linux-amarula@patchwork.amarulasolutions.com>;
	Fri, 08 Apr 2022 09:22:51 -0700 (PDT)
ARC-Seal: i=2; a=rsa-sha256; t=1649434970; cv=pass;
	d=google.com; s=arc-20160816;
	b=FM8D8lAzZpcHP35HCyDu5zWDh6ChcT+8Yl31lz7UoyCYFhiBJ0jfdjVzB697N+Xk/D
	S7GNC1SKb6P+8r3p9xbX8t+/GIhY0k8LemsN12c8ag3ISctega/Y6kN0EcEsKFAJ9P1x
	EcAwBmKrY+cuHcYccZjIqN6+qFz5vxh5+SLV8lG2N+GsjVbyAhLc5y6kDHYhRLPKX8ri
	U+f/MvSRbnSMJctE5pnGSPpPwyzyhbBuxyYpYyB4+90dV82ht5CAmATo4Wx0mE8NZDzP
	q9lqxXHx5kRYW+tM5LrTl7QwuPq7TDFCyUQZ5CtBcjKKxurHhkv+iknTVTiLzUbp7GTP
	aPCg==
ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com;
	s=arc-20160816;
	h=list-unsubscribe:list-archive:list-help:list-post:list-id
	:mailing-list:precedence:mime-version:references:in-reply-to
	:message-id:date:subject:cc:to:from:dkim-signature;
	bh=RFIv6t6uU6/28kHtc1+PyuYkIslPcgmBDtw7hOdcXhI=;
	b=SaPMTYloU4999uUw/0L71GeUxiy2TwhMBgxw/JCOftgjCHL1hZ41U93k4LBRfg1RiE
	SrC8DcUXg0FgOTqx+AOQVqJh5p4pAJjr9snJtN7op5tO5R7wdt7hT2frdPwI9fa8yQK6
	5w5JyBizjd17Q9UHNxvnzoXlNg41Fa6X9EClAsw0j75sdmsgU4tblZMGeL8ev3OlIFUK
	pyNpKwcRAiXBp3btWrsfnKF8SZObhK5JWh5W4sYl0500iTwZblJzMQHxY8t/dZQrD+CO
	PmBvKghkbu4utByrOAq4h47QllKtBu7mmoUl9dJ3Td8Y0RdWApbcf9UnUmNa0nqI29ER
	G9JA==
ARC-Authentication-Results: i=2; mx.google.com;
	dkim=pass header.i=@amarulasolutions.com header.s=google
	header.b=VjoSi9WU;
	spf=pass (google.com: domain of jagan@amarulasolutions.com designates
	209.85.220.41 as permitted sender)
	smtp.mailfrom=jagan@amarulasolutions.com;
	dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
	d=amarulasolutions.com; s=google;
	h=from:to:cc:subject:date:message-id:in-reply-to:references
	:mime-version:x-original-sender:x-original-authentication-results
	:precedence:mailing-list:list-id:list-post:list-help:list-archive
	:list-unsubscribe;
	bh=RFIv6t6uU6/28kHtc1+PyuYkIslPcgmBDtw7hOdcXhI=;
	b=F3TZKnirDl9dDCRihBg8P5ov3307vwdQUQSec7Q8Wc04osZba+CpuhyuLjqSUjBxNN
	9MyqvGaxTB4Eovkl0Qzv5y7sZcvMhcQujdhMtvurbiuugT0RyoxT1qFL0l6osN7yiICu
	jeJMYl5JCBv5jzdkvNgNX6aw3y2zwd+QECVMQ=
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
	d=1e100.net; s=20210112;
	h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to
	:references:mime-version:x-original-sender
	:x-original-authentication-results:precedence:mailing-list:list-id
	:x-spam-checked-in-group:list-post:list-help:list-archive
	:list-unsubscribe;
	bh=RFIv6t6uU6/28kHtc1+PyuYkIslPcgmBDtw7hOdcXhI=;
	b=L/qnanqf1Rt93iFh5xNr8djKvdJMntAE+NkT4QlrCnNJmkLAmqSy8whFKHbBIvKKYj
	AeBN2UUfgBegkypGMqeNbTm1E+C4zAIJXZhab4pMaLf0bmIT6Cqc3ZS17OmnjNdYPOi5
	4g5F6ualpfErnUwVy4NDzlUc3JJ6+ceUV6cUXOabt0sODuR6P9e0ilVzjin1ef7ElfU4
	a2GS7mLkuKVOYyMQHCxAwZ+lltxuE+7FxapCY4KlNQ2h3n7vqVIz/U6b3GSfuEDYQHKF
	PLnnwIAJ+IqwXMDXnqFPeirpqeFNd7fK/+eoWyxcaQsRXbRvgm2dN8VHleum+VtfovHc
	KWXw==
X-Gm-Message-State: AOAM531NUkS7DP8t9/XSPiqjaGEeDmAcpNB+h9l2RwFKHCBdJgIoopgA
	YxCPVcZMnIp/cwpOhBEu+KqunJCR
X-Google-Smtp-Source: 
 ABdhPJy6jPwyj8YU1bZ2maF7w3vIozfQ0JAs3g4CJuoF51J37KCRzTFqA0V0zzO8QtQ0feCb5diAPg==
X-Received: by 2002:aa7:88d6:0:b0:4fa:ba98:4f5d with SMTP id
	k22-20020aa788d6000000b004faba984f5dmr20330440pff.5.1649434970018;
	Fri, 08 Apr 2022 09:22:50 -0700 (PDT)
X-BeenThere: linux-amarula@amarulasolutions.com
Received: by 2002:a05:6a00:13aa:b0:4fa:9dfd:68ee with SMTP id
	t42-20020a056a0013aa00b004fa9dfd68eels1433356pfg.10.gmail;
	Fri, 08 Apr 2022 09:22:49 -0700 (PDT)
X-Received: by 2002:a05:6a00:1908:b0:4f7:8813:b2cb with SMTP id
	y8-20020a056a00190800b004f78813b2cbmr20343967pfi.54.1649434969238;
	Fri, 08 Apr 2022 09:22:49 -0700 (PDT)
ARC-Seal: i=1; a=rsa-sha256; t=1649434969; cv=none;
	d=google.com; s=arc-20160816;
	b=XPrmAp0JU+HlFq6qPnXLunr70jI0lijWGPrIyybUhjM6V8zoyhOHB8RbaDRkmCCCmq
	yVbHatgWjjC9nSXLpLVWX89sSuDRHJfoZFNYcNwMZYBu9HEu5x44n131JoD4heptZlfm
	BpKwcYeAB+Kd3pA3/u9h7lZm8rH1c2GSrspUmIJchgonv3bdBm7Siy8VY6Zqm9ScHMSc
	ZmY0o6R8thv3PnAgO4TwqRvDVigjpDBHJMTfLrBGgjJfNfTMniloFiXk94H8q28JrxLD
	CtxZNds7VC7TT/V+M4EKF5u7SbijCqzdca9BqUyo01nP0vbRTqiU/ACYsxM6IvFABs+1
	meaA==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com;
	s=arc-20160816;
	h=content-transfer-encoding:mime-version:references:in-reply-to
	:message-id:date:subject:cc:to:from:dkim-signature;
	bh=h67+xEaF679u3X7yXL9S0kYbWc8Rb5WkxAfTc72OsWE=;
	b=McRZJhfOQg/e0ZKOu6GevB1VegU0clGsvRsu5qpQi6xTqkl/zsJOPYfqTTh2dSESId
	lYs09skQycavfXgxdYcZPTAMWVjUkhApRKe/EI1NvAWdzeHYCMYpKtnpiAI/k54UlcIL
	ZyYoLpJE7DzIoqc8tUXBJCSM7RxI39lawXoQ1yGqIvJ0u5oct1GhisuY5fGODWQvHfxt
	TA2Y3FrzeUhAyF4VzR0euEHhjwrdB79D7POedihTJ6z4kCLb905yB5D1i46GCOcqQkbm
	VaSJ3fJeblIVW4OFrFJYaCQlU09dgeT+wbJ6PitKlqnuEvDzhYbInrenaJy5LH1tKWhm
	DzIQ==
ARC-Authentication-Results: i=1; mx.google.com;
	dkim=pass header.i=@amarulasolutions.com header.s=google
	header.b=VjoSi9WU;
	spf=pass (google.com: domain of jagan@amarulasolutions.com designates
	209.85.220.41 as permitted sender)
	smtp.mailfrom=jagan@amarulasolutions.com;
	dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com
Received: from mail-sor-f41.google.com (mail-sor-f41.google.com.
	[209.85.220.41]) by mx.google.com with SMTPS id
	t71-20020a63814a000000b003746edc71e0sor1020413pgd.2.2022.04.08.09.22.49
	for <linux-amarula@amarulasolutions.com>
	(Google Transport Security); Fri, 08 Apr 2022 09:22:49 -0700 (PDT)
Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com
	designates 209.85.220.41 as permitted sender)
	client-ip=209.85.220.41;
X-Received: by 2002:a63:ec46:0:b0:381:81c4:ebbd with SMTP id
	r6-20020a63ec46000000b0038181c4ebbdmr16197865pgj.534.1649434968925;
	Fri, 08 Apr 2022 09:22:48 -0700 (PDT)
Received: from j-ThinkPad-E14-Gen-2.domain.name ([45.249.78.214])
	by smtp.gmail.com with ESMTPSA id
	n18-20020a056a0007d200b004fdac35672fsm24929863pfu.68.2022.04.08.09.22.41
	(version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);
	Fri, 08 Apr 2022 09:22:48 -0700 (PDT)
From: Jagan Teki <jagan@amarulasolutions.com>
To: Andrzej Hajda <andrzej.hajda@intel.com>, Inki Dae <inki.dae@samsung.com>,
	Marek Szyprowski <m.szyprowski@samsung.com>,
	Joonyoung Shim <jy0922.shim@samsung.com>,
	Seung-Woo Kim <sw0312.kim@samsung.com>,
	Kyungmin Park <kyungmin.park@samsung.com>,
	Frieder Schrempf <frieder.schrempf@kontron.de>,
	Fancy Fang <chen.fang@nxp.com>, Tim Harvey <tharvey@gateworks.com>,
	Michael Nazzareno Trimarchi <michael@amarulasolutions.com>,
	Adam Ford <aford173@gmail.com>, Neil Armstrong <narmstrong@baylibre.com>,
	Robert Foss <robert.foss@linaro.org>,
	Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
	Rob Herring <robh+dt@kernel.org>
Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
	linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	NXP Linux Team <linux-imx@nxp.com>,
	linux-amarula <linux-amarula@amarulasolutions.com>,
	Jagan Teki <jagan@amarulasolutions.com>
Subject: [PATCH 05/11] drm: bridge: samsung-dsim: Fix PLL_P (PMS_P) offset
Date: Fri,  8 Apr 2022 21:51:02 +0530
Message-Id: <20220408162108.184583-6-jagan@amarulasolutions.com>
X-Mailer: git-send-email 2.25.1
In-Reply-To: <20220408162108.184583-1-jagan@amarulasolutions.com>
References: <20220408162108.184583-1-jagan@amarulasolutions.com>
MIME-Version: 1.0
X-Original-Sender: jagan@amarulasolutions.com
X-Original-Authentication-Results: mx.google.com;       dkim=pass
	header.i=@amarulasolutions.com header.s=google header.b=VjoSi9WU;
	spf=pass (google.com: domain of jagan@amarulasolutions.com designates
	209.85.220.41 as permitted sender)
	smtp.mailfrom=jagan@amarulasolutions.com;
	dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com
Content-Type: text/plain; charset="UTF-8"
Precedence: list
Mailing-list: list linux-amarula@amarulasolutions.com;
	contact linux-amarula+owners@amarulasolutions.com
List-ID: <linux-amarula.amarulasolutions.com>
X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com
X-Google-Group-Id: 476853432473
List-Post: 
 <https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/post>,
	<mailto:linux-amarula@amarulasolutions.com>
List-Help: 
 <https://support.google.com/a/amarulasolutions.com/bin/topic.py?topic=25838>,
	<mailto:linux-amarula+help@amarulasolutions.com>
List-Archive: 
 <https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/>
List-Unsubscribe: 
 <mailto:googlegroups-manage+476853432473+unsubscribe@googlegroups.com>,
	<https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/subscribe>

The i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
with 13.7.10.1 Master PLL PMS Value setting Register mentioned PMS_P offset
range from BIT[18-13] and the upstream driver is using the same offset.

However, offset 13 is not working on i.MX8M Mini platforms but downstream
NXP driver is using 14 [1] and it is working with i.MX8M Mini SoC.

Not sure about whether it is reference manual documentation or something
else but this patch trusts the downstream code and fixes the PLL_P offset.

[1] https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/drm/bridge/sec-dsim.c?h=imx_5.4.47_2.2.0#n211

v1:
* updated commit message
* add downstream driver link

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/gpu/drm/bridge/samsung-dsim.c | 10 ++++++++--
 include/drm/bridge/samsung-dsim.h     |  1 +
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index 3e12b469dfa8..423d654e8ffd 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -169,7 +169,7 @@
 /* DSIM_PLLCTRL */
 #define DSIM_FREQ_BAND(x)		((x) << 24)
 #define DSIM_PLL_EN			(1 << 23)
-#define DSIM_PLL_P(x)			((x) << 13)
+#define DSIM_PLL_P(x, offset)		((x) << (offset))
 #define DSIM_PLL_M(x)			((x) << 4)
 #define DSIM_PLL_S(x)			((x) << 1)
 
@@ -369,6 +369,7 @@ static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = {
 	.max_freq = 1000,
 	.wait_for_reset = 1,
 	.num_bits_resol = 11,
+	.pll_p_offset = 13,
 	.reg_values = reg_values,
 	.platform_init = true,
 };
@@ -382,6 +383,7 @@ static const struct samsung_dsim_driver_data exynos4_dsi_driver_data = {
 	.max_freq = 1000,
 	.wait_for_reset = 1,
 	.num_bits_resol = 11,
+	.pll_p_offset = 13,
 	.reg_values = reg_values,
 	.platform_init = true,
 };
@@ -393,6 +395,7 @@ static const struct samsung_dsim_driver_data exynos5_dsi_driver_data = {
 	.max_freq = 1000,
 	.wait_for_reset = 1,
 	.num_bits_resol = 11,
+	.pll_p_offset = 13,
 	.reg_values = reg_values,
 	.platform_init = true,
 };
@@ -405,6 +408,7 @@ static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = {
 	.max_freq = 1500,
 	.wait_for_reset = 0,
 	.num_bits_resol = 12,
+	.pll_p_offset = 13,
 	.reg_values = exynos5433_reg_values,
 	.platform_init = true,
 };
@@ -417,6 +421,7 @@ static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = {
 	.max_freq = 1500,
 	.wait_for_reset = 1,
 	.num_bits_resol = 12,
+	.pll_p_offset = 13,
 	.reg_values = exynos5422_reg_values,
 	.platform_init = true,
 };
@@ -564,7 +569,8 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi,
 	writel(driver_data->reg_values[PLL_TIMER],
 			dsi->reg_base + driver_data->plltmr_reg);
 
-	reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s);
+	reg = DSIM_PLL_EN | DSIM_PLL_P(p, driver_data->pll_p_offset) |
+	      DSIM_PLL_M(m) | DSIM_PLL_S(s);
 
 	if (driver_data->has_freqband) {
 		static const unsigned long freq_bands[] = {
diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung-dsim.h
index eca7eacb5910..4eb48ec6543f 100644
--- a/include/drm/bridge/samsung-dsim.h
+++ b/include/drm/bridge/samsung-dsim.h
@@ -38,6 +38,7 @@ struct samsung_dsim_driver_data {
 	unsigned int max_freq;
 	unsigned int wait_for_reset;
 	unsigned int num_bits_resol;
+	unsigned int pll_p_offset;
 	const unsigned int *reg_values;
 	bool platform_init;
 };

From patchwork Fri Apr  8 16:21:03 2022
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
X-Patchwork-Submitter: Jagan Teki <jagan@amarulasolutions.com>
X-Patchwork-Id: 1907
Return-Path: 
 <linux-amarula+bncBD7MFH7A7EEBBYWCYGJAMGQE4FQZ2LY@amarulasolutions.com>
X-Original-To: linux-amarula@patchwork.amarulasolutions.com
Delivered-To: linux-amarula@patchwork.amarulasolutions.com
Received: from mail-pl1-f197.google.com (mail-pl1-f197.google.com
	[209.85.214.197])
	by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 672883F0D5
	for <linux-amarula@patchwork.amarulasolutions.com>;
	Fri,  8 Apr 2022 18:22:59 +0200 (CEST)
Received: by mail-pl1-f197.google.com with SMTP id
	h9-20020a170902f54900b001582df39ce2sf411931plf.19
	for <linux-amarula@patchwork.amarulasolutions.com>;
	Fri, 08 Apr 2022 09:22:59 -0700 (PDT)
ARC-Seal: i=2; a=rsa-sha256; t=1649434978; cv=pass;
	d=google.com; s=arc-20160816;
	b=J6Un46KcLn9YdWp9ELvPyn7kV4icm7t4jaOVJs/L1nw1kFyLNRCuHl+Kxc/GRxkfoN
	GE33UjYANIoNXRhI7tCafUUEZs0FiNuLYZXCH0KsZDEI/8X0pBTyyju7VElyCh1aSVwF
	pk2ZKj0S6DwlDlIWysiB0eL4+XFc3ncCaW9IYMmEq+0U0Gbt9+bEL2IfHOb1UXwb/RMg
	8IBTWzu+qLmshmLroz3082fzUhwnWRlahW43rEEJSG1J5YMy8wPXe5mC4OD8MJ/QXi7n
	95i2S0KNdXmXdnwlOI4BOGNTCH/J9RNjlzPApco7Ai/4vmxzooWHPTgGL5oPkKj2ukiF
	W4DQ==
ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com;
	s=arc-20160816;
	h=list-unsubscribe:list-archive:list-help:list-post:list-id
	:mailing-list:precedence:mime-version:references:in-reply-to
	:message-id:date:subject:cc:to:from:dkim-signature;
	bh=MAZ/9N9tM4HritKGvz1/i/gh9hy4bSyJIqB7JRNq8F0=;
	b=Tp/0w/vdY9n2hb5vuo8md3lcy69/jtBmr99uH/pdI7e3km7uS+6Rs/KGmc2lFW4VUW
	yY+iq7AtX/+GUKDXLMujrqByphyv5I+jgBkO5ZD3BbYMVQukVwgdVwY/QcxkuUq3m9FY
	RcWQm2OS5mZwCKfqNU1HJLIU31fjc6ZFGIMkw4KnR56pG0EuVGg3z0TyVS1csHGuvDgj
	ZYJhr02MsJfdM9GUblQaJEzxWsUNkC5LkFa+xP0efM3gni0eKwUqYxMoHtuTCPIOS3Df
	l/xtJyA0GxiVWY2f5SgasUF4UTwpSK8qqn1t4y8Yl+VCjiEHomRNqimnHMJZBn9jtKxD
	8ZNg==
ARC-Authentication-Results: i=2; mx.google.com;
	dkim=pass header.i=@amarulasolutions.com header.s=google
	header.b=PJ1FXOhy;
	spf=pass (google.com: domain of jagan@amarulasolutions.com designates
	209.85.220.41 as permitted sender)
	smtp.mailfrom=jagan@amarulasolutions.com;
	dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
	d=amarulasolutions.com; s=google;
	h=from:to:cc:subject:date:message-id:in-reply-to:references
	:mime-version:x-original-sender:x-original-authentication-results
	:precedence:mailing-list:list-id:list-post:list-help:list-archive
	:list-unsubscribe;
	bh=MAZ/9N9tM4HritKGvz1/i/gh9hy4bSyJIqB7JRNq8F0=;
	b=BAAGDJwuO/JqJPprfa6/QN/bXqha8327BoGxhlw0Wnt9FSgEmUX2BSeG7CTqCP8oBS
	7IjY/spoVVGxgSRV9rAH8kDiQ97J0DJdRhLC7GJBIASuZOQ5FrriqldFgHywe8HNP64k
	25LsitpwspSbr8oAP1Ig7ytVUQfb6AEStTQxg=
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
	d=1e100.net; s=20210112;
	h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to
	:references:mime-version:x-original-sender
	:x-original-authentication-results:precedence:mailing-list:list-id
	:x-spam-checked-in-group:list-post:list-help:list-archive
	:list-unsubscribe;
	bh=MAZ/9N9tM4HritKGvz1/i/gh9hy4bSyJIqB7JRNq8F0=;
	b=4mil7X7gqhn6KNKjB6AEImsHZDYDU1LWr685KWQzRpdsptgy/SbkoMuhgPY5UWVvI6
	l7VoPK8Nkbhf+tLWxYxg43BOB38jGt6MGlYLdY6fEpc8t/ErBzRzCxPHDNaJsWwFB4pP
	m9w7K4XZauOsnvbjW9etalCpHDHoOEAcnb1kaOGr4VKRdB8cz1cwXczVH7LMBudXS3nA
	bjYjlQLMNc/L7S/YLzv5SpFqOwFUYLGhdRa3Votn0i4vRomuOp6sV7pg4XVatejp0xdD
	cfl7W22V7neyLBb150ZMwIyU7WCztbTJHCVW0Z55c+HhNevAp2ednBFmIZdgypyz4Ggm
	1zcQ==
X-Gm-Message-State: AOAM5305LQ5FJ3Ng4kVnOacwNSHfbaatzQ7fEQIAlhB4VPVbB0BjAAot
	IIq0dfk+T/6uXh4M+rXMgELgXPbX
X-Google-Smtp-Source: 
 ABdhPJwtY6sKuK/oiVyhvCJ8+AMqiqVsagesEj1mxL6CFRFNFcR+tO3fGIgSbNL5Li1DEvght0Hhjw==
X-Received: by 2002:a17:903:2444:b0:154:13b6:8850 with SMTP id
	l4-20020a170903244400b0015413b68850mr20109057pls.55.1649434978231;
	Fri, 08 Apr 2022 09:22:58 -0700 (PDT)
X-BeenThere: linux-amarula@amarulasolutions.com
Received: by 2002:a05:6a00:23c2:b0:4fa:698b:ecd with SMTP id
	g2-20020a056a0023c200b004fa698b0ecdls1436639pfc.8.gmail;
	Fri, 08 Apr 2022 09:22:57 -0700 (PDT)
X-Received: by 2002:a65:5acd:0:b0:399:24bc:bbfd with SMTP id
	d13-20020a655acd000000b0039924bcbbfdmr16372034pgt.323.1649434977483;
	Fri, 08 Apr 2022 09:22:57 -0700 (PDT)
ARC-Seal: i=1; a=rsa-sha256; t=1649434977; cv=none;
	d=google.com; s=arc-20160816;
	b=pgwZk3kEvMG00KJ+I/2RmvVR9bFTXoesLfoobNvso5+lbWmEJrDzT9rw+2Wo3axBr+
	G35N1L61EHBkCR7U3IPo0dt04eAMp7S84oeyeZ6ZKAR0KL9J3gXRqakwQ84a9Ti/gkRf
	fQ3V8s/bOuA7ESfi8/ygpkIqIZ1xkozqI/8g73iPFSg/aKDyCCnDOVbDPdB5prYnpYmE
	YOns2axX5L5kPJjdS6/ylEmzeCV9iEhGJErwWMqkBrnOBoBud5cKDTh0/+coDlGhx6zR
	qhN0R5sSJZGrVt+IsMWA1PsWbJyVjqML6mkjwR1oF1psoRhvTDabnpmG81s5tnsNpZKr
	cvxQ==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com;
	s=arc-20160816;
	h=content-transfer-encoding:mime-version:references:in-reply-to
	:message-id:date:subject:cc:to:from:dkim-signature;
	bh=Is0eSnwBB0c+KCKE5P6y3Z/4g9fKoG//Yrq64nJGzuA=;
	b=gVy5imTpyQOTGitxR18NyPwEMRGjsl5GyT78qdEO9uOgr5IP6Iep7sXvRCDuzsWfNJ
	mF16tT96wmj/smLWW1wxDm6/INnZ88Q55wUgJHHuBvG5hW788wcVGcUqo5TGR8FOz6jE
	V+4Pk73Zo/cQsdHXFNAf6iJPLLEJcduiIwf1L1DPnZkW71sZvRb5pVkUcUl/zSo5psft
	lKdoEpzDOvmHm8lYN7ZlCS4kg4a0+p+Y5CB57vNKeJcdwwdpWFvnuQwwm30tM4l4m3Gh
	/XJJwfgGQLd9jWH53j/hZdrkIig18gCm7pSG2xYTnb5eW9cAN1+YphhtuRyOLQnyjQZe
	YjJw==
ARC-Authentication-Results: i=1; mx.google.com;
	dkim=pass header.i=@amarulasolutions.com header.s=google
	header.b=PJ1FXOhy;
	spf=pass (google.com: domain of jagan@amarulasolutions.com designates
	209.85.220.41 as permitted sender)
	smtp.mailfrom=jagan@amarulasolutions.com;
	dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com
Received: from mail-sor-f41.google.com (mail-sor-f41.google.com.
	[209.85.220.41]) by mx.google.com with SMTPS id
	y8-20020a1709027c8800b00154aa89f135sor680960pll.123.2022.04.08.09.22.57
	for <linux-amarula@amarulasolutions.com>
	(Google Transport Security); Fri, 08 Apr 2022 09:22:57 -0700 (PDT)
Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com
	designates 209.85.220.41 as permitted sender)
	client-ip=209.85.220.41;
X-Received: by 2002:a17:902:cf05:b0:156:9d:ca01 with SMTP id
	i5-20020a170902cf0500b00156009dca01mr19868194plg.111.1649434977157;
	Fri, 08 Apr 2022 09:22:57 -0700 (PDT)
Received: from j-ThinkPad-E14-Gen-2.domain.name ([45.249.78.214])
	by smtp.gmail.com with ESMTPSA id
	n18-20020a056a0007d200b004fdac35672fsm24929863pfu.68.2022.04.08.09.22.49
	(version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);
	Fri, 08 Apr 2022 09:22:56 -0700 (PDT)
From: Jagan Teki <jagan@amarulasolutions.com>
To: Andrzej Hajda <andrzej.hajda@intel.com>, Inki Dae <inki.dae@samsung.com>,
	Marek Szyprowski <m.szyprowski@samsung.com>,
	Joonyoung Shim <jy0922.shim@samsung.com>,
	Seung-Woo Kim <sw0312.kim@samsung.com>,
	Kyungmin Park <kyungmin.park@samsung.com>,
	Frieder Schrempf <frieder.schrempf@kontron.de>,
	Fancy Fang <chen.fang@nxp.com>, Tim Harvey <tharvey@gateworks.com>,
	Michael Nazzareno Trimarchi <michael@amarulasolutions.com>,
	Adam Ford <aford173@gmail.com>, Neil Armstrong <narmstrong@baylibre.com>,
	Robert Foss <robert.foss@linaro.org>,
	Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
	Rob Herring <robh+dt@kernel.org>
Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
	linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	NXP Linux Team <linux-imx@nxp.com>,
	linux-amarula <linux-amarula@amarulasolutions.com>,
	Jagan Teki <jagan@amarulasolutions.com>
Subject: [PATCH 06/11] drm: bridge: samsung-dsim: Add module init, exit
Date: Fri,  8 Apr 2022 21:51:03 +0530
Message-Id: <20220408162108.184583-7-jagan@amarulasolutions.com>
X-Mailer: git-send-email 2.25.1
In-Reply-To: <20220408162108.184583-1-jagan@amarulasolutions.com>
References: <20220408162108.184583-1-jagan@amarulasolutions.com>
MIME-Version: 1.0
X-Original-Sender: jagan@amarulasolutions.com
X-Original-Authentication-Results: mx.google.com;       dkim=pass
	header.i=@amarulasolutions.com header.s=google header.b=PJ1FXOhy;
	spf=pass (google.com: domain of jagan@amarulasolutions.com designates
	209.85.220.41 as permitted sender)
	smtp.mailfrom=jagan@amarulasolutions.com;
	dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com
Content-Type: text/plain; charset="UTF-8"
Precedence: list
Mailing-list: list linux-amarula@amarulasolutions.com;
	contact linux-amarula+owners@amarulasolutions.com
List-ID: <linux-amarula.amarulasolutions.com>
X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com
X-Google-Group-Id: 476853432473
List-Post: 
 <https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/post>,
	<mailto:linux-amarula@amarulasolutions.com>
List-Help: 
 <https://support.google.com/a/amarulasolutions.com/bin/topic.py?topic=25838>,
	<mailto:linux-amarula+help@amarulasolutions.com>
List-Archive: 
 <https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/>
List-Unsubscribe: 
 <mailto:googlegroups-manage+476853432473+unsubscribe@googlegroups.com>,
	<https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/subscribe>

Add module init and exit functions for the bridge to register
and unregister dsi_driver.

Exynos drm driver stack will register the platform_driver separately
in the common of it's exynos_drm_drv.c including dsi_driver.

Register again would return -EBUSY, so return 0 for such cases as
dsi_driver is already registered.

v1:
* none

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/gpu/drm/bridge/samsung-dsim.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index 423d654e8ffd..1fe4b8e737a4 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -1696,6 +1696,28 @@ struct platform_driver dsi_driver = {
 	},
 };
 
+static int __init samsung_mipi_dsim_init(void)
+{
+	int ret;
+
+	ret = platform_driver_register(&dsi_driver);
+
+	/**
+	 * Exynos drm driver stack will register the platform_driver
+	 * separately in the common of it's exynos_drm_drv.c including
+	 * dsi_driver. Register again would return -EBUSY, so return 0
+	 * for such cases as dsi_driver is already registered.
+	 */
+	return ret == -EBUSY ? 0 : ret;
+}
+module_init(samsung_mipi_dsim_init);
+
+static void __exit samsung_mipi_dsim_exit(void)
+{
+	platform_driver_unregister(&dsi_driver);
+}
+module_exit(samsung_mipi_dsim_exit);
+
 MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>");
 MODULE_DESCRIPTION("Samsung MIPI DSIM controller bridge");
 MODULE_LICENSE("GPL v2");

From patchwork Fri Apr  8 16:21:04 2022
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
X-Patchwork-Submitter: Jagan Teki <jagan@amarulasolutions.com>
X-Patchwork-Id: 1908
Return-Path: 
 <linux-amarula+bncBD7MFH7A7EEBB2WCYGJAMGQEPDIEXCQ@amarulasolutions.com>
X-Original-To: linux-amarula@patchwork.amarulasolutions.com
Delivered-To: linux-amarula@patchwork.amarulasolutions.com
Received: from mail-pj1-f69.google.com (mail-pj1-f69.google.com
	[209.85.216.69])
	by ganimede.amarulasolutions.com (Postfix) with ESMTPS id A827F3F0D5
	for <linux-amarula@patchwork.amarulasolutions.com>;
	Fri,  8 Apr 2022 18:23:07 +0200 (CEST)
Received: by mail-pj1-f69.google.com with SMTP id
	g14-20020a17090a4b0e00b001cb1363ae99sf3205864pjh.1
	for <linux-amarula@patchwork.amarulasolutions.com>;
	Fri, 08 Apr 2022 09:23:07 -0700 (PDT)
ARC-Seal: i=2; a=rsa-sha256; t=1649434986; cv=pass;
	d=google.com; s=arc-20160816;
	b=uO4U3t8I1NQvV115M0hP8FqszJfopUrdvQePmlYpAbWi4Doc37cH+vHDIZT8u4zK03
	AV6TGUhOE9sB+RjmT0xiWvyvM85hgNqW6Y+XpQtAkj6b5a5KqwbEPIRDdcMY/umzVHfs
	b4VgwboI6FYcz8Q8oKj1VB3LstQ7DUVNIzdS9+21wBfk7fkfq9FgObsTiHkUhlXVRKvS
	QM0RDwM4JgQ6jfKxWM1LxNw7gCKgFam1oeFbWDsyYPnEhsjEH3dXsAg/64C4dU0mIos4
	6beEGpOe5ypxEQR2QZVqOQrlLm24fZXq08WdeVaKIF60KdJqGeqk3kFQGd1PnyslTMsF
	6fPw==
ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com;
	s=arc-20160816;
	h=list-unsubscribe:list-archive:list-help:list-post:list-id
	:mailing-list:precedence:mime-version:references:in-reply-to
	:message-id:date:subject:cc:to:from:dkim-signature;
	bh=QAbt8PW5BOLmpQgmOZThfWs/fdW4LdwPtPaK3dlPBDU=;
	b=ibZgXeDU5gWMp6DtZwjMQ3YTp9QSYh9QIjv/uaLTJH0zeSJtCi5oFFkJfF0q3LeC3/
	jMuKez394GI4k1SoV9XS4JfwmtASX/MDANZhKC6N/OyVlq3/OeOrsyThmL/xAZdQ1Hw4
	iEOc/5GDGRAsTJ09RAqApQAP2a2Bpz+Vkn5FWisDsrOrAxeHVWE2wPdUrEG1jX/rowh/
	5fqzE23fd35HhZDVmfSRkkr3rmDBnSCRqSFefDj57zzVPSs4Lg5uucvbwpl0rvQMkH24
	XODq6SZLXQe5nZFxBVWHPF6yNiGuxZhAp/OqYpSRwpcRT+/Qh7rGBkkPRiUfqfN+D4WJ
	0sZg==
ARC-Authentication-Results: i=2; mx.google.com;
	dkim=pass header.i=@amarulasolutions.com header.s=google
	header.b=rDDE8uCI;
	spf=pass (google.com: domain of jagan@amarulasolutions.com designates
	209.85.220.41 as permitted sender)
	smtp.mailfrom=jagan@amarulasolutions.com;
	dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
	d=amarulasolutions.com; s=google;
	h=from:to:cc:subject:date:message-id:in-reply-to:references
	:mime-version:x-original-sender:x-original-authentication-results
	:precedence:mailing-list:list-id:list-post:list-help:list-archive
	:list-unsubscribe;
	bh=QAbt8PW5BOLmpQgmOZThfWs/fdW4LdwPtPaK3dlPBDU=;
	b=PJGJFJQ4LtMQucT2il1kev7ftgP/RF/3BWcoUju62H1AjTrVLdSkE9kqI0VOIAewjf
	aalt0gyIOtpTJoXPlSzndjeuEqj3lS2NH+IkONTostLxtr0zbBiPZHa4KbXkjcfPQ7ty
	JdBfkeSktpd0liHUohI754ZPdkvtVw7WKHevs=
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
	d=1e100.net; s=20210112;
	h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to
	:references:mime-version:x-original-sender
	:x-original-authentication-results:precedence:mailing-list:list-id
	:x-spam-checked-in-group:list-post:list-help:list-archive
	:list-unsubscribe;
	bh=QAbt8PW5BOLmpQgmOZThfWs/fdW4LdwPtPaK3dlPBDU=;
	b=wyGa4PK1/z+aDTWZLBG9uL4hF1gzguMNV0wTt9j6ZMyGNy9vrMAe/rm3lWceURR0d2
	/GuYlbkqff8jEj59eOzJ6gEAWCCmPiqaBF0m1mUmeZokDcJt181ebwAHsETmInPIgt9b
	5VHpN3hAWrAOxNhiGlsT1VtmaIP/ty+/6w0mW19O4/H5m5dr2SOTKoOD8xlUwnhoYCIH
	wl7jqqQ29xUTi7x/CtLNR53eRlvmgkfTf/Cf3Hx9cg7ntyJRcwc7h3NBAArQGRDUnwOW
	ODqD/HWJDep42HjCyR8pt6md+WLqj3GnpeT2ig/KhfBn+OZlyL5yGAV3KNRzl5oan1dj
	4ZUw==
X-Gm-Message-State: AOAM531ElTs+CbBbuCcUB4/Jw9aEruapFfaK6/XU+bW5julgNKHL1gpg
	/W2N30TprzGwjkpMatDyxCtfpsF/
X-Google-Smtp-Source: 
 ABdhPJw4184GXfD+n4XV2yshC7WfwLaqYe3GNrrg+E4ldB1EfxNO3cJtoEtDzsY3maMd3Xq4/pbaxw==
X-Received: by 2002:a17:902:ce02:b0:153:bd65:5c0e with SMTP id
	k2-20020a170902ce0200b00153bd655c0emr19842514plg.160.1649434986489;
	Fri, 08 Apr 2022 09:23:06 -0700 (PDT)
X-BeenThere: linux-amarula@amarulasolutions.com
Received: by 2002:a17:90a:1b64:b0:1ca:ab17:e0fc with SMTP id
	q91-20020a17090a1b6400b001caab17e0fcls2079439pjq.1.gmail;
	Fri, 08 Apr 2022 09:23:06 -0700 (PDT)
X-Received: by 2002:a17:90b:4ad2:b0:1c7:cee:b126 with SMTP id
	mh18-20020a17090b4ad200b001c70ceeb126mr22399460pjb.219.1649434985701;
	Fri, 08 Apr 2022 09:23:05 -0700 (PDT)
ARC-Seal: i=1; a=rsa-sha256; t=1649434985; cv=none;
	d=google.com; s=arc-20160816;
	b=OoXsS2sObSWk9DGxarN1lGxlugXHBNOtqTKyv0Oc//iVEFcxvgITZF96PkDNvLq0na
	oDzhYSYTufn21tRouKrYhzAN2ZrueI7RqAZYX0EJGNtwpBwPXEriqFO7nD4HhYlCLy4v
	Lc7WhEvnOw7+33ZIlSSZW18rSOwBHezde/chDMEsdyokEbZgfkLQHbBaEL52W0pQiW+V
	7VxpuXFUYj26ptqfQDq9Pnjhc38zWKf9dFitomicWao+FtvGxHUcjqFdjtCih319dkkh
	VvF6ZWjoCFjNc41lPQaLleqDlfja+I2YR4ZHpk8xpww1//L9FGN5p9Xds/gUB+hhfGjf
	fdZA==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com;
	s=arc-20160816;
	h=content-transfer-encoding:mime-version:references:in-reply-to
	:message-id:date:subject:cc:to:from:dkim-signature;
	bh=QPxziLerI0UxR876U+YKww6O14nhkPwPhp+Yk2SkNsw=;
	b=YNYt80UdD9Di0eDNK6pB8cps4Jkp+RRsjc4e0sz966AUsNb5Wq40C1D5CJi9jqySJP
	17umj6q/C7RD5b0gTMR346gZjvxNTYHWbtGiVqrq+K6sqM1riC/C3XSE09t+Jihiaxwr
	XHse0FSrEC6lvwXGE71SioK1lLKqmbWaJxcUXNs+B39pXWB+SaP0K+M7PXThEmfbBbBY
	55W5FEtG9Q39o4wCuwd27juMq2mw0XnhmfpK+8/IVADalxByaWmXvJzPEPOifKcWqYo+
	d9F/2ziMknUOwQUfqhYzJoMkDEufaHWz4cKqT7pLoXrHH/DJMKvn+1vxvVs4EsNTaOWS
	1cPA==
ARC-Authentication-Results: i=1; mx.google.com;
	dkim=pass header.i=@amarulasolutions.com header.s=google
	header.b=rDDE8uCI;
	spf=pass (google.com: domain of jagan@amarulasolutions.com designates
	209.85.220.41 as permitted sender)
	smtp.mailfrom=jagan@amarulasolutions.com;
	dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com
Received: from mail-sor-f41.google.com (mail-sor-f41.google.com.
	[209.85.220.41]) by mx.google.com with SMTPS id
	128-20020a620486000000b004fa8e92e2f8sor956538pfe.18.2022.04.08.09.23.05
	for <linux-amarula@amarulasolutions.com>
	(Google Transport Security); Fri, 08 Apr 2022 09:23:05 -0700 (PDT)
Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com
	designates 209.85.220.41 as permitted sender)
	client-ip=209.85.220.41;
X-Received: by 2002:a63:d955:0:b0:398:b864:ab71 with SMTP id
	e21-20020a63d955000000b00398b864ab71mr16413922pgj.515.1649434985368;
	Fri, 08 Apr 2022 09:23:05 -0700 (PDT)
Received: from j-ThinkPad-E14-Gen-2.domain.name ([45.249.78.214])
	by smtp.gmail.com with ESMTPSA id
	n18-20020a056a0007d200b004fdac35672fsm24929863pfu.68.2022.04.08.09.22.57
	(version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);
	Fri, 08 Apr 2022 09:23:04 -0700 (PDT)
From: Jagan Teki <jagan@amarulasolutions.com>
To: Andrzej Hajda <andrzej.hajda@intel.com>, Inki Dae <inki.dae@samsung.com>,
	Marek Szyprowski <m.szyprowski@samsung.com>,
	Joonyoung Shim <jy0922.shim@samsung.com>,
	Seung-Woo Kim <sw0312.kim@samsung.com>,
	Kyungmin Park <kyungmin.park@samsung.com>,
	Frieder Schrempf <frieder.schrempf@kontron.de>,
	Fancy Fang <chen.fang@nxp.com>, Tim Harvey <tharvey@gateworks.com>,
	Michael Nazzareno Trimarchi <michael@amarulasolutions.com>,
	Adam Ford <aford173@gmail.com>, Neil Armstrong <narmstrong@baylibre.com>,
	Robert Foss <robert.foss@linaro.org>,
	Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
	Rob Herring <robh+dt@kernel.org>
Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
	linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	NXP Linux Team <linux-imx@nxp.com>,
	linux-amarula <linux-amarula@amarulasolutions.com>,
	Jagan Teki <jagan@amarulasolutions.com>
Subject: [PATCH 07/11] drm: bridge: samsung-dsim: Add atomic_check
Date: Fri,  8 Apr 2022 21:51:04 +0530
Message-Id: <20220408162108.184583-8-jagan@amarulasolutions.com>
X-Mailer: git-send-email 2.25.1
In-Reply-To: <20220408162108.184583-1-jagan@amarulasolutions.com>
References: <20220408162108.184583-1-jagan@amarulasolutions.com>
MIME-Version: 1.0
X-Original-Sender: jagan@amarulasolutions.com
X-Original-Authentication-Results: mx.google.com;       dkim=pass
	header.i=@amarulasolutions.com header.s=google header.b=rDDE8uCI;
	spf=pass (google.com: domain of jagan@amarulasolutions.com designates
	209.85.220.41 as permitted sender)
	smtp.mailfrom=jagan@amarulasolutions.com;
	dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com
Content-Type: text/plain; charset="UTF-8"
Precedence: list
Mailing-list: list linux-amarula@amarulasolutions.com;
	contact linux-amarula+owners@amarulasolutions.com
List-ID: <linux-amarula.amarulasolutions.com>
X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com
X-Google-Group-Id: 476853432473
List-Post: 
 <https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/post>,
	<mailto:linux-amarula@amarulasolutions.com>
List-Help: 
 <https://support.google.com/a/amarulasolutions.com/bin/topic.py?topic=25838>,
	<mailto:linux-amarula+help@amarulasolutions.com>
List-Archive: 
 <https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/>
List-Unsubscribe: 
 <mailto:googlegroups-manage+476853432473+unsubscribe@googlegroups.com>,
	<https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/subscribe>

Fixing up the mode flags is required in order to correlate the
correct sync flags of the surrounding components in the chain
to make sure the whole pipeline can work properly.

So, handle the mode flags via bridge, atomic_check.

v1:
* fix mode flags in atomic_check instead of mode_fixup

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/gpu/drm/bridge/samsung-dsim.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index 1fe4b8e737a4..38db1f93ed51 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -1338,6 +1338,19 @@ static void samsung_dsim_atomic_post_disable(struct drm_bridge *bridge,
 	pm_runtime_put_sync(dsi->dev);
 }
 
+static int samsung_dsim_atomic_check(struct drm_bridge *bridge,
+				     struct drm_bridge_state *bridge_state,
+				     struct drm_crtc_state *crtc_state,
+				     struct drm_connector_state *conn_state)
+{
+	struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
+
+	adjusted_mode->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
+	adjusted_mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
+
+	return 0;
+}
+
 static void samsung_dsim_mode_set(struct drm_bridge *bridge,
 				  const struct drm_display_mode *mode,
 				  const struct drm_display_mode *adjusted_mode)
@@ -1359,6 +1372,7 @@ static const struct drm_bridge_funcs samsung_dsim_bridge_funcs = {
 	.atomic_duplicate_state		= drm_atomic_helper_bridge_duplicate_state,
 	.atomic_destroy_state		= drm_atomic_helper_bridge_destroy_state,
 	.atomic_reset			= drm_atomic_helper_bridge_reset,
+	.atomic_check			= samsung_dsim_atomic_check,
 	.atomic_pre_enable		= samsung_dsim_atomic_pre_enable,
 	.atomic_enable			= samsung_dsim_atomic_enable,
 	.atomic_disable			= samsung_dsim_atomic_disable,

From patchwork Fri Apr  8 16:21:05 2022
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
X-Patchwork-Submitter: Jagan Teki <jagan@amarulasolutions.com>
X-Patchwork-Id: 1909
Return-Path: 
 <linux-amarula+bncBD7MFH7A7EEBB4WCYGJAMGQELYJV7CI@amarulasolutions.com>
X-Original-To: linux-amarula@patchwork.amarulasolutions.com
Delivered-To: linux-amarula@patchwork.amarulasolutions.com
Received: from mail-pj1-f72.google.com (mail-pj1-f72.google.com
	[209.85.216.72])
	by ganimede.amarulasolutions.com (Postfix) with ESMTPS id EB59F3F0D5
	for <linux-amarula@patchwork.amarulasolutions.com>;
	Fri,  8 Apr 2022 18:23:15 +0200 (CEST)
Received: by mail-pj1-f72.google.com with SMTP id
	d10-20020a17090a3b0a00b001ca93b34e3csf5700063pjc.7
	for <linux-amarula@patchwork.amarulasolutions.com>;
	Fri, 08 Apr 2022 09:23:15 -0700 (PDT)
ARC-Seal: i=2; a=rsa-sha256; t=1649434994; cv=pass;
	d=google.com; s=arc-20160816;
	b=s/eXxdzkeHgEUOkJbhNrWXWZmdcScRXqF9IIM0YFcj3ohF6h8BKIZEH+WNxWWSgPCr
	MgDJLh2hCFqkJZsnJAs69GnJ8K3Mw9WulrVPkJA57NLa4vmt/mP+fyy+ihlPv0V6ckb/
	UP9cL7lX4fNRO4BEHvxQ14ljF/GQCHmK7J76RIhiaijhWC2OKfhda5mOTp9OyfcFFxN6
	GMsRGloAwOULmEBF/7/3KwhaXCYXMnMNxefoWDWxfGzXCkGKL1rZcJbnlfIxE17BFg+o
	6qyQLFUPcB4KFvD/7jZ/cFaHggd/5Dv/KQ11pvFGXmU/D61fN5eDldkGMRJuUMvjdWEc
	6gKw==
ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com;
	s=arc-20160816;
	h=list-unsubscribe:list-archive:list-help:list-post:list-id
	:mailing-list:precedence:mime-version:references:in-reply-to
	:message-id:date:subject:cc:to:from:dkim-signature;
	bh=1jh0Z17DnObZ/lkmzyuHgs/7q5ufAf5U3vIE+BGQtJc=;
	b=XEWmZp70PRppuZ7DM4ee0wwSEGztqzHwFQKIQ3l2cCacF/y8BoLSTQkproAn2MXE6p
	frdgmqdZj5VIP/NdlAwFifY9VcswHZBlyoXVET5FqPNnsOcInmiT2vVgJrEvuU3uCBQf
	jwyhPx/ncgUdlkDVkuKpxdnWgD2sXQwK7ncgefCru07vngkgtjNB4uQ+ePg0gp4pFqnA
	hKmlvFOyjLUV9esPRFO/jS8LfYEMfeDmo5lQhN8LNBxFeyivPG+dhYtpLg+NdzjBTAYl
	7SqWHanYsF6o4/otukNBQJF7S1BHZi7TNDRG8UdJHjR4QqAPZkTJA4n37MZNUHCu/oO3
	fViQ==
ARC-Authentication-Results: i=2; mx.google.com;
	dkim=pass header.i=@amarulasolutions.com header.s=google
	header.b="AUwD0c/H";
	spf=pass (google.com: domain of jagan@amarulasolutions.com designates
	209.85.220.41 as permitted sender)
	smtp.mailfrom=jagan@amarulasolutions.com;
	dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
	d=amarulasolutions.com; s=google;
	h=from:to:cc:subject:date:message-id:in-reply-to:references
	:mime-version:x-original-sender:x-original-authentication-results
	:precedence:mailing-list:list-id:list-post:list-help:list-archive
	:list-unsubscribe;
	bh=1jh0Z17DnObZ/lkmzyuHgs/7q5ufAf5U3vIE+BGQtJc=;
	b=pxr9vzUrJ8VnrHyKxfKsxmg82cYQV9CuiC85Ka3som4Dcv8TdeZqV7ElCWiOodcFpk
	cbyQYetBBKitv46YY1t7TWg2J6uzCK1es1jppk9oMklPZcDKjPwoFyy3MS7ypp0/ETfd
	Y/M97M9iQj91H1E/eMpTmwTasG3P86Vh84TMA=
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
	d=1e100.net; s=20210112;
	h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to
	:references:mime-version:x-original-sender
	:x-original-authentication-results:precedence:mailing-list:list-id
	:x-spam-checked-in-group:list-post:list-help:list-archive
	:list-unsubscribe;
	bh=1jh0Z17DnObZ/lkmzyuHgs/7q5ufAf5U3vIE+BGQtJc=;
	b=smq2u7i/IW0N8XFolBsr9E3OT+9tbztY/+TMWssrupdRvbC60iaIOElyevuyyIdPLt
	rN4mnrd2pG1IqUNeayzCXtY8E9ofqGrpJIhMYX7Wvy7RfbWRgaI8ZOYvXo9sjP5Ig4MP
	K+OyrjBWelmcHxJunE0dOfdscKRz0BhZYkxQ0lFTWOOG37BcrrJ2Y5UAB+pzz5kb8Jf+
	9eqb5HooHTyi+jPTtWPbR4lCPBl5HGRAvx5VjnlQtWfh2ifUpKRZHK0HVCozqN7nKpVe
	7WumQGRRzrdQfIyGmWHCUTePSM/Hyo0iqu/TLn5XlIht+VWKuvN0NufrYZbsHnvOLZLF
	IrZw==
X-Gm-Message-State: AOAM532MiFlZBcnilGW5HeaJYdY4JxEWT7DXKczfXU1U8iVzvfOTSTN3
	Nkeafw08cJb5kp9D4Iw6nHIx3vYQ
X-Google-Smtp-Source: 
 ABdhPJwHeErQthdXNjN9vx4wltM4CdHlp8fjKAOXJa+iEDwv54RBcuAx+wckNDQIh1v9XOjK/aUmAQ==
X-Received: by 2002:a17:902:cec1:b0:158:2ced:1e1b with SMTP id
	d1-20020a170902cec100b001582ced1e1bmr1984586plg.145.1649434994800;
	Fri, 08 Apr 2022 09:23:14 -0700 (PDT)
X-BeenThere: linux-amarula@amarulasolutions.com
Received: by 2002:a05:6a00:179d:b0:505:9501:adc5 with SMTP id
	s29-20020a056a00179d00b005059501adc5ls285728pfg.2.gmail;
	Fri, 08 Apr 2022 09:23:14 -0700 (PDT)
X-Received: by 2002:a63:fa56:0:b0:399:3452:ffa8 with SMTP id
	g22-20020a63fa56000000b003993452ffa8mr16140898pgk.255.1649434994063;
	Fri, 08 Apr 2022 09:23:14 -0700 (PDT)
ARC-Seal: i=1; a=rsa-sha256; t=1649434994; cv=none;
	d=google.com; s=arc-20160816;
	b=JG7pcR0A4vyn2iIwgkz6OuBImpX4VD3OHlh+ypbQsZqDC4h9I3BqFpG6ptCPOyRYzQ
	T/SjayS8p9bvjq2ykJm7fie5oGBfa63ZOZ3hJmu+VmNDd1ozKp0hjLVm+IJjxeo3dVnU
	rJREayvpc3w7xjJp7okcuw2/BfoaSRcmTB5RyKtuaHxc96ZUDtDim5nUIUVsrMY+v/UV
	vQ188/hB/xJ5UaHmhWM9IBsTOVXRrzGy5WjJgqyWdq/PL+Ds3RH9CYKXQgA8/JGFejnV
	YJ1EYxxF8Zgz/d1Hs1MzP8tivJrbGIax8khcRnCBWqXCKVjnRiaZXalu5Es9n8CbYChy
	iKiQ==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com;
	s=arc-20160816;
	h=content-transfer-encoding:mime-version:references:in-reply-to
	:message-id:date:subject:cc:to:from:dkim-signature;
	bh=JGCB1sW6LyijUbLjQ0T8cjIYHkAIPaRA2Df2SDrEzx4=;
	b=XGX74qQUwjlIQSd8903E+b/VAwwjWFMS37gtbje2LhI2s3bZN9cpkTT70kZpFBLUuP
	jr9noSsXckFeJBdRgf9617H8wA3epl5TsbiOH+Mo43aEaSjVg50n2IX7FUmkRWfhTBjD
	DDtzSkmvCP21ym3nee/eNeAQdVgApW6T1QpT75clveDU+obMIP90J6li71QmLFQ8rdNu
	zX8UFxpPgzKhNh9gRUfpFlMgrPf2WKzO60uu6+iVWXVZwkib9VlPeiW8XfVyA5d396c0
	hwdCvBuAjoDSuef4xr1EAXN910OA+AxIunf2NZRRNmRY/xtCng2zHNrLu6dQWbIRWZXX
	6DEA==
ARC-Authentication-Results: i=1; mx.google.com;
	dkim=pass header.i=@amarulasolutions.com header.s=google
	header.b="AUwD0c/H";
	spf=pass (google.com: domain of jagan@amarulasolutions.com designates
	209.85.220.41 as permitted sender)
	smtp.mailfrom=jagan@amarulasolutions.com;
	dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com
Received: from mail-sor-f41.google.com (mail-sor-f41.google.com.
	[209.85.220.41]) by mx.google.com with SMTPS id
	x189-20020a6386c6000000b003994e333c4esor996446pgd.8.2022.04.08.09.23.14
	for <linux-amarula@amarulasolutions.com>
	(Google Transport Security); Fri, 08 Apr 2022 09:23:14 -0700 (PDT)
Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com
	designates 209.85.220.41 as permitted sender)
	client-ip=209.85.220.41;
X-Received: by 2002:a63:9d07:0:b0:398:9594:a48f with SMTP id
	i7-20020a639d07000000b003989594a48fmr16365061pgd.51.1649434993731;
	Fri, 08 Apr 2022 09:23:13 -0700 (PDT)
Received: from j-ThinkPad-E14-Gen-2.domain.name ([45.249.78.214])
	by smtp.gmail.com with ESMTPSA id
	n18-20020a056a0007d200b004fdac35672fsm24929863pfu.68.2022.04.08.09.23.05
	(version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);
	Fri, 08 Apr 2022 09:23:13 -0700 (PDT)
From: Jagan Teki <jagan@amarulasolutions.com>
To: Andrzej Hajda <andrzej.hajda@intel.com>, Inki Dae <inki.dae@samsung.com>,
	Marek Szyprowski <m.szyprowski@samsung.com>,
	Joonyoung Shim <jy0922.shim@samsung.com>,
	Seung-Woo Kim <sw0312.kim@samsung.com>,
	Kyungmin Park <kyungmin.park@samsung.com>,
	Frieder Schrempf <frieder.schrempf@kontron.de>,
	Fancy Fang <chen.fang@nxp.com>, Tim Harvey <tharvey@gateworks.com>,
	Michael Nazzareno Trimarchi <michael@amarulasolutions.com>,
	Adam Ford <aford173@gmail.com>, Neil Armstrong <narmstrong@baylibre.com>,
	Robert Foss <robert.foss@linaro.org>,
	Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
	Rob Herring <robh+dt@kernel.org>
Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
	linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	NXP Linux Team <linux-imx@nxp.com>,
	linux-amarula <linux-amarula@amarulasolutions.com>,
	Jagan Teki <jagan@amarulasolutions.com>
Subject: [PATCH 08/11] drm: bridge: samsung-dsim: Add
	atomic_get_input_bus_fmts
Date: Fri,  8 Apr 2022 21:51:05 +0530
Message-Id: <20220408162108.184583-9-jagan@amarulasolutions.com>
X-Mailer: git-send-email 2.25.1
In-Reply-To: <20220408162108.184583-1-jagan@amarulasolutions.com>
References: <20220408162108.184583-1-jagan@amarulasolutions.com>
MIME-Version: 1.0
X-Original-Sender: jagan@amarulasolutions.com
X-Original-Authentication-Results: mx.google.com;       dkim=pass
	header.i=@amarulasolutions.com header.s=google header.b="AUwD0c/H";
	spf=pass (google.com: domain of jagan@amarulasolutions.com designates
	209.85.220.41 as permitted sender)
	smtp.mailfrom=jagan@amarulasolutions.com;
	dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com
Content-Type: text/plain; charset="UTF-8"
Precedence: list
Mailing-list: list linux-amarula@amarulasolutions.com;
	contact linux-amarula+owners@amarulasolutions.com
List-ID: <linux-amarula.amarulasolutions.com>
X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com
X-Google-Group-Id: 476853432473
List-Post: 
 <https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/post>,
	<mailto:linux-amarula@amarulasolutions.com>
List-Help: 
 <https://support.google.com/a/amarulasolutions.com/bin/topic.py?topic=25838>,
	<mailto:linux-amarula+help@amarulasolutions.com>
List-Archive: 
 <https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/>
List-Unsubscribe: 
 <mailto:googlegroups-manage+476853432473+unsubscribe@googlegroups.com>,
	<https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/subscribe>

Finding the right input bus format throughout the pipeline is hard
so add atomic_get_input_bus_fmts callback and initialize with the
default RGB888_1X24 bus format on DSI-end.

This format can be used in pipeline for negotiating bus format between
the DSI-end of this bridge and the other component closer to pipeline
components.

v1:
* new patch

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/gpu/drm/bridge/samsung-dsim.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index 38db1f93ed51..02802526f82f 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -1338,6 +1338,32 @@ static void samsung_dsim_atomic_post_disable(struct drm_bridge *bridge,
 	pm_runtime_put_sync(dsi->dev);
 }
 
+#define MAX_INPUT_SEL_FORMATS	1
+
+static u32 *
+samsung_dsim_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
+				       struct drm_bridge_state *bridge_state,
+				       struct drm_crtc_state *crtc_state,
+				       struct drm_connector_state *conn_state,
+				       u32 output_fmt,
+				       unsigned int *num_input_fmts)
+{
+	u32 *input_fmts;
+
+	*num_input_fmts = 0;
+
+	input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
+			     GFP_KERNEL);
+	if (!input_fmts)
+		return NULL;
+
+	/* This is the DSI-end bus format */
+	input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
+	*num_input_fmts = 1;
+
+	return input_fmts;
+}
+
 static int samsung_dsim_atomic_check(struct drm_bridge *bridge,
 				     struct drm_bridge_state *bridge_state,
 				     struct drm_crtc_state *crtc_state,
@@ -1372,6 +1398,7 @@ static const struct drm_bridge_funcs samsung_dsim_bridge_funcs = {
 	.atomic_duplicate_state		= drm_atomic_helper_bridge_duplicate_state,
 	.atomic_destroy_state		= drm_atomic_helper_bridge_destroy_state,
 	.atomic_reset			= drm_atomic_helper_bridge_reset,
+	.atomic_get_input_bus_fmts	= samsung_dsim_atomic_get_input_bus_fmts,
 	.atomic_check			= samsung_dsim_atomic_check,
 	.atomic_pre_enable		= samsung_dsim_atomic_pre_enable,
 	.atomic_enable			= samsung_dsim_atomic_enable,

From patchwork Fri Apr  8 16:21:06 2022
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
X-Patchwork-Submitter: Jagan Teki <jagan@amarulasolutions.com>
X-Patchwork-Id: 1910
Return-Path: 
 <linux-amarula+bncBD7MFH7A7EEBB6WCYGJAMGQETFQTR5A@amarulasolutions.com>
X-Original-To: linux-amarula@patchwork.amarulasolutions.com
Delivered-To: linux-amarula@patchwork.amarulasolutions.com
Received: from mail-pf1-f199.google.com (mail-pf1-f199.google.com
	[209.85.210.199])
	by ganimede.amarulasolutions.com (Postfix) with ESMTPS id E9FF63F0D5
	for <linux-amarula@patchwork.amarulasolutions.com>;
	Fri,  8 Apr 2022 18:23:23 +0200 (CEST)
Received: by mail-pf1-f199.google.com with SMTP id
	m8-20020a62a208000000b0050593296139sf429866pff.1
	for <linux-amarula@patchwork.amarulasolutions.com>;
	Fri, 08 Apr 2022 09:23:23 -0700 (PDT)
ARC-Seal: i=2; a=rsa-sha256; t=1649435002; cv=pass;
	d=google.com; s=arc-20160816;
	b=KFIKpqjGUuJMnfgYpnp0xbln+stHFk9YqAKUkJd3Di1OjaJrH+Hu0Cr2kzwR00BtXI
	lPKUZFB4EvySAV2kId5OaqBPNEUMVT6qCD55UOchS5VltEEzsunT/QpsbXDBI0TzxVRT
	c4eZOszG1BInGx1kFYylhTEHqrPLW3S/f/j5DKc0Mx/6xB3SsgoYSTGOfQ44GUM87gjb
	bTVbfGklHGSobLDKIo30ET6HdDmxxg/dSCWaWlD07sRvPVzEwHrPSGENVjDcHiZZjeex
	nR7MzAeTIaUFG4Lg+poySzRGmndbc474MhVjWoo4HH+xWq/1nGfLCcpuqsgGFS6EOin8
	7Qwg==
ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com;
	s=arc-20160816;
	h=list-unsubscribe:list-archive:list-help:list-post:list-id
	:mailing-list:precedence:mime-version:references:in-reply-to
	:message-id:date:subject:cc:to:from:dkim-signature;
	bh=FlCJyaKC9fMT8kp7Crw140do3N/F0aq0mN0bd+d34F0=;
	b=ksoXtRUPMCkc3rOg0m+UgDIZLIONWifIP3W++C+6f01nGhkFQmYJmnMXKqEL3wWuxu
	Erl6t30TEhws7EWMWCUII1n3Xb072X7G/YKVtpq1yopA0HxyeGOdO5DibRdVr82OTuqo
	YhG8KDXAwjRoL7fnXaDpesnvv1xQ3NKJnF2QoMTx2V75wUGIjD43JAtG4xct8hYck99w
	57bQPt+aiDuMK9Z2/TOv/zh/7jUaPifmHTRZOgRxS+6Gt4DYphCmt71LCIg2BVCPwpqV
	MkL+0jT7t9Zjqy0B4BdVyIRryaWIlFYV+RajM0GNRSYg/daPw4nUQrCCTJRN/JVRkm+Z
	GeMw==
ARC-Authentication-Results: i=2; mx.google.com;
	dkim=pass header.i=@amarulasolutions.com header.s=google
	header.b=GEYKFzIc;
	spf=pass (google.com: domain of jagan@amarulasolutions.com designates
	209.85.220.41 as permitted sender)
	smtp.mailfrom=jagan@amarulasolutions.com;
	dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
	d=amarulasolutions.com; s=google;
	h=from:to:cc:subject:date:message-id:in-reply-to:references
	:mime-version:x-original-sender:x-original-authentication-results
	:precedence:mailing-list:list-id:list-post:list-help:list-archive
	:list-unsubscribe;
	bh=FlCJyaKC9fMT8kp7Crw140do3N/F0aq0mN0bd+d34F0=;
	b=kNk9s7HIL73iDZGyJpt6lm6iQw46JfvtVEfd1IkJuvtWkPGkQ6XFUUxB2T8gpGeS4R
	GsbDLgv8L67pJ8Xuj/X8No7D8C/HT9oSpoVvMzP+FGF/yLhOrEkJ+TuUKhMsacISjTM7
	4hCEpezj7B/9oBFfJrI4ik/SLe3OsGj0ZPT7A=
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
	d=1e100.net; s=20210112;
	h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to
	:references:mime-version:x-original-sender
	:x-original-authentication-results:precedence:mailing-list:list-id
	:x-spam-checked-in-group:list-post:list-help:list-archive
	:list-unsubscribe;
	bh=FlCJyaKC9fMT8kp7Crw140do3N/F0aq0mN0bd+d34F0=;
	b=mqYV2RJ4wcV9+Cf/kYuN9Kff6ML723MBM3oawN16IDYIhXQ3X4LUoFkh6uoVkjqIzo
	ikwa2OpgOWomnr2F538IzKjm6+uj2zgUoSKBOuqG7rVGYwiB+Ekto7gDhXyGOIPTtPL+
	vEVrbIN8Gh49i5m7FctZn0q5Oc27MqziWn/yTD2OjD7k57L/OSbetkiX+kPCy3SkIF6B
	gq/mwzeDirBzJI9TlchyqSbf3107Mv8SJ2xFomKbwr2a6CqB3SdRNtybWvKRiugk1+BX
	MEnWhNhmzldX4xBU2+pk8YTiDeuYyVwWzfHZnjpjwjogsNCkQf6WMfYmEOc9h7d0RvZt
	DSnw==
X-Gm-Message-State: AOAM530j+hgnYSXdbo/aMfgB/bd+cOrFGHP71GzbVe2KSIduwWXCn8Q0
	O6nedhVbfxSvZ5+TBRCpfCAhKGWx
X-Google-Smtp-Source: 
 ABdhPJxRpVR9cRuzaeFQmoToXbFNa2qlXZVUlHXLOORiFNEJB7MIVGtzaDtLbnNHEPUmbLK6hdPilg==
X-Received: by 2002:a05:6a00:1395:b0:505:6fc9:3525 with SMTP id
	t21-20020a056a00139500b005056fc93525mr7203994pfg.38.1649435002780;
	Fri, 08 Apr 2022 09:23:22 -0700 (PDT)
X-BeenThere: linux-amarula@amarulasolutions.com
Received: by 2002:a17:903:22c1:b0:155:efc1:1565 with SMTP id
	y1-20020a17090322c100b00155efc11565ls2225323plg.3.gmail;
	Fri, 08 Apr 2022 09:23:22 -0700 (PDT)
X-Received: by 2002:a17:903:249:b0:153:857c:a1fe with SMTP id
	j9-20020a170903024900b00153857ca1femr20155854plh.44.1649435002097;
	Fri, 08 Apr 2022 09:23:22 -0700 (PDT)
ARC-Seal: i=1; a=rsa-sha256; t=1649435002; cv=none;
	d=google.com; s=arc-20160816;
	b=JnRXeEFLoQF0yfFQPJN4A57s5PLkGJwz2KUeWKJFYOrQ8+J0kSyyXQP8zanU18dCqZ
	I25DMEyTGqhWZxkgdpB2MkCsLj0e3aZj0NRCqu/HCMwbV9amHUPU8yzwBepxsCCV+Eeh
	JFEDqICRkav8JsUcGDYjQ0M9aNa+TCoE0hUdBRm3vgpbobEL+DCjYpn7PMkt3t1Nxibc
	q74bjt+GfssY8BSD0D2Ja+HyzTxf0sXrv02u2xB4jV3zDP/jZqx94oMJ9TURG4muvKRD
	jaZtJFFDuzWupKB+MxNuAgJqBYOtMAUv0xmxgOXZhbJ1H5fLr50mOOiKKTsMpPLOc+4y
	Gf3g==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com;
	s=arc-20160816;
	h=content-transfer-encoding:mime-version:references:in-reply-to
	:message-id:date:subject:cc:to:from:dkim-signature;
	bh=lhe1gjfVmNBzu+OAJh4OI2ThwckJvfBSRTmYzb4Lz0s=;
	b=i/R0+5E9+nGC3Zpuar79wf2zTZkHxp4LhIohcYp9R+CBZvK77gs4L5ccrOxxqLmJUs
	cEtJw91BlhNAo38VLHh1OEXWlgEEv6GDYdRZqa1+e/jWZezyHW+MOPhi20uco+cZmDDE
	JlSP+pKyWqnJZ8AhdU2WPvmylv2x8+2Q/UsEW1WJeHh0OaiyfATGWDnWQckjdcedEFKu
	+as1WpuANFudQ0+nE5J55clLmTEPAtPDDt7ZxyNSq7jZqhxmtrgoRIjlTlzqHERyScDi
	ccDAuafOOngEdK6R/NL7HhV1o8qgA3wfIhGND4kYo70RphnunNFHpxePnJeHhxkxYSK8
	G7Pw==
ARC-Authentication-Results: i=1; mx.google.com;
	dkim=pass header.i=@amarulasolutions.com header.s=google
	header.b=GEYKFzIc;
	spf=pass (google.com: domain of jagan@amarulasolutions.com designates
	209.85.220.41 as permitted sender)
	smtp.mailfrom=jagan@amarulasolutions.com;
	dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com
Received: from mail-sor-f41.google.com (mail-sor-f41.google.com.
	[209.85.220.41]) by mx.google.com with SMTPS id
	12-20020a17090a198c00b001caf31405d6sor742965pji.32.2022.04.08.09.23.22
	for <linux-amarula@amarulasolutions.com>
	(Google Transport Security); Fri, 08 Apr 2022 09:23:22 -0700 (PDT)
Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com
	designates 209.85.220.41 as permitted sender)
	client-ip=209.85.220.41;
X-Received: by 2002:a17:90a:c302:b0:1bd:14ff:15 with SMTP id
	g2-20020a17090ac30200b001bd14ff0015mr22844531pjt.19.1649435001831;
	Fri, 08 Apr 2022 09:23:21 -0700 (PDT)
Received: from j-ThinkPad-E14-Gen-2.domain.name ([45.249.78.214])
	by smtp.gmail.com with ESMTPSA id
	n18-20020a056a0007d200b004fdac35672fsm24929863pfu.68.2022.04.08.09.23.14
	(version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);
	Fri, 08 Apr 2022 09:23:21 -0700 (PDT)
From: Jagan Teki <jagan@amarulasolutions.com>
To: Andrzej Hajda <andrzej.hajda@intel.com>, Inki Dae <inki.dae@samsung.com>,
	Marek Szyprowski <m.szyprowski@samsung.com>,
	Joonyoung Shim <jy0922.shim@samsung.com>,
	Seung-Woo Kim <sw0312.kim@samsung.com>,
	Kyungmin Park <kyungmin.park@samsung.com>,
	Frieder Schrempf <frieder.schrempf@kontron.de>,
	Fancy Fang <chen.fang@nxp.com>, Tim Harvey <tharvey@gateworks.com>,
	Michael Nazzareno Trimarchi <michael@amarulasolutions.com>,
	Adam Ford <aford173@gmail.com>, Neil Armstrong <narmstrong@baylibre.com>,
	Robert Foss <robert.foss@linaro.org>,
	Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
	Rob Herring <robh+dt@kernel.org>
Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
	linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	NXP Linux Team <linux-imx@nxp.com>,
	linux-amarula <linux-amarula@amarulasolutions.com>,
	Jagan Teki <jagan@amarulasolutions.com>
Subject: [PATCH 09/11] drm: bridge: samsung-dsim: Add input_bus_flags
Date: Fri,  8 Apr 2022 21:51:06 +0530
Message-Id: <20220408162108.184583-10-jagan@amarulasolutions.com>
X-Mailer: git-send-email 2.25.1
In-Reply-To: <20220408162108.184583-1-jagan@amarulasolutions.com>
References: <20220408162108.184583-1-jagan@amarulasolutions.com>
MIME-Version: 1.0
X-Original-Sender: jagan@amarulasolutions.com
X-Original-Authentication-Results: mx.google.com;       dkim=pass
	header.i=@amarulasolutions.com header.s=google header.b=GEYKFzIc;
	spf=pass (google.com: domain of jagan@amarulasolutions.com designates
	209.85.220.41 as permitted sender)
	smtp.mailfrom=jagan@amarulasolutions.com;
	dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com
Content-Type: text/plain; charset="UTF-8"
Precedence: list
Mailing-list: list linux-amarula@amarulasolutions.com;
	contact linux-amarula+owners@amarulasolutions.com
List-ID: <linux-amarula.amarulasolutions.com>
X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com
X-Google-Group-Id: 476853432473
List-Post: 
 <https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/post>,
	<mailto:linux-amarula@amarulasolutions.com>
List-Help: 
 <https://support.google.com/a/amarulasolutions.com/bin/topic.py?topic=25838>,
	<mailto:linux-amarula+help@amarulasolutions.com>
List-Archive: 
 <https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/>
List-Unsubscribe: 
 <mailto:googlegroups-manage+476853432473+unsubscribe@googlegroups.com>,
	<https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/subscribe>

eLCDIF is expecting to have input_bus_flags as DE_LOW in order to
set active low during valid data transfer on each horizontal line.

Add DE_LOW flag via drm bridge timings.

v1:
* none

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/gpu/drm/bridge/samsung-dsim.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index 02802526f82f..71bbaf19f530 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -1543,6 +1543,10 @@ __weak void samsung_dsim_plat_remove(struct samsung_dsim *priv)
 {
 }
 
+static const struct drm_bridge_timings samsung_dsim_bridge_timings = {
+	.input_bus_flags = DRM_BUS_FLAG_DE_LOW,
+};
+
 static int samsung_dsim_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
@@ -1622,6 +1626,7 @@ static int samsung_dsim_probe(struct platform_device *pdev)
 
 	dsi->bridge.funcs = &samsung_dsim_bridge_funcs;
 	dsi->bridge.of_node = dev->of_node;
+	dsi->bridge.timings = &samsung_dsim_bridge_timings;
 	dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
 
 	if (dsi->driver_data->platform_init) {

From patchwork Fri Apr  8 16:21:07 2022
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
X-Patchwork-Submitter: Jagan Teki <jagan@amarulasolutions.com>
X-Patchwork-Id: 1911
Return-Path: 
 <linux-amarula+bncBD7MFH7A7EEBBA6DYGJAMGQEZJFBBCY@amarulasolutions.com>
X-Original-To: linux-amarula@patchwork.amarulasolutions.com
Delivered-To: linux-amarula@patchwork.amarulasolutions.com
Received: from mail-pg1-f198.google.com (mail-pg1-f198.google.com
	[209.85.215.198])
	by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 765E03F0D5
	for <linux-amarula@patchwork.amarulasolutions.com>;
	Fri,  8 Apr 2022 18:23:32 +0200 (CEST)
Received: by mail-pg1-f198.google.com with SMTP id
	z2-20020a63c042000000b0039963a0efffsf5056658pgi.4
	for <linux-amarula@patchwork.amarulasolutions.com>;
	Fri, 08 Apr 2022 09:23:32 -0700 (PDT)
ARC-Seal: i=2; a=rsa-sha256; t=1649435011; cv=pass;
	d=google.com; s=arc-20160816;
	b=Qsr3i+C7NXRCAc/G2qkm1x7A78XMp+sHoJmpsfcozJgTXBnyuTTtiuPdagMTZ5ut7a
	u4xO/FK+cffzHQ8g1ukdcKL/P2IPZwYzgFLwM3toDgEyhAkgXSKRsez3nDBmDBMfAKMH
	EqfwpTisNHd2lG3EnP/pX8a+Aoxb9xtml1RxyjDAz8RX+S2h43g2hgIGFG2avQBi16kH
	cQ/zJCyqDM2gnDTJhAKYudcbfrzHpPZUc/opuArs14GjMu4FuWSxULM7WhAqVpbUYLCK
	kDbWQPobZZSGv1bfASay7c4qVzD59QWY1LWhfkqMowa/nZO9MiKlVGiUdpIyIOF0Lihq
	+HAA==
ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com;
	s=arc-20160816;
	h=list-unsubscribe:list-archive:list-help:list-post:list-id
	:mailing-list:precedence:mime-version:references:in-reply-to
	:message-id:date:subject:cc:to:from:dkim-signature;
	bh=svlnwASDvGhE/TK8PISbvauU7i8w/ScNHzKqyg5XFAY=;
	b=IZhj+1/lBNAY6N9GH10Z6xjRpEnjaPT8xN6WgdVn/LWGwllyQfm7UcUSgACTungtj3
	SmuXTvZhxI9M1ShxPjFk5zlTPi5fmJ0Y2k79qbeXhC1VIeX0teNp4P3+PwW+S7uvDjqZ
	hAz5DFx4ALC/JsWuox8adaRbBG/vsEz/voheWl6n/Yh74K+kAhlqOjhp4y8a4gWuYBX0
	TZ7eo8pHAcU7LJEHd6lYgM8slktzswXN1JKQHlda9dJ5dFXY4AGFT2mKiziKk+ldikFd
	nhdEuhvQrgmOnsNd0l1LyF6PO7cryq5+SRM43UQ5NO/Ih3lzJxfhKLgk2voGSPU03qlh
	N9sA==
ARC-Authentication-Results: i=2; mx.google.com;
	dkim=pass header.i=@amarulasolutions.com header.s=google
	header.b="l/g4lICQ";
	spf=pass (google.com: domain of jagan@amarulasolutions.com designates
	209.85.220.41 as permitted sender)
	smtp.mailfrom=jagan@amarulasolutions.com;
	dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
	d=amarulasolutions.com; s=google;
	h=from:to:cc:subject:date:message-id:in-reply-to:references
	:mime-version:x-original-sender:x-original-authentication-results
	:precedence:mailing-list:list-id:list-post:list-help:list-archive
	:list-unsubscribe;
	bh=svlnwASDvGhE/TK8PISbvauU7i8w/ScNHzKqyg5XFAY=;
	b=OoWIYaYQlpOOcUm9IpuUXn8/5BvEtcRpQuF8tLxhb/axY/P3J/cW7h3GeEtCC9JWPq
	uZKtD4IHcoAxEvkVfZmW3Cj2PZkBHtFmsV2v0buUxA+3NyV1c5W3tCSbtCgH7EfPiyPA
	Q2uVgn3lIfmgGu4YByX9bsMAYVwrRr0/9t4Y0=
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
	d=1e100.net; s=20210112;
	h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to
	:references:mime-version:x-original-sender
	:x-original-authentication-results:precedence:mailing-list:list-id
	:x-spam-checked-in-group:list-post:list-help:list-archive
	:list-unsubscribe;
	bh=svlnwASDvGhE/TK8PISbvauU7i8w/ScNHzKqyg5XFAY=;
	b=EDZE7cYHIiPalYRwkivP4bfqCC4dnhpjQR7xv10ExhiRAj2FAtmQ4VT0f+zsaQf+7x
	Tz1nqdCrhp1tcSZ6FjbaJrSyiS4mUr3AwAfEVV3iT87Fh9lakNExWfrWtwvq1Aku3URK
	4llqSiYHdkLizSV/maa63Xoi1bhynjQxAJ+iY32hoadlbMiC+5XTSwwG2Q26d7zv9Xx+
	+bexGxGolMro2Tr3NBlv/G0auXWISggz10bbR+2bBrYK0Cg3XUF20qZRaHMggbAqeGDg
	3CY+kocJiWPYjEgAOuU/CAjPdf9SqCTj8n6Q77K9psQnAmAnxy70WFlzHcV836eg7bqa
	pGEA==
X-Gm-Message-State: AOAM533rEa4FlYINYjHdALYgE0/4V3q6H7IhddgAtapjVr9kjL8iIT+F
	7H7O1/twA05qBYpFOzcZA0V8wFW0
X-Google-Smtp-Source: 
 ABdhPJwresVPtUPq/xSkLS2EuulMwHubeNUI249XKF1zsAgcY617c/Ohg9r279Io/QAgiDlV5qCtdQ==
X-Received: by 2002:a63:c04e:0:b0:39d:f8f:200d with SMTP id
	z14-20020a63c04e000000b0039d0f8f200dmr1223337pgi.10.1649435011291;
	Fri, 08 Apr 2022 09:23:31 -0700 (PDT)
X-BeenThere: linux-amarula@amarulasolutions.com
Received: by 2002:a17:90a:6782:b0:1b9:7c8a:8c03 with SMTP id
	o2-20020a17090a678200b001b97c8a8c03ls2086495pjj.0.gmail;
	Fri, 08 Apr 2022 09:23:30 -0700 (PDT)
X-Received: by 2002:a17:902:f544:b0:153:bb8a:9374 with SMTP id
	h4-20020a170902f54400b00153bb8a9374mr20657550plf.154.1649435010578;
	Fri, 08 Apr 2022 09:23:30 -0700 (PDT)
ARC-Seal: i=1; a=rsa-sha256; t=1649435010; cv=none;
	d=google.com; s=arc-20160816;
	b=EnoXQAN/+bui2SBDyq4g4pz0dyptUwpqM1vaAK8nedWSALelC84F7Eq8IS6KRHkD7d
	345KCAc7ndyuAMH99zra611hj4znLOtgKZ9UdVhqWrCXSAvV+C6tffjxqKd13l8+Zdea
	/wLmngr43Hsm1FlERhYatlxx8fQR67dGeRvQ+SIGvQfbxUOh6KKTj4W0k5BBFJoMDbUX
	spQe/L6qI6OZOOONmvQhHH37eULu9N6gnUCnwljjtiNlpcSgqJPK3QVReZePrKJ2o9aY
	H21Uvm22uMcy9lZ+sdRxhkApTVpVtN7buTfPQz26c0FKt2DQTPB33xqFpX1Y18KbK/Sp
	EGqQ==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com;
	s=arc-20160816;
	h=content-transfer-encoding:mime-version:references:in-reply-to
	:message-id:date:subject:cc:to:from:dkim-signature;
	bh=zevXHTigISY3S4Y7YWLt05sAPhFkf3znQwcUqUtkS7M=;
	b=D5pjUV74HOEPkRygJ0pX4ECNvzde51OVv3KAlg1mHTjDD5lbisVAyZuagnJgUFmIia
	g+UROtIj4RAXZY7GNfdwOmK15Ej1K6s+iiqLY556ECsTooQIPY/xjHJXO7aWdoOgETvA
	TpFEis6vUmkkL06cIBRrK6Xktk+2fMRXdO0hzWwRThe6M3QlTRTApMdlQaEPT5iZNAX7
	IMZ4XvDu0INiDjeW7irufqxNq0zfAXG+D0NZ5Ba1diM0HRRd4OnKbMiuEpOgi60C9rFZ
	xYqx2jf+6kM1ci+5YfTvzYhne6XstQjdAtB+nBuJ5bSFsPJ6LdcsTW+e4oXZhlpIy8hr
	xVqw==
ARC-Authentication-Results: i=1; mx.google.com;
	dkim=pass header.i=@amarulasolutions.com header.s=google
	header.b="l/g4lICQ";
	spf=pass (google.com: domain of jagan@amarulasolutions.com designates
	209.85.220.41 as permitted sender)
	smtp.mailfrom=jagan@amarulasolutions.com;
	dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com
Received: from mail-sor-f41.google.com (mail-sor-f41.google.com.
	[209.85.220.41]) by mx.google.com with SMTPS id
	w2-20020a17090ac98200b001c62fb0ed2csor2335468pjt.35.2022.04.08.09.23.30
	for <linux-amarula@amarulasolutions.com>
	(Google Transport Security); Fri, 08 Apr 2022 09:23:30 -0700 (PDT)
Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com
	designates 209.85.220.41 as permitted sender)
	client-ip=209.85.220.41;
X-Received: by 2002:a17:90b:1805:b0:1c7:ba88:9550 with SMTP id
	lw5-20020a17090b180500b001c7ba889550mr22875005pjb.16.1649435010210;
	Fri, 08 Apr 2022 09:23:30 -0700 (PDT)
Received: from j-ThinkPad-E14-Gen-2.domain.name ([45.249.78.214])
	by smtp.gmail.com with ESMTPSA id
	n18-20020a056a0007d200b004fdac35672fsm24929863pfu.68.2022.04.08.09.23.22
	(version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);
	Fri, 08 Apr 2022 09:23:29 -0700 (PDT)
From: Jagan Teki <jagan@amarulasolutions.com>
To: Andrzej Hajda <andrzej.hajda@intel.com>, Inki Dae <inki.dae@samsung.com>,
	Marek Szyprowski <m.szyprowski@samsung.com>,
	Joonyoung Shim <jy0922.shim@samsung.com>,
	Seung-Woo Kim <sw0312.kim@samsung.com>,
	Kyungmin Park <kyungmin.park@samsung.com>,
	Frieder Schrempf <frieder.schrempf@kontron.de>,
	Fancy Fang <chen.fang@nxp.com>, Tim Harvey <tharvey@gateworks.com>,
	Michael Nazzareno Trimarchi <michael@amarulasolutions.com>,
	Adam Ford <aford173@gmail.com>, Neil Armstrong <narmstrong@baylibre.com>,
	Robert Foss <robert.foss@linaro.org>,
	Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
	Rob Herring <robh+dt@kernel.org>
Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
	linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	NXP Linux Team <linux-imx@nxp.com>,
	linux-amarula <linux-amarula@amarulasolutions.com>,
	Jagan Teki <jagan@amarulasolutions.com>
Subject: [PATCH 10/11] dt-bindings: display: exynos: dsim: Add NXP i.MX8MM
	support
Date: Fri,  8 Apr 2022 21:51:07 +0530
Message-Id: <20220408162108.184583-11-jagan@amarulasolutions.com>
X-Mailer: git-send-email 2.25.1
In-Reply-To: <20220408162108.184583-1-jagan@amarulasolutions.com>
References: <20220408162108.184583-1-jagan@amarulasolutions.com>
MIME-Version: 1.0
X-Original-Sender: jagan@amarulasolutions.com
X-Original-Authentication-Results: mx.google.com;       dkim=pass
	header.i=@amarulasolutions.com header.s=google header.b="l/g4lICQ";
	spf=pass (google.com: domain of jagan@amarulasolutions.com designates
	209.85.220.41 as permitted sender)
	smtp.mailfrom=jagan@amarulasolutions.com;
	dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com
Content-Type: text/plain; charset="UTF-8"
Precedence: list
Mailing-list: list linux-amarula@amarulasolutions.com;
	contact linux-amarula+owners@amarulasolutions.com
List-ID: <linux-amarula.amarulasolutions.com>
X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com
X-Google-Group-Id: 476853432473
List-Post: 
 <https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/post>,
	<mailto:linux-amarula@amarulasolutions.com>
List-Help: 
 <https://support.google.com/a/amarulasolutions.com/bin/topic.py?topic=25838>,
	<mailto:linux-amarula+help@amarulasolutions.com>
List-Archive: 
 <https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/>
List-Unsubscribe: 
 <mailto:googlegroups-manage+476853432473+unsubscribe@googlegroups.com>,
	<https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/subscribe>

Samsung MIPI DSIM bridge can also be found in i.MX8MM/i.MX8MN SoC.

Add dt-bingings for it.

v1:
* new patch

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt b/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
index be377786e8cd..5133d4d39190 100644
--- a/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
+++ b/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
@@ -7,6 +7,7 @@ Required properties:
 		"samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */
 		"samsung,exynos5422-mipi-dsi" /* for Exynos5422/5800 SoCs */
 		"samsung,exynos5433-mipi-dsi" /* for Exynos5433 SoCs */
+		"fsl,imx8mm-mipi-dsim" /* for i.MX8M Mini/Nano SoCs */
   - reg: physical base address and length of the registers set for the device
   - interrupts: should contain DSI interrupt
   - clocks: list of clock specifiers, must contain an entry for each required

From patchwork Fri Apr  8 16:21:08 2022
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
X-Patchwork-Submitter: Jagan Teki <jagan@amarulasolutions.com>
X-Patchwork-Id: 1912
Return-Path: 
 <linux-amarula+bncBD7MFH7A7EEBBC6DYGJAMGQEXIBDNCY@amarulasolutions.com>
X-Original-To: linux-amarula@patchwork.amarulasolutions.com
Delivered-To: linux-amarula@patchwork.amarulasolutions.com
Received: from mail-pl1-f198.google.com (mail-pl1-f198.google.com
	[209.85.214.198])
	by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 49A1F3F0D5
	for <linux-amarula@patchwork.amarulasolutions.com>;
	Fri,  8 Apr 2022 18:23:40 +0200 (CEST)
Received: by mail-pl1-f198.google.com with SMTP id
	j1-20020a170903028100b0014b1f9e0068sf4708411plr.8
	for <linux-amarula@patchwork.amarulasolutions.com>;
	Fri, 08 Apr 2022 09:23:40 -0700 (PDT)
ARC-Seal: i=2; a=rsa-sha256; t=1649435019; cv=pass;
	d=google.com; s=arc-20160816;
	b=pG5RsRXD13eB2tpo1LoBZgNXoOsZiUBTRcGDvDX64eDLcJgVoqAnQl+LdefO8IPsWo
	tp43IACXs8douA8Z56IYTVIarnIqRJqolj/f2iBKirp9Ih3N/8KJZoDq5DcMjZKL8hhC
	o4FqVc1aihF5Fvh5BMuorGqDs98t3fDTrV8J7v9Rgua/C6qav7VRy97kP7Rxmj+QB+96
	M4nsYhUu9ao+VvbmBPZQjFSaG41opxiEbcPnNFjJB5F9WUOov23gbWqC2iWjTgwb+kXW
	uWMb49mNGPij4LfoEgj0hofpGlzHY2/IVGJaHQJSEM7SpEls0dNzbQvjkWPesLDE1L7B
	VkzQ==
ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com;
	s=arc-20160816;
	h=list-unsubscribe:list-archive:list-help:list-post:list-id
	:mailing-list:precedence:mime-version:references:in-reply-to
	:message-id:date:subject:cc:to:from:dkim-signature;
	bh=2yW7P6S0XkPG8+LwSPYMBNnwGBbKFUr7cOasxMz7OYs=;
	b=Kfe8cWw7rAsR5tGS+Gz1MCtx3zdBfNVca/UJxnoeYd19S45HIdGPa0+1h34B9DwqCM
	hJbt3B39HGXRk+LAU9Gu5PuBZ2QW5Rf//6Kuj0nKlPPspAPcDKsVMKay4YVV4wwdxQcb
	fJMqb8Ro3SPRh7tX5aR01GZYqFAy2rw/h8CR7c5YUUOcB5f13Q+u7CFsaaNJ29ZGROtl
	xdLzxtJjnfhOr/2usDbOWN9XVN0FVOVcBAExGb71AJUKKD+m5hhZaaRX+nUkHil80Iuc
	F67gqUgrsqQPG3PUgtgXTBsQdXX9voqRI/7yH0Na5epO91/i8hR5Qk/fHV9PuGukxWGf
	Ye2A==
ARC-Authentication-Results: i=2; mx.google.com;
	dkim=pass header.i=@amarulasolutions.com header.s=google
	header.b=We3vH+y0;
	spf=pass (google.com: domain of jagan@amarulasolutions.com designates
	209.85.220.41 as permitted sender)
	smtp.mailfrom=jagan@amarulasolutions.com;
	dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
	d=amarulasolutions.com; s=google;
	h=from:to:cc:subject:date:message-id:in-reply-to:references
	:mime-version:x-original-sender:x-original-authentication-results
	:precedence:mailing-list:list-id:list-post:list-help:list-archive
	:list-unsubscribe;
	bh=2yW7P6S0XkPG8+LwSPYMBNnwGBbKFUr7cOasxMz7OYs=;
	b=C86Y4f5ykjj26INQEVKo9PJb8ipwx9mT0ZCEk+HoF1oEAwkIjEZ6O+iWDYzHEU7AoP
	J7x9rx9Lg0/ODokSfq4XsiuMKxg45jWOGqlqQCzY/mVVWhTn0a9uArDc/5aRYveoP7D8
	AiAmoKfR9RyrDRWvrjXDwUMkbckN0qie8Tztk=
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
	d=1e100.net; s=20210112;
	h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to
	:references:mime-version:x-original-sender
	:x-original-authentication-results:precedence:mailing-list:list-id
	:x-spam-checked-in-group:list-post:list-help:list-archive
	:list-unsubscribe;
	bh=2yW7P6S0XkPG8+LwSPYMBNnwGBbKFUr7cOasxMz7OYs=;
	b=Hf/OsYmcHT75fs9EHcWHuUquD5QdEEXQuemyTl6jRGK/eW3UPks0dvEnhrOnKiJ1FC
	p+TTFcOFAuBUNAxR33W4y1Irgv+52tuBpo+kbq5j7c7RLgsl8oTtzCbLI7k5eqdmJnkD
	oraJYI/yTpuTJKKCYzApCXK29ltM+1zyXSCvk2voLT5LiFbdiaaj78tQ3kn7HrZaYm7u
	g4P5AGF8ihqphJO27UbVF2UObeZJ0osWiiH2QkiW4oO1rjTQAnqe9Tn3SDTdbbMfSxpK
	KQdBaFGbmQ1AIRmyF6CBudhy7sDFM8VKH4FpxX4N46ItSgBna/sl06AyZcR1M+z5fhBi
	ERUg==
X-Gm-Message-State: AOAM531du2bHdf5rSt9O2tlswORamgPj0lk5OrV3dcXY16fkBvvsAivn
	83he1Y8+CSzU5qtjz8i289AWHTf3
X-Google-Smtp-Source: 
 ABdhPJyGHR18HLLla488/o/xh1IqMS6NATT7kl6uzD69O2g2RdX45ygC22qYjBDEC+ZY+3EpBbliGQ==
X-Received: by 2002:a17:90a:a416:b0:1ca:b9f8:bcec with SMTP id
	y22-20020a17090aa41600b001cab9f8bcecmr22635200pjp.163.1649435019101;
	Fri, 08 Apr 2022 09:23:39 -0700 (PDT)
X-BeenThere: linux-amarula@amarulasolutions.com
Received: by 2002:a63:7a50:0:b0:398:36ed:d87d with SMTP id
	j16-20020a637a50000000b0039836edd87dls1154103pgn.8.gmail;
	Fri, 08 Apr 2022 09:23:38 -0700 (PDT)
X-Received: by 2002:a63:c015:0:b0:385:fe06:eb86 with SMTP id
	h21-20020a63c015000000b00385fe06eb86mr16026761pgg.132.1649435018392;
	Fri, 08 Apr 2022 09:23:38 -0700 (PDT)
ARC-Seal: i=1; a=rsa-sha256; t=1649435018; cv=none;
	d=google.com; s=arc-20160816;
	b=GIaOvneO1IdlsfJX2iqq20zEVJ4OcG9q2+8DowTpcp8sLbWJ1orjtfDXhCYl0rJpXk
	d3DtGxwgnERyxs3R8JC6a6lzZBCTMww51v0qF2U3WoZmyaLRPuDmcZiYZV/xpHyNhkth
	GLDGfv4kiv+9rLtALo5p4CRSBPlnNuhr6DlrSxsdq6+KMql01vQbT4QahDnzUyeE76O3
	8uAxindUrmZkQgVL4sLdca1Q3ug0XwMJOL+gLysaQTA9aN5sXIdzjfyETeo1CV8w26NK
	bWBcJvsZhv0sS3+KHkwaFWlsbhtvgjGZAlARYbmQaGayFruKJH0/pRUJXp3R4I5s3Omr
	a+rA==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com;
	s=arc-20160816;
	h=content-transfer-encoding:mime-version:references:in-reply-to
	:message-id:date:subject:cc:to:from:dkim-signature;
	bh=7BcGnOMSzwjZFrNXSVlFPVWXXS7lgriFVwZOMf5bb+Q=;
	b=W2bzBdMQ2RsYEs7tRDS7sbASHnw/Q9TA7JjLcCi7MsKdB1hCsTybYLxXwnlIS58uK7
	ghHms5BonKdXxyet1YRy+AoQFvgh0obCp3CypZBrE29LH2lZWCe4qPGXnUeCd5lrjaqn
	i8jz/s6ZiLfENtHVsKKTbPf4ZtY/Vpetec9dKgwRJVS8zwrXrm/frd6zg+rBk/XkYA9W
	LjKxAckdQ+Req8HpaiKSf6eU2gY47Du7JwgCpZ8ltghD3RMjUieyGwECQsM1nxQnqzvc
	EQnw5TvNiWWv3w7DHFn0yjVxVQ7CeYPReNvGJSsFXsWmmfsZ3qFg4u3J7KF/shvscl2m
	8KBA==
ARC-Authentication-Results: i=1; mx.google.com;
	dkim=pass header.i=@amarulasolutions.com header.s=google
	header.b=We3vH+y0;
	spf=pass (google.com: domain of jagan@amarulasolutions.com designates
	209.85.220.41 as permitted sender)
	smtp.mailfrom=jagan@amarulasolutions.com;
	dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com
Received: from mail-sor-f41.google.com (mail-sor-f41.google.com.
	[209.85.220.41]) by mx.google.com with SMTPS id
	k11-20020a170902694b00b001567abfbeadsor661709plt.151.2022.04.08.09.23.38
	for <linux-amarula@amarulasolutions.com>
	(Google Transport Security); Fri, 08 Apr 2022 09:23:38 -0700 (PDT)
Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com
	designates 209.85.220.41 as permitted sender)
	client-ip=209.85.220.41;
X-Received: by 2002:a17:903:2352:b0:155:d4e8:12c6 with SMTP id
	c18-20020a170903235200b00155d4e812c6mr20780844plh.27.1649435018093;
	Fri, 08 Apr 2022 09:23:38 -0700 (PDT)
Received: from j-ThinkPad-E14-Gen-2.domain.name ([45.249.78.214])
	by smtp.gmail.com with ESMTPSA id
	n18-20020a056a0007d200b004fdac35672fsm24929863pfu.68.2022.04.08.09.23.30
	(version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);
	Fri, 08 Apr 2022 09:23:37 -0700 (PDT)
From: Jagan Teki <jagan@amarulasolutions.com>
To: Andrzej Hajda <andrzej.hajda@intel.com>, Inki Dae <inki.dae@samsung.com>,
	Marek Szyprowski <m.szyprowski@samsung.com>,
	Joonyoung Shim <jy0922.shim@samsung.com>,
	Seung-Woo Kim <sw0312.kim@samsung.com>,
	Kyungmin Park <kyungmin.park@samsung.com>,
	Frieder Schrempf <frieder.schrempf@kontron.de>,
	Fancy Fang <chen.fang@nxp.com>, Tim Harvey <tharvey@gateworks.com>,
	Michael Nazzareno Trimarchi <michael@amarulasolutions.com>,
	Adam Ford <aford173@gmail.com>, Neil Armstrong <narmstrong@baylibre.com>,
	Robert Foss <robert.foss@linaro.org>,
	Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
	Rob Herring <robh+dt@kernel.org>
Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
	linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	NXP Linux Team <linux-imx@nxp.com>,
	linux-amarula <linux-amarula@amarulasolutions.com>,
	Jagan Teki <jagan@amarulasolutions.com>
Subject: [PATCH 11/11] drm: bridge: samsung-dsim: Add i.MX8MM support
Date: Fri,  8 Apr 2022 21:51:08 +0530
Message-Id: <20220408162108.184583-12-jagan@amarulasolutions.com>
X-Mailer: git-send-email 2.25.1
In-Reply-To: <20220408162108.184583-1-jagan@amarulasolutions.com>
References: <20220408162108.184583-1-jagan@amarulasolutions.com>
MIME-Version: 1.0
X-Original-Sender: jagan@amarulasolutions.com
X-Original-Authentication-Results: mx.google.com;       dkim=pass
	header.i=@amarulasolutions.com header.s=google header.b=We3vH+y0;
	spf=pass (google.com: domain of jagan@amarulasolutions.com designates
	209.85.220.41 as permitted sender)
	smtp.mailfrom=jagan@amarulasolutions.com;
	dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com
Content-Type: text/plain; charset="UTF-8"
Precedence: list
Mailing-list: list linux-amarula@amarulasolutions.com;
	contact linux-amarula+owners@amarulasolutions.com
List-ID: <linux-amarula.amarulasolutions.com>
X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com
X-Google-Group-Id: 476853432473
List-Post: 
 <https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/post>,
	<mailto:linux-amarula@amarulasolutions.com>
List-Help: 
 <https://support.google.com/a/amarulasolutions.com/bin/topic.py?topic=25838>,
	<mailto:linux-amarula+help@amarulasolutions.com>
List-Archive: 
 <https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/>
List-Unsubscribe: 
 <mailto:googlegroups-manage+476853432473+unsubscribe@googlegroups.com>,
	<https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/subscribe>

Samsung MIPI DSIM master can also be found in i.MX8MM SoC.

Add compatible and associated driver_data for it.

v1:
* none

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
 drivers/gpu/drm/bridge/samsung-dsim.c | 34 +++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index 71bbaf19f530..d91510a51981 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -360,6 +360,24 @@ static const unsigned int exynos5433_reg_values[] = {
 	[PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c),
 };
 
+static const unsigned int imx8mm_dsim_reg_values[] = {
+	[RESET_TYPE] = DSIM_SWRST,
+	[PLL_TIMER] = 500,
+	[STOP_STATE_CNT] = 0xf,
+	[PHYCTRL_ULPS_EXIT] = 0,
+	[PHYCTRL_VREG_LP] = 0,
+	[PHYCTRL_SLEW_UP] = 0,
+	[PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06),
+	[PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b),
+	[PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07),
+	[PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x26),
+	[PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d),
+	[PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08),
+	[PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x08),
+	[PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d),
+	[PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b),
+};
+
 static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = {
 	.reg_ofs = exynos_reg_ofs,
 	.plltmr_reg = 0x50,
@@ -426,6 +444,18 @@ static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = {
 	.platform_init = true,
 };
 
+static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data = {
+	.reg_ofs = exynos5433_reg_ofs,
+	.plltmr_reg = 0xa0,
+	.has_clklane_stop = 1,
+	.num_clks = 2,
+	.max_freq = 2100,
+	.wait_for_reset = 0,
+	.num_bits_resol = 12,
+	.pll_p_offset = 14,
+	.reg_values = imx8mm_dsim_reg_values,
+};
+
 static const struct of_device_id samsung_dsim_of_match[] = {
 	{
 		.compatible = "samsung,exynos3250-mipi-dsi",
@@ -447,6 +477,10 @@ static const struct of_device_id samsung_dsim_of_match[] = {
 		.compatible = "samsung,exynos5433-mipi-dsi",
 		.data = &exynos5433_dsi_driver_data
 	},
+	{
+		.compatible = "fsl,imx8mm-mipi-dsim",
+		.data = &imx8mm_dsi_driver_data
+	},
 	{ /* sentinel. */ }
 };