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[209.85.220.41]) by mx.google.com with SMTPS id s10-20020a508dca000000b004372b52e011sor4799906edh.28.2022.07.12.23.54.10 for (Google Transport Security); Tue, 12 Jul 2022 23:54:10 -0700 (PDT) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:aa7:dd4b:0:b0:43a:d508:7cb9 with SMTP id o11-20020aa7dd4b000000b0043ad5087cb9mr2799088edw.218.1657695250372; Tue, 12 Jul 2022 23:54:10 -0700 (PDT) Received: from panicking.amarulasolutions.com ([2.198.242.86]) by smtp.gmail.com with ESMTPSA id j5-20020a056402238500b004358f6e0570sm7389026eda.17.2022.07.12.23.54.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jul 2022 23:54:09 -0700 (PDT) From: Michael Trimarchi To: Dario Binacchi , linux-amarula@amarulasolutions.com Subject: [PATCH 1/4] mtd: nand: Drop busw variable and use chip->options field Date: Wed, 13 Jul 2022 08:54:03 +0200 Message-Id: <20220713065406.272114-1-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=d4MfGWv0; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , No functional change. Reduce the function parameters in preparation of support specific nand manufacture Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/nand_base.c | 58 ++++++++++++++++++-------------- 1 file changed, 32 insertions(+), 26 deletions(-) diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 6f81257cf1..cb22e0ec13 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -3890,8 +3890,7 @@ static void nand_onfi_detect_micron(struct nand_chip *chip, /* * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise. */ -static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, - int *busw) +static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip) { struct nand_onfi_params *p = &chip->onfi_params; char id[4]; @@ -3963,9 +3962,7 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, chip->bits_per_cell = p->bits_per_cell; if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS) - *busw = NAND_BUSWIDTH_16; - else - *busw = 0; + chip->options |= NAND_BUSWIDTH_16; if (p->ecc_bits != 0xff) { chip->ecc_strength_ds = p->ecc_bits; @@ -3995,8 +3992,7 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, return 1; } #else -static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, - int *busw) +static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip) { return 0; } @@ -4005,8 +4001,7 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, /* * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise. */ -static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip, - int *busw) +static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip) { struct nand_jedec_params *p = &chip->jedec_params; struct jedec_ecc_info *ecc; @@ -4068,9 +4063,7 @@ static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip, chip->bits_per_cell = p->bits_per_cell; if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS) - *busw = NAND_BUSWIDTH_16; - else - *busw = 0; + chip->options |= NAND_BUSWIDTH_16; /* ECC info */ ecc = &p->ecc_info[0]; @@ -4160,7 +4153,7 @@ static int nand_get_bits_per_cell(u8 cellinfo) * manufacturer-specific "extended ID" decoding patterns. */ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, - u8 id_data[8], int *busw) + u8 id_data[8]) { int extid, id_len; /* The 3rd id byte holds MLC / multichip data */ @@ -4213,7 +4206,6 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, /* Calc blocksize */ mtd->erasesize = (128 * 1024) << (((extid >> 1) & 0x04) | (extid & 0x03)); - *busw = 0; } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX && !nand_is_slc(chip)) { unsigned int tmp; @@ -4254,7 +4246,6 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, mtd->erasesize = 768 * 1024; else mtd->erasesize = (64 * 1024) << tmp; - *busw = 0; } else { /* Calc pagesize */ mtd->writesize = 1024 << (extid & 0x03); @@ -4267,7 +4258,7 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, mtd->erasesize = (64 * 1024) << (extid & 0x03); extid >>= 2; /* Get buswidth information */ - *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; + chip->options |= (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; /* * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per @@ -4293,15 +4284,14 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, * the chip. */ static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, - struct nand_flash_dev *type, u8 id_data[8], - int *busw) + struct nand_flash_dev *type, u8 id_data[8]) { int maf_id = id_data[0]; mtd->erasesize = type->erasesize; mtd->writesize = type->pagesize; mtd->oobsize = mtd->writesize / 32; - *busw = type->options & NAND_BUSWIDTH_16; + chip->options |= (type->options & NAND_BUSWIDTH_16) ? NAND_BUSWIDTH_16 : 0; /* All legacy ID NAND are small-page, SLC */ chip->bits_per_cell = 1; @@ -4363,7 +4353,7 @@ static inline bool is_full_id_nand(struct nand_flash_dev *type) } static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, - struct nand_flash_dev *type, u8 *id_data, int *busw) + struct nand_flash_dev *type, u8 *id_data) { if (!strncmp((char *)type->id, (char *)id_data, type->id_len)) { mtd->writesize = type->pagesize; @@ -4378,7 +4368,7 @@ static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, chip->onfi_timing_mode_default = type->onfi_timing_mode_default; - *busw = type->options & NAND_BUSWIDTH_16; + chip->options |= (type->options & NAND_BUSWIDTH_16) ? NAND_BUSWIDTH_16 : 0; if (!mtd->name) mtd->name = type->name; @@ -4441,9 +4431,24 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, if (!type) type = nand_flash_ids; + /* + * Save the NAND_BUSWIDTH_16 flag before letting auto-detection logic + * override it. + * This is required to make sure initial NAND bus width set by the + * NAND controller driver is coherent with the real NAND bus width + * (extracted by auto-detection code). + */ + busw = chip->options & NAND_BUSWIDTH_16; + + /* + * The flag is only set (never cleared), reset it to its default value + * before starting auto-detection. + */ + chip->options &= ~NAND_BUSWIDTH_16; + for (; type->name != NULL; type++) { if (is_full_id_nand(type)) { - if (find_full_id_nand(mtd, chip, type, id_data, &busw)) + if (find_full_id_nand(mtd, chip, type, id_data)) goto ident_done; } else if (*dev_id == type->dev_id) { break; @@ -4453,11 +4458,11 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, chip->onfi_version = 0; if (!type->name || !type->pagesize) { /* Check if the chip is ONFI compliant */ - if (nand_flash_detect_onfi(mtd, chip, &busw)) + if (nand_flash_detect_onfi(mtd, chip)) goto ident_done; /* Check if the chip is JEDEC compliant */ - if (nand_flash_detect_jedec(mtd, chip, &busw)) + if (nand_flash_detect_jedec(mtd, chip)) goto ident_done; } @@ -4471,10 +4476,11 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, if (!type->pagesize) { /* Decode parameters from extended ID */ - nand_decode_ext_id(mtd, chip, id_data, &busw); + nand_decode_ext_id(mtd, chip, id_data); } else { - nand_decode_id(mtd, chip, type, id_data, &busw); + nand_decode_id(mtd, chip, type, id_data); } + /* Get chip options */ chip->options |= type->options; From patchwork Wed Jul 13 06:54:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Trimarchi X-Patchwork-Id: 2119 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f71.google.com (mail-ed1-f71.google.com [209.85.208.71]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 5CE163F1F7 for ; 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[209.85.220.41]) by mx.google.com with SMTPS id a9-20020a509e89000000b0043a7c2b13c5sor4725177edf.25.2022.07.12.23.54.12 for (Google Transport Security); Tue, 12 Jul 2022 23:54:12 -0700 (PDT) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:aa7:c783:0:b0:435:2a52:3388 with SMTP id n3-20020aa7c783000000b004352a523388mr2759004eds.164.1657695252496; Tue, 12 Jul 2022 23:54:12 -0700 (PDT) Received: from panicking.amarulasolutions.com ([2.198.242.86]) by smtp.gmail.com with ESMTPSA id j5-20020a056402238500b004358f6e0570sm7389026eda.17.2022.07.12.23.54.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jul 2022 23:54:11 -0700 (PDT) From: Michael Trimarchi To: Dario Binacchi , linux-amarula@amarulasolutions.com Subject: [PATCH 2/4] mtd: nand: Store nand ID in struct nand_chip Date: Wed, 13 Jul 2022 08:54:04 +0200 Message-Id: <20220713065406.272114-2-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220713065406.272114-1-michael@amarulasolutions.com> References: <20220713065406.272114-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=CFRuCEIk; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Upstream commit 7f501f0a72036dc29ad9a53811474c393634b401 Store the NAND ID in struct nand_chip to avoid passing id_data and id_len as function parameters. Signed-off-by: Boris Brezillon Acked-by: Richard Weinberger Reviewed-by: Marek Vasut Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/nand_base.c | 54 ++++++++++++++++---------------- include/linux/mtd/rawnand.h | 15 +++++++++ 2 files changed, 42 insertions(+), 27 deletions(-) diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index cb22e0ec13..6d8b892288 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4152,16 +4152,14 @@ static int nand_get_bits_per_cell(u8 cellinfo) * chip. The rest of the parameters must be decoded according to generic or * manufacturer-specific "extended ID" decoding patterns. */ -static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, - u8 id_data[8]) +static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip) { int extid, id_len; /* The 3rd id byte holds MLC / multichip data */ - chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); + chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]); /* The 4th id byte is the important one */ - extid = id_data[3]; - - id_len = nand_id_len(id_data, 8); + extid = chip->id.data[3]; + id_len = chip->id.len; /* * Field definitions are in the following datasheets: @@ -4172,8 +4170,8 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung * ID to decide what to do. */ - if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG && - !nand_is_slc(chip) && id_data[5] != 0x00) { + if (id_len == 6 && chip->id.data[0] == NAND_MFR_SAMSUNG && + !nand_is_slc(chip) && chip->id.data[5] != 0x00) { /* Calc pagesize */ mtd->writesize = 2048 << (extid & 0x03); extid >>= 2; @@ -4206,7 +4204,7 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, /* Calc blocksize */ mtd->erasesize = (128 * 1024) << (((extid >> 1) & 0x04) | (extid & 0x03)); - } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX && + } else if (id_len == 6 && chip->id.data[0] == NAND_MFR_HYNIX && !nand_is_slc(chip)) { unsigned int tmp; @@ -4268,10 +4266,10 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, * 110b -> 24nm * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC */ - if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA && + if (id_len >= 6 && chip->id.data[0] == NAND_MFR_TOSHIBA && nand_is_slc(chip) && - (id_data[5] & 0x7) == 0x6 /* 24nm */ && - !(id_data[4] & 0x80) /* !BENAND */) { + (chip->id.data[5] & 0x7) == 0x6 /* 24nm */ && + !(chip->id.data[4] & 0x80) /* !BENAND */) { mtd->oobsize = 32 * mtd->writesize >> 9; } @@ -4284,9 +4282,9 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, * the chip. */ static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, - struct nand_flash_dev *type, u8 id_data[8]) + struct nand_flash_dev *type) { - int maf_id = id_data[0]; + int maf_id = chip->id.data[0]; mtd->erasesize = type->erasesize; mtd->writesize = type->pagesize; @@ -4302,11 +4300,11 @@ static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, * listed in nand_ids table. * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) */ - if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00 - && id_data[6] == 0x00 && id_data[7] == 0x00 + if (maf_id == NAND_MFR_AMD && chip->id.data[4] != 0x00 && chip->id.data[5] == 0x00 + && chip->id.data[6] == 0x00 && chip->id.data[7] == 0x00 && mtd->writesize == 512) { mtd->erasesize = 128 * 1024; - mtd->erasesize <<= ((id_data[3] & 0x03) << 1); + mtd->erasesize <<= ((chip->id.data[3] & 0x03) << 1); } } @@ -4316,9 +4314,9 @@ static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, * page size, cell-type information). */ static void nand_decode_bbm_options(struct mtd_info *mtd, - struct nand_chip *chip, u8 id_data[8]) + struct nand_chip *chip) { - int maf_id = id_data[0]; + int maf_id = chip->id.data[0]; /* Set the bad block position */ if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16)) @@ -4353,14 +4351,14 @@ static inline bool is_full_id_nand(struct nand_flash_dev *type) } static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, - struct nand_flash_dev *type, u8 *id_data) + struct nand_flash_dev *type) { - if (!strncmp((char *)type->id, (char *)id_data, type->id_len)) { + if (!strncmp((char *)type->id, (char *)chip->id.data, type->id_len)) { mtd->writesize = type->pagesize; mtd->erasesize = type->erasesize; mtd->oobsize = type->oobsize; - chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); + chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]); chip->chipsize = (uint64_t)type->chipsize << 20; chip->options |= type->options; chip->ecc_strength_ds = NAND_ECC_STRENGTH(type); @@ -4388,7 +4386,7 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, { int busw, ret; int maf_idx; - u8 id_data[8]; + u8 *id_data = chip->id.data; /* * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) @@ -4446,9 +4444,11 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, */ chip->options &= ~NAND_BUSWIDTH_16; + chip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data)); + for (; type->name != NULL; type++) { if (is_full_id_nand(type)) { - if (find_full_id_nand(mtd, chip, type, id_data)) + if (find_full_id_nand(mtd, chip, type)) goto ident_done; } else if (*dev_id == type->dev_id) { break; @@ -4476,9 +4476,9 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, if (!type->pagesize) { /* Decode parameters from extended ID */ - nand_decode_ext_id(mtd, chip, id_data); + nand_decode_ext_id(mtd, chip); } else { - nand_decode_id(mtd, chip, type, id_data); + nand_decode_id(mtd, chip, type); } /* Get chip options */ @@ -4516,7 +4516,7 @@ ident_done: return ERR_PTR(-EINVAL); } - nand_decode_bbm_options(mtd, chip, id_data); + nand_decode_bbm_options(mtd, chip); /* Calculate the address shift from the page size */ chip->page_shift = ffs(mtd->writesize) - 1; diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 3417ca2a0d..f2c6a978cb 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -507,6 +507,19 @@ static inline void nand_hw_control_init(struct nand_hw_control *nfc) init_waitqueue_head(&nfc->wq); } +/* The maximum expected count of bytes in the NAND ID sequence */ +#define NAND_MAX_ID_LEN 8 + +/** + * struct nand_id - NAND id structure + * @data: buffer containing the id bytes. + * @len: ID length. + */ +struct nand_id { + u8 data[NAND_MAX_ID_LEN]; + int len; +}; + /** * struct nand_ecc_step_info - ECC step information of ECC engine * @stepsize: data bytes per ECC step @@ -888,6 +901,8 @@ nand_get_sdr_timings(const struct nand_data_interface *conf) struct nand_chip { struct mtd_info mtd; + struct nand_id id; + void __iomem *IO_ADDR_R; void __iomem *IO_ADDR_W;