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[209.85.220.41]) by mx.google.com with SMTPS id sc17-20020a1709078a1100b0072b67a5f3e1sor287227ejc.70.2022.07.14.00.51.35 for (Google Transport Security); Thu, 14 Jul 2022 00:51:36 -0700 (PDT) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:906:9b0a:b0:72b:4fc2:4b07 with SMTP id eo10-20020a1709069b0a00b0072b4fc24b07mr7639277ejc.700.1657785095299; Thu, 14 Jul 2022 00:51:35 -0700 (PDT) Received: from panicking.amarulasolutions.com ([2.198.242.86]) by smtp.gmail.com with ESMTPSA id r23-20020a170906a21700b0072b616ade26sm369252ejy.216.2022.07.14.00.51.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 00:51:34 -0700 (PDT) From: Michael Trimarchi To: linux-amarula@amarulasolutions.com, Dario Binacchi , Tommaso Merciai Subject: [PATCH 01/11] mtd: nand: Get rid of busw parameter Date: Thu, 14 Jul 2022 09:51:21 +0200 Message-Id: <20220714075131.411548-1-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=didIiQ2b; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Upstream commit 29a198a1592d83f2bc1be3b2631b3bcf3d5b380f Auto-detection functions are passed a busw parameter to retrieve the actual NAND bus width and eventually set the correct value in chip->options. Rework the nand_get_flash_type() function to get rid of this extra parameter and let detection code directly set the NAND_BUSWIDTH_16 flag in chip->options if needed. Signed-off-by: Boris Brezillon Acked-by: Richard Weinberger Reviewed-by: Marek Vasut Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/nand_base.c | 59 +++++++++++++++++--------------- 1 file changed, 32 insertions(+), 27 deletions(-) diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 6f81257cf1..9244287b10 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -3890,8 +3890,7 @@ static void nand_onfi_detect_micron(struct nand_chip *chip, /* * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise. */ -static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, - int *busw) +static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip) { struct nand_onfi_params *p = &chip->onfi_params; char id[4]; @@ -3963,9 +3962,7 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, chip->bits_per_cell = p->bits_per_cell; if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS) - *busw = NAND_BUSWIDTH_16; - else - *busw = 0; + chip->options |= NAND_BUSWIDTH_16; if (p->ecc_bits != 0xff) { chip->ecc_strength_ds = p->ecc_bits; @@ -3995,8 +3992,7 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, return 1; } #else -static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, - int *busw) +static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip) { return 0; } @@ -4005,8 +4001,7 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, /* * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise. */ -static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip, - int *busw) +static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip) { struct nand_jedec_params *p = &chip->jedec_params; struct jedec_ecc_info *ecc; @@ -4068,9 +4063,7 @@ static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip, chip->bits_per_cell = p->bits_per_cell; if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS) - *busw = NAND_BUSWIDTH_16; - else - *busw = 0; + chip->options |= NAND_BUSWIDTH_16; /* ECC info */ ecc = &p->ecc_info[0]; @@ -4160,7 +4153,7 @@ static int nand_get_bits_per_cell(u8 cellinfo) * manufacturer-specific "extended ID" decoding patterns. */ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, - u8 id_data[8], int *busw) + u8 id_data[8]) { int extid, id_len; /* The 3rd id byte holds MLC / multichip data */ @@ -4213,7 +4206,6 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, /* Calc blocksize */ mtd->erasesize = (128 * 1024) << (((extid >> 1) & 0x04) | (extid & 0x03)); - *busw = 0; } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX && !nand_is_slc(chip)) { unsigned int tmp; @@ -4254,7 +4246,6 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, mtd->erasesize = 768 * 1024; else mtd->erasesize = (64 * 1024) << tmp; - *busw = 0; } else { /* Calc pagesize */ mtd->writesize = 1024 << (extid & 0x03); @@ -4267,7 +4258,9 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, mtd->erasesize = (64 * 1024) << (extid & 0x03); extid >>= 2; /* Get buswidth information */ - *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; + /* Get buswidth information */ + if (extid & 0x1) + chip->options |= NAND_BUSWIDTH_16; /* * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per @@ -4293,15 +4286,13 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, * the chip. */ static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, - struct nand_flash_dev *type, u8 id_data[8], - int *busw) + struct nand_flash_dev *type, u8 id_data[8]) { int maf_id = id_data[0]; mtd->erasesize = type->erasesize; mtd->writesize = type->pagesize; mtd->oobsize = mtd->writesize / 32; - *busw = type->options & NAND_BUSWIDTH_16; /* All legacy ID NAND are small-page, SLC */ chip->bits_per_cell = 1; @@ -4363,7 +4354,7 @@ static inline bool is_full_id_nand(struct nand_flash_dev *type) } static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, - struct nand_flash_dev *type, u8 *id_data, int *busw) + struct nand_flash_dev *type, u8 *id_data) { if (!strncmp((char *)type->id, (char *)id_data, type->id_len)) { mtd->writesize = type->pagesize; @@ -4378,8 +4369,6 @@ static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, chip->onfi_timing_mode_default = type->onfi_timing_mode_default; - *busw = type->options & NAND_BUSWIDTH_16; - if (!mtd->name) mtd->name = type->name; @@ -4441,9 +4430,24 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, if (!type) type = nand_flash_ids; + /* + * Save the NAND_BUSWIDTH_16 flag before letting auto-detection logic + * override it. + * This is required to make sure initial NAND bus width set by the + * NAND controller driver is coherent with the real NAND bus width + * (extracted by auto-detection code). + */ + busw = chip->options & NAND_BUSWIDTH_16; + + /* + * The flag is only set (never cleared), reset it to its default value + * before starting auto-detection. + */ + chip->options &= ~NAND_BUSWIDTH_16; + for (; type->name != NULL; type++) { if (is_full_id_nand(type)) { - if (find_full_id_nand(mtd, chip, type, id_data, &busw)) + if (find_full_id_nand(mtd, chip, type, id_data)) goto ident_done; } else if (*dev_id == type->dev_id) { break; @@ -4453,11 +4457,11 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, chip->onfi_version = 0; if (!type->name || !type->pagesize) { /* Check if the chip is ONFI compliant */ - if (nand_flash_detect_onfi(mtd, chip, &busw)) + if (nand_flash_detect_onfi(mtd, chip)) goto ident_done; /* Check if the chip is JEDEC compliant */ - if (nand_flash_detect_jedec(mtd, chip, &busw)) + if (nand_flash_detect_jedec(mtd, chip)) goto ident_done; } @@ -4471,10 +4475,11 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, if (!type->pagesize) { /* Decode parameters from extended ID */ - nand_decode_ext_id(mtd, chip, id_data, &busw); + nand_decode_ext_id(mtd, chip, id_data); } else { - nand_decode_id(mtd, chip, type, id_data, &busw); + nand_decode_id(mtd, chip, type, id_data); } + /* Get chip options */ chip->options |= type->options; From patchwork Thu Jul 14 07:51:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Trimarchi X-Patchwork-Id: 2144 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ej1-f69.google.com (mail-ej1-f69.google.com [209.85.218.69]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id C63253F013 for ; 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[209.85.220.41]) by mx.google.com with SMTPS id dk4-20020a170906f0c400b0071d538ee4dfsor297183ejb.46.2022.07.14.00.51.38 for (Google Transport Security); Thu, 14 Jul 2022 00:51:38 -0700 (PDT) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:907:948e:b0:72d:3fd2:5da0 with SMTP id dm14-20020a170907948e00b0072d3fd25da0mr5337596ejc.225.1657785097316; Thu, 14 Jul 2022 00:51:37 -0700 (PDT) Received: from panicking.amarulasolutions.com ([2.198.242.86]) by smtp.gmail.com with ESMTPSA id r23-20020a170906a21700b0072b616ade26sm369252ejy.216.2022.07.14.00.51.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 00:51:36 -0700 (PDT) From: Michael Trimarchi To: linux-amarula@amarulasolutions.com, Dario Binacchi , Tommaso Merciai Subject: [PATCH 02/11] mtd: nand: Store nand ID in struct nand_chip Date: Thu, 14 Jul 2022 09:51:22 +0200 Message-Id: <20220714075131.411548-2-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220714075131.411548-1-michael@amarulasolutions.com> References: <20220714075131.411548-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=htSvhErT; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Upstream commit 7f501f0a72036dc29ad9a53811474c393634b401 Store the NAND ID in struct nand_chip to avoid passing id_data and id_len as function parameters. Signed-off-by: Boris Brezillon Acked-by: Richard Weinberger Reviewed-by: Marek Vasut Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/nand_base.c | 54 ++++++++++++++++---------------- include/linux/mtd/rawnand.h | 15 +++++++++ 2 files changed, 42 insertions(+), 27 deletions(-) diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 9244287b10..6e964275e5 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4152,16 +4152,14 @@ static int nand_get_bits_per_cell(u8 cellinfo) * chip. The rest of the parameters must be decoded according to generic or * manufacturer-specific "extended ID" decoding patterns. */ -static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, - u8 id_data[8]) +static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip) { int extid, id_len; /* The 3rd id byte holds MLC / multichip data */ - chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); + chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]); /* The 4th id byte is the important one */ - extid = id_data[3]; - - id_len = nand_id_len(id_data, 8); + extid = chip->id.data[3]; + id_len = chip->id.len; /* * Field definitions are in the following datasheets: @@ -4172,8 +4170,8 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung * ID to decide what to do. */ - if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG && - !nand_is_slc(chip) && id_data[5] != 0x00) { + if (id_len == 6 && chip->id.data[0] == NAND_MFR_SAMSUNG && + !nand_is_slc(chip) && chip->id.data[5] != 0x00) { /* Calc pagesize */ mtd->writesize = 2048 << (extid & 0x03); extid >>= 2; @@ -4206,7 +4204,7 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, /* Calc blocksize */ mtd->erasesize = (128 * 1024) << (((extid >> 1) & 0x04) | (extid & 0x03)); - } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX && + } else if (id_len == 6 && chip->id.data[0] == NAND_MFR_HYNIX && !nand_is_slc(chip)) { unsigned int tmp; @@ -4270,10 +4268,10 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, * 110b -> 24nm * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC */ - if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA && + if (id_len >= 6 && chip->id.data[0] == NAND_MFR_TOSHIBA && nand_is_slc(chip) && - (id_data[5] & 0x7) == 0x6 /* 24nm */ && - !(id_data[4] & 0x80) /* !BENAND */) { + (chip->id.data[5] & 0x7) == 0x6 /* 24nm */ && + !(chip->id.data[4] & 0x80) /* !BENAND */) { mtd->oobsize = 32 * mtd->writesize >> 9; } @@ -4286,9 +4284,9 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, * the chip. */ static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, - struct nand_flash_dev *type, u8 id_data[8]) + struct nand_flash_dev *type) { - int maf_id = id_data[0]; + int maf_id = chip->id.data[0]; mtd->erasesize = type->erasesize; mtd->writesize = type->pagesize; @@ -4303,11 +4301,11 @@ static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, * listed in nand_ids table. * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) */ - if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00 - && id_data[6] == 0x00 && id_data[7] == 0x00 + if (maf_id == NAND_MFR_AMD && chip->id.data[4] != 0x00 && chip->id.data[5] == 0x00 + && chip->id.data[6] == 0x00 && chip->id.data[7] == 0x00 && mtd->writesize == 512) { mtd->erasesize = 128 * 1024; - mtd->erasesize <<= ((id_data[3] & 0x03) << 1); + mtd->erasesize <<= ((chip->id.data[3] & 0x03) << 1); } } @@ -4317,9 +4315,9 @@ static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, * page size, cell-type information). */ static void nand_decode_bbm_options(struct mtd_info *mtd, - struct nand_chip *chip, u8 id_data[8]) + struct nand_chip *chip) { - int maf_id = id_data[0]; + int maf_id = chip->id.data[0]; /* Set the bad block position */ if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16)) @@ -4354,14 +4352,14 @@ static inline bool is_full_id_nand(struct nand_flash_dev *type) } static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, - struct nand_flash_dev *type, u8 *id_data) + struct nand_flash_dev *type) { - if (!strncmp((char *)type->id, (char *)id_data, type->id_len)) { + if (!strncmp((char *)type->id, (char *)chip->id.data, type->id_len)) { mtd->writesize = type->pagesize; mtd->erasesize = type->erasesize; mtd->oobsize = type->oobsize; - chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); + chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]); chip->chipsize = (uint64_t)type->chipsize << 20; chip->options |= type->options; chip->ecc_strength_ds = NAND_ECC_STRENGTH(type); @@ -4387,7 +4385,7 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, { int busw, ret; int maf_idx; - u8 id_data[8]; + u8 *id_data = chip->id.data; /* * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) @@ -4445,9 +4443,11 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, */ chip->options &= ~NAND_BUSWIDTH_16; + chip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data)); + for (; type->name != NULL; type++) { if (is_full_id_nand(type)) { - if (find_full_id_nand(mtd, chip, type, id_data)) + if (find_full_id_nand(mtd, chip, type)) goto ident_done; } else if (*dev_id == type->dev_id) { break; @@ -4475,9 +4475,9 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, if (!type->pagesize) { /* Decode parameters from extended ID */ - nand_decode_ext_id(mtd, chip, id_data); + nand_decode_ext_id(mtd, chip); } else { - nand_decode_id(mtd, chip, type, id_data); + nand_decode_id(mtd, chip, type); } /* Get chip options */ @@ -4515,7 +4515,7 @@ ident_done: return ERR_PTR(-EINVAL); } - nand_decode_bbm_options(mtd, chip, id_data); + nand_decode_bbm_options(mtd, chip); /* Calculate the address shift from the page size */ chip->page_shift = ffs(mtd->writesize) - 1; diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 3417ca2a0d..f2c6a978cb 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -507,6 +507,19 @@ static inline void nand_hw_control_init(struct nand_hw_control *nfc) init_waitqueue_head(&nfc->wq); } +/* The maximum expected count of bytes in the NAND ID sequence */ +#define NAND_MAX_ID_LEN 8 + +/** + * struct nand_id - NAND id structure + * @data: buffer containing the id bytes. + * @len: ID length. + */ +struct nand_id { + u8 data[NAND_MAX_ID_LEN]; + int len; +}; + /** * struct nand_ecc_step_info - ECC step information of ECC engine * @stepsize: data bytes per ECC step @@ -888,6 +901,8 @@ nand_get_sdr_timings(const struct nand_data_interface *conf) struct nand_chip { struct mtd_info mtd; + struct nand_id id; + void __iomem *IO_ADDR_R; void __iomem *IO_ADDR_W; From patchwork Thu Jul 14 07:51:23 2022 Content-Type: text/plain; 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[209.85.220.41]) by mx.google.com with SMTPS id hq26-20020a1709073f1a00b006f3a0bc0cf1sor313287ejc.128.2022.07.14.00.51.40 for (Google Transport Security); Thu, 14 Jul 2022 00:51:40 -0700 (PDT) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:907:28d4:b0:72b:49c0:d04a with SMTP id en20-20020a17090728d400b0072b49c0d04amr7613123ejc.141.1657785099346; Thu, 14 Jul 2022 00:51:39 -0700 (PDT) Received: from panicking.amarulasolutions.com ([2.198.242.86]) by smtp.gmail.com with ESMTPSA id r23-20020a170906a21700b0072b616ade26sm369252ejy.216.2022.07.14.00.51.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 00:51:38 -0700 (PDT) From: Michael Trimarchi To: linux-amarula@amarulasolutions.com, Dario Binacchi , Tommaso Merciai Subject: [PATCH 03/11] mtd: nand: Add manufacturer specific initialization/detection steps Date: Thu, 14 Jul 2022 09:51:23 +0200 Message-Id: <20220714075131.411548-3-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220714075131.411548-1-michael@amarulasolutions.com> References: <20220714075131.411548-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=pnztSpIq; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Upstream commit abbe26d144ec22bb067fa414d717b9f7ca2e12bd A lot of NANDs are implementing generic features in a non-generic way, or are providing advanced auto-detection logic where the NAND ID bytes meaning changes with the NAND generation. Providing this vendor specific initialization step will allow us to get rid of full-id entries in the nand_ids table or all the vendor specific cases added over the time in the generic NAND ID decoding logic. Signed-off-by: Boris Brezillon Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/nand_base.c | 90 +++++++++++++++++++++++++------- include/linux/mtd/rawnand.h | 30 +++++++++++ 2 files changed, 102 insertions(+), 18 deletions(-) diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 6e964275e5..d9024432b7 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4278,6 +4278,39 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip) } } +/* + * Manufacturer detection. Only used when the NAND is not ONFI or JEDEC + * compliant and does not have a full-id or legacy-id entry in the nand_ids + * table. + */ +static void nand_manufacturer_detect(struct mtd_info *mtd, struct nand_chip *chip) +{ + /* + * Try manufacturer detection if available and use + * nand_decode_ext_id() otherwise. + */ + if (chip->manufacturer.desc && chip->manufacturer.desc->ops && + chip->manufacturer.desc->ops->detect) + chip->manufacturer.desc->ops->detect(chip); + else + nand_decode_ext_id(mtd, chip); +} + +/* + * Manufacturer initialization. This function is called for all NANDs including + * ONFI and JEDEC compliant ones. + * Manufacturer drivers should put all their specific initialization code in + * their ->init() hook. + */ +static int nand_manufacturer_init(struct nand_chip *chip) +{ + if (!chip->manufacturer.desc || !chip->manufacturer.desc->ops || + !chip->manufacturer.desc->ops->init) + return 0; + + return chip->manufacturer.desc->ops->init(chip); +} + /* * Old devices have chip data hardcoded in the device ID table. nand_decode_id * decodes a matching ID table entry and assigns the MTD size parameters for @@ -4375,6 +4408,26 @@ static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, return false; } +/** + * nand_get_manufacturer_desc - Get manufacturer information from the + * manufacturer ID + * @id: manufacturer ID + * + * Returns a nand_manufacturer_desc object if the manufacturer is defined + * in the NAND manufacturers database, NULL otherwise. + */ +static const struct nand_manufacturers *nand_get_manufacturer_desc(u8 id) +{ + int i; + + for (i = 0; nand_manuf_ids[i].id != 0x0; i++) { + if (nand_manuf_ids[i].id == id) + return &nand_manuf_ids[i]; + } + + return NULL; +} + /* * Get the flash and manufacturer id and lookup if the type is supported. */ @@ -4383,8 +4436,8 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, int *maf_id, int *dev_id, struct nand_flash_dev *type) { + const struct nand_manufacturers *manufacturer_desc; int busw, ret; - int maf_idx; u8 *id_data = chip->id.data; /* @@ -4425,6 +4478,12 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, return ERR_PTR(-ENODEV); } + chip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data)); + + /* Try to identify manufacturer */ + manufacturer_desc = nand_get_manufacturer_desc(*maf_id); + chip->manufacturer.desc = manufacturer_desc; + if (!type) type = nand_flash_ids; @@ -4443,8 +4502,6 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, */ chip->options &= ~NAND_BUSWIDTH_16; - chip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data)); - for (; type->name != NULL; type++) { if (is_full_id_nand(type)) { if (find_full_id_nand(mtd, chip, type)) @@ -4474,8 +4531,7 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, chip->chipsize = (uint64_t)type->chipsize << 20; if (!type->pagesize) { - /* Decode parameters from extended ID */ - nand_decode_ext_id(mtd, chip); + nand_manufacturer_detect(mtd, chip); } else { nand_decode_id(mtd, chip, type); } @@ -4491,12 +4547,6 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, chip->options &= ~NAND_SAMSUNG_LP_OPTIONS; ident_done: - /* Try to identify manufacturer */ - for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) { - if (nand_manuf_ids[maf_idx].id == *maf_id) - break; - } - if (chip->options & NAND_BUSWIDTH_AUTO) { WARN_ON(chip->options & NAND_BUSWIDTH_16); chip->options |= busw; @@ -4508,7 +4558,7 @@ ident_done: */ pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", *maf_id, *dev_id); - pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name); + pr_info("%s %s\n", manufacturer_desc->name, mtd->name); pr_warn("bus width %d instead %d bit\n", (chip->options & NAND_BUSWIDTH_16) ? 16 : 8, busw ? 16 : 8); @@ -4541,28 +4591,32 @@ ident_done: if (mtd->writesize > 512 && chip->cmdfunc == nand_command) chip->cmdfunc = nand_command_lp; + ret = nand_manufacturer_init(chip); + if (ret) + return ERR_PTR(ret); + pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", *maf_id, *dev_id); #ifdef CONFIG_SYS_NAND_ONFI_DETECTION if (chip->onfi_version) - pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, + pr_info("%s %s\n", manufacturer_desc->name, chip->onfi_params.model); else if (chip->jedec_version) - pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, + pr_info("%s %s\n", manufacturer_desc->name, chip->jedec_params.model); else - pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, + pr_info("%s %s\n", manufacturer_desc->name, type->name); #else if (chip->jedec_version) - pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, + pr_info("%s %s\n", manufacturer_desc->name, chip->jedec_params.model); else - pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, + pr_info("%s %s\n", manufacturer_desc->name, type->name); - pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, + pr_info("%s %s\n", manufacturer_desc->name, type->name); #endif diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index f2c6a978cb..57fe7fb47b 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -796,6 +796,17 @@ nand_get_sdr_timings(const struct nand_data_interface *conf) return &conf->timings.sdr; } +/** + * struct nand_manufacturer_ops - NAND Manufacturer operations + * @detect: detect the NAND memory organization and capabilities + * @init: initialize all vendor specific fields (like the ->read_retry() + * implementation) if any. + */ +struct nand_manufacturer_ops { + void (*detect)(struct nand_chip *chip); + int (*init)(struct nand_chip *chip); +}; + /** * struct nand_chip - NAND Private Flash Chip Data * @mtd: MTD device registered to the MTD framework @@ -897,6 +908,7 @@ nand_get_sdr_timings(const struct nand_data_interface *conf) * devices. * @priv: [OPTIONAL] pointer to private chip data * @write_page: [REPLACEABLE] High-level page write function + * @manufacturer: [INTERN] Contains manufacturer information */ struct nand_chip { @@ -983,6 +995,11 @@ struct nand_chip { struct nand_bbt_descr *badblock_pattern; void *priv; + + struct { + const struct nand_manufacturers *desc; + void *priv; + } manufacturer; }; static inline void nand_set_flash_node(struct nand_chip *chip, @@ -1016,6 +1033,17 @@ static inline void nand_set_controller_data(struct nand_chip *chip, void *priv) chip->priv = priv; } +static inline void nand_set_manufacturer_data(struct nand_chip *chip, + void *priv) +{ + chip->manufacturer.priv = priv; +} + +static inline void *nand_get_manufacturer_data(struct nand_chip *chip) +{ + return chip->manufacturer.priv; +} + /* * NAND Flash Manufacturer ID Codes */ @@ -1120,10 +1148,12 @@ struct nand_flash_dev { * struct nand_manufacturers - NAND Flash Manufacturer ID Structure * @name: Manufacturer name * @id: manufacturer ID code of device. + * @ops: manufacturer operations */ struct nand_manufacturers { int id; char *name; + const struct nand_manufacturer_ops *ops; }; extern struct nand_flash_dev nand_flash_ids[]; From patchwork Thu Jul 14 07:51:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Trimarchi X-Patchwork-Id: 2146 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ej1-f70.google.com (mail-ej1-f70.google.com [209.85.218.70]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id EF78C3F013 for ; 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[209.85.220.41]) by mx.google.com with SMTPS id h22-20020a1709060f5600b007263150e3a6sor285430ejj.51.2022.07.14.00.51.42 for (Google Transport Security); Thu, 14 Jul 2022 00:51:42 -0700 (PDT) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:906:3f51:b0:712:3945:8c0d with SMTP id f17-20020a1709063f5100b0071239458c0dmr7487955ejj.302.1657785101736; Thu, 14 Jul 2022 00:51:41 -0700 (PDT) Received: from panicking.amarulasolutions.com ([2.198.242.86]) by smtp.gmail.com with ESMTPSA id r23-20020a170906a21700b0072b616ade26sm369252ejy.216.2022.07.14.00.51.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 00:51:41 -0700 (PDT) From: Michael Trimarchi To: linux-amarula@amarulasolutions.com, Dario Binacchi , Tommaso Merciai Subject: [PATCH 04/11] mtd: nand: Get rid of mtd variable in function calls Date: Thu, 14 Jul 2022 09:51:24 +0200 Message-Id: <20220714075131.411548-4-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220714075131.411548-1-michael@amarulasolutions.com> References: <20220714075131.411548-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=mEpoWws5; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , chip points to mtd. Passing chip is enough to have a reference to mtd when is necessary Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/nand_base.c | 20 +++++++++++--------- include/linux/mtd/rawnand.h | 3 +-- 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index d9024432b7..be1a6738c1 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4152,8 +4152,9 @@ static int nand_get_bits_per_cell(u8 cellinfo) * chip. The rest of the parameters must be decoded according to generic or * manufacturer-specific "extended ID" decoding patterns. */ -static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip) +static void nand_decode_ext_id(struct nand_chip *chip) { + struct mtd_info *mtd = &chip->mtd; int extid, id_len; /* The 3rd id byte holds MLC / multichip data */ chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]); @@ -4283,7 +4284,7 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip) * compliant and does not have a full-id or legacy-id entry in the nand_ids * table. */ -static void nand_manufacturer_detect(struct mtd_info *mtd, struct nand_chip *chip) +static void nand_manufacturer_detect(struct nand_chip *chip) { /* * Try manufacturer detection if available and use @@ -4293,7 +4294,7 @@ static void nand_manufacturer_detect(struct mtd_info *mtd, struct nand_chip *chi chip->manufacturer.desc->ops->detect) chip->manufacturer.desc->ops->detect(chip); else - nand_decode_ext_id(mtd, chip); + nand_decode_ext_id(chip); } /* @@ -4316,9 +4317,10 @@ static int nand_manufacturer_init(struct nand_chip *chip) * decodes a matching ID table entry and assigns the MTD size parameters for * the chip. */ -static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, +static void nand_decode_id(struct nand_chip *chip, struct nand_flash_dev *type) { + struct mtd_info *mtd = &chip->mtd; int maf_id = chip->id.data[0]; mtd->erasesize = type->erasesize; @@ -4431,11 +4433,11 @@ static const struct nand_manufacturers *nand_get_manufacturer_desc(u8 id) /* * Get the flash and manufacturer id and lookup if the type is supported. */ -struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, - struct nand_chip *chip, +struct nand_flash_dev *nand_get_flash_type(struct nand_chip *chip, int *maf_id, int *dev_id, struct nand_flash_dev *type) { + struct mtd_info *mtd = &chip->mtd; const struct nand_manufacturers *manufacturer_desc; int busw, ret; u8 *id_data = chip->id.data; @@ -4531,9 +4533,9 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, chip->chipsize = (uint64_t)type->chipsize << 20; if (!type->pagesize) { - nand_manufacturer_detect(mtd, chip); + nand_manufacturer_detect(chip); } else { - nand_decode_id(mtd, chip, type); + nand_decode_id(chip, type); } /* Get chip options */ @@ -4723,7 +4725,7 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips, nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16); /* Read the flash type */ - type = nand_get_flash_type(mtd, chip, &nand_maf_id, + type = nand_get_flash_type(chip, &nand_maf_id, &nand_dev_id, table); if (IS_ERR(type)) { diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 57fe7fb47b..d8141cb4d1 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -29,8 +29,7 @@ struct nand_flash_dev; struct device_node; /* Get the flash and manufacturer id and lookup if the type is supported. */ -struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, - struct nand_chip *chip, +struct nand_flash_dev *nand_get_flash_type(struct nand_chip *chip, int *maf_id, int *dev_id, struct nand_flash_dev *type); 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[209.85.220.41]) by mx.google.com with SMTPS id 10-20020a170906058a00b007033fef81a4sor312486ejn.56.2022.07.14.00.51.44 for (Google Transport Security); Thu, 14 Jul 2022 00:51:44 -0700 (PDT) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:907:2bde:b0:72b:4da0:6f3c with SMTP id gv30-20020a1709072bde00b0072b4da06f3cmr7289712ejc.623.1657785103706; Thu, 14 Jul 2022 00:51:43 -0700 (PDT) Received: from panicking.amarulasolutions.com ([2.198.242.86]) by smtp.gmail.com with ESMTPSA id r23-20020a170906a21700b0072b616ade26sm369252ejy.216.2022.07.14.00.51.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 00:51:43 -0700 (PDT) From: Michael Trimarchi To: linux-amarula@amarulasolutions.com, Dario Binacchi , Tommaso Merciai Subject: [PATCH 05/11] mtd: nand: Export symbol nand_decode_ext_id Date: Thu, 14 Jul 2022 09:51:25 +0200 Message-Id: <20220714075131.411548-5-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220714075131.411548-1-michael@amarulasolutions.com> References: <20220714075131.411548-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=rmdiUWnj; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , In preparation of moving specific nand support that are not jedec or onfi Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/nand_base.c | 3 ++- include/linux/mtd/rawnand.h | 3 +++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index be1a6738c1..fa9ffb56fd 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4152,7 +4152,7 @@ static int nand_get_bits_per_cell(u8 cellinfo) * chip. The rest of the parameters must be decoded according to generic or * manufacturer-specific "extended ID" decoding patterns. */ -static void nand_decode_ext_id(struct nand_chip *chip) +void nand_decode_ext_id(struct nand_chip *chip) { struct mtd_info *mtd = &chip->mtd; int extid, id_len; @@ -4278,6 +4278,7 @@ static void nand_decode_ext_id(struct nand_chip *chip) } } +EXPORT_SYMBOL_GPL(nand_decode_ext_id); /* * Manufacturer detection. Only used when the NAND is not ONFI or JEDEC diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index d8141cb4d1..8fb2a43296 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -1374,4 +1374,7 @@ int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len, int nand_write_data_op(struct nand_chip *chip, const void *buf, unsigned int len, bool force_8bit); +/* Default extended ID decoding function */ +void nand_decode_ext_id(struct nand_chip *chip); + #endif /* __LINUX_MTD_RAWNAND_H */ From patchwork Thu Jul 14 07:51:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Trimarchi X-Patchwork-Id: 2148 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ej1-f69.google.com (mail-ej1-f69.google.com [209.85.218.69]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id BCF263F013 for ; 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[209.85.220.41]) by mx.google.com with SMTPS id ga38-20020a1709070c2600b00722fce50938sor294831ejc.132.2022.07.14.00.51.47 for (Google Transport Security); Thu, 14 Jul 2022 00:51:47 -0700 (PDT) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:906:3f49:b0:722:e1d2:f857 with SMTP id f9-20020a1709063f4900b00722e1d2f857mr7425680ejj.15.1657785106474; Thu, 14 Jul 2022 00:51:46 -0700 (PDT) Received: from panicking.amarulasolutions.com ([2.198.242.86]) by smtp.gmail.com with ESMTPSA id r23-20020a170906a21700b0072b616ade26sm369252ejy.216.2022.07.14.00.51.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 00:51:45 -0700 (PDT) From: Michael Trimarchi To: linux-amarula@amarulasolutions.com, Dario Binacchi , Tommaso Merciai Subject: [PATCH 06/11] mtd: nand: Move Samsung specific init/detection logic in nand_samsung.c Date: Thu, 14 Jul 2022 09:51:26 +0200 Message-Id: <20220714075131.411548-6-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220714075131.411548-1-michael@amarulasolutions.com> References: <20220714075131.411548-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=qtjsbO2A; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Upstream commit c51d0ac59f24200dfdccc897ff7c3c9446c7599a Move Samsung specific initialization and detection logic into nand_samsung.c. This is part of the "separate vendor specific code from core" cleanup process. Signed-off-by: Boris Brezillon Acked-by: Richard Weinberger Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/Makefile | 3 +- drivers/mtd/nand/raw/nand_base.c | 50 +--------------- drivers/mtd/nand/raw/nand_ids.c | 4 +- drivers/mtd/nand/raw/nand_samsung.c | 90 +++++++++++++++++++++++++++++ include/linux/mtd/rawnand.h | 2 + 5 files changed, 99 insertions(+), 50 deletions(-) create mode 100644 drivers/mtd/nand/raw/nand_samsung.c diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 6ec3581d20..c023c3cb68 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -14,7 +14,7 @@ obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o obj-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o -obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o +obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_samsung.o obj-$(CONFIG_SPL_NAND_IDENT) += nand_ids.o nand_timings.o obj-$(CONFIG_SPL_NAND_INIT) += nand.o ifeq ($(CONFIG_SPL_ENV_SUPPORT),y) @@ -31,6 +31,7 @@ obj-y += nand_ids.o obj-y += nand_util.o obj-y += nand_ecc.o obj-y += nand_base.o +obj-y += nand_samsung.o obj-y += nand_timings.o endif # not spl diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index fa9ffb56fd..d4a91b5fcc 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4165,47 +4165,12 @@ void nand_decode_ext_id(struct nand_chip *chip) /* * Field definitions are in the following datasheets: * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32) - * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44) * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22) * * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung * ID to decide what to do. */ - if (id_len == 6 && chip->id.data[0] == NAND_MFR_SAMSUNG && - !nand_is_slc(chip) && chip->id.data[5] != 0x00) { - /* Calc pagesize */ - mtd->writesize = 2048 << (extid & 0x03); - extid >>= 2; - /* Calc oobsize */ - switch (((extid >> 2) & 0x04) | (extid & 0x03)) { - case 1: - mtd->oobsize = 128; - break; - case 2: - mtd->oobsize = 218; - break; - case 3: - mtd->oobsize = 400; - break; - case 4: - mtd->oobsize = 436; - break; - case 5: - mtd->oobsize = 512; - break; - case 6: - mtd->oobsize = 640; - break; - case 7: - default: /* Other cases are "reserved" (unknown) */ - mtd->oobsize = 1024; - break; - } - extid >>= 2; - /* Calc blocksize */ - mtd->erasesize = (128 * 1024) << - (((extid >> 1) & 0x04) | (extid & 0x03)); - } else if (id_len == 6 && chip->id.data[0] == NAND_MFR_HYNIX && + if (id_len == 6 && chip->id.data[0] == NAND_MFR_HYNIX && !nand_is_slc(chip)) { unsigned int tmp; @@ -4367,13 +4332,10 @@ static void nand_decode_bbm_options(struct mtd_info *mtd, * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba, * AMD/Spansion, and Macronix. All others scan only the first page. */ - if (!nand_is_slc(chip) && - (maf_id == NAND_MFR_SAMSUNG || - maf_id == NAND_MFR_HYNIX)) + if (!nand_is_slc(chip) && maf_id == NAND_MFR_HYNIX) chip->bbt_options |= NAND_BBT_SCANLASTPAGE; else if ((nand_is_slc(chip) && - (maf_id == NAND_MFR_SAMSUNG || - maf_id == NAND_MFR_HYNIX || + (maf_id == NAND_MFR_HYNIX || maf_id == NAND_MFR_TOSHIBA || maf_id == NAND_MFR_AMD || maf_id == NAND_MFR_MACRONIX)) || @@ -4542,12 +4504,6 @@ struct nand_flash_dev *nand_get_flash_type(struct nand_chip *chip, /* Get chip options */ chip->options |= type->options; - /* - * Check if chip is not a Samsung device. Do not clear the - * options for chips which do not have an extended id. - */ - if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize) - chip->options &= ~NAND_SAMSUNG_LP_OPTIONS; ident_done: if (chip->options & NAND_BUSWIDTH_AUTO) { diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c index 2a50f0b214..f4126c3a5a 100644 --- a/drivers/mtd/nand/raw/nand_ids.c +++ b/drivers/mtd/nand/raw/nand_ids.c @@ -10,7 +10,7 @@ #include #include -#define LP_OPTIONS NAND_SAMSUNG_LP_OPTIONS +#define LP_OPTIONS 0 #define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16) #define SP_OPTIONS NAND_NEED_READRDY @@ -189,7 +189,7 @@ struct nand_flash_dev nand_flash_ids[] = { /* Manufacturer IDs */ struct nand_manufacturers nand_manuf_ids[] = { {NAND_MFR_TOSHIBA, "Toshiba"}, - {NAND_MFR_SAMSUNG, "Samsung"}, + {NAND_MFR_SAMSUNG, "Samsung", &samsung_nand_manuf_ops}, {NAND_MFR_FUJITSU, "Fujitsu"}, {NAND_MFR_NATIONAL, "National"}, {NAND_MFR_RENESAS, "Renesas"}, diff --git a/drivers/mtd/nand/raw/nand_samsung.c b/drivers/mtd/nand/raw/nand_samsung.c new file mode 100644 index 0000000000..3dfbbec382 --- /dev/null +++ b/drivers/mtd/nand/raw/nand_samsung.c @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2017 Free Electrons + * Copyright (C) 2017 NextThing Co + * + * Author: Boris Brezillon + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +static void samsung_nand_decode_id(struct nand_chip *chip) +{ + struct mtd_info *mtd = nand_to_mtd(chip); + + /* New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44) */ + if (chip->id.len == 6 && !nand_is_slc(chip) && + chip->id.data[5] != 0x00) { + u8 extid = chip->id.data[3]; + + /* Get pagesize */ + mtd->writesize = 2048 << (extid & 0x03); + + extid >>= 2; + + /* Get oobsize */ + switch (((extid >> 2) & 0x4) | (extid & 0x3)) { + case 1: + mtd->oobsize = 128; + break; + case 2: + mtd->oobsize = 218; + break; + case 3: + mtd->oobsize = 400; + break; + case 4: + mtd->oobsize = 436; + break; + case 5: + mtd->oobsize = 512; + break; + case 6: + mtd->oobsize = 640; + break; + case 7: + default: /* Other cases are "reserved" (unknown) */ + WARN(1, "Invalid OOB size value"); + mtd->oobsize = 1024; + break; + } + + /* Get blocksize */ + extid >>= 2; + mtd->erasesize = (128 * 1024) << + (((extid >> 1) & 0x04) | (extid & 0x03)); + } else { + nand_decode_ext_id(chip); + } +} + +static int samsung_nand_init(struct nand_chip *chip) +{ + struct mtd_info *mtd = nand_to_mtd(chip); + + if (mtd->writesize > 512) + chip->options |= NAND_SAMSUNG_LP_OPTIONS; + + if (!nand_is_slc(chip)) + chip->bbt_options |= NAND_BBT_SCANLASTPAGE; + else + chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; + + return 0; +} + +const struct nand_manufacturer_ops samsung_nand_manuf_ops = { + .detect = samsung_nand_decode_id, + .init = samsung_nand_init, +}; diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 8fb2a43296..d0312e924b 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -1158,6 +1158,8 @@ struct nand_manufacturers { extern struct nand_flash_dev nand_flash_ids[]; extern struct nand_manufacturers nand_manuf_ids[]; +extern const struct nand_manufacturer_ops samsung_nand_manuf_ops; + int nand_default_bbt(struct mtd_info *mtd); int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs); 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[209.85.220.41]) by mx.google.com with SMTPS id b15-20020a170906660f00b0072b4c50a9c0sor291249ejp.66.2022.07.14.00.51.50 for (Google Transport Security); Thu, 14 Jul 2022 00:51:50 -0700 (PDT) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:907:7395:b0:72b:86f2:4fd5 with SMTP id er21-20020a170907739500b0072b86f24fd5mr7800303ejc.332.1657785109353; Thu, 14 Jul 2022 00:51:49 -0700 (PDT) Received: from panicking.amarulasolutions.com ([2.198.242.86]) by smtp.gmail.com with ESMTPSA id r23-20020a170906a21700b0072b616ade26sm369252ejy.216.2022.07.14.00.51.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 00:51:48 -0700 (PDT) From: Michael Trimarchi To: linux-amarula@amarulasolutions.com, Dario Binacchi , Tommaso Merciai Subject: [PATCH 07/11] mtd: nand: Move Hynix specific init/detection logic in nand_hynix.c Date: Thu, 14 Jul 2022 09:51:27 +0200 Message-Id: <20220714075131.411548-7-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220714075131.411548-1-michael@amarulasolutions.com> References: <20220714075131.411548-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=TExNNOyZ; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Upstream commit 01389b6bd2f4f7649cdbb4a99a15d9e0c05d6f8c Move Hynix specific initialization and detection logic into nand_hynix.c. This is part of the "separate vendor specific code from core" cleanup process. Signed-off-by: Boris Brezillon Acked-by: Richard Weinberger Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/Makefile | 3 +- drivers/mtd/nand/raw/nand_base.c | 117 ++++++++---------------------- drivers/mtd/nand/raw/nand_hynix.c | 86 ++++++++++++++++++++++ drivers/mtd/nand/raw/nand_ids.c | 2 +- include/linux/mtd/rawnand.h | 1 + 5 files changed, 121 insertions(+), 88 deletions(-) create mode 100644 drivers/mtd/nand/raw/nand_hynix.c diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index c023c3cb68..d6ba111ab2 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -14,7 +14,7 @@ obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o obj-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o -obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_samsung.o +obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_hynix.o nand_samsung.o obj-$(CONFIG_SPL_NAND_IDENT) += nand_ids.o nand_timings.o obj-$(CONFIG_SPL_NAND_INIT) += nand.o ifeq ($(CONFIG_SPL_ENV_SUPPORT),y) @@ -31,6 +31,7 @@ obj-y += nand_ids.o obj-y += nand_util.o obj-y += nand_ecc.o obj-y += nand_base.o +obj-y += nand_hynix.o obj-y += nand_samsung.o obj-y += nand_timings.o diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index d4a91b5fcc..da22cf6e79 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4162,85 +4162,34 @@ void nand_decode_ext_id(struct nand_chip *chip) extid = chip->id.data[3]; id_len = chip->id.len; + /* Calc pagesize */ + mtd->writesize = 1024 << (extid & 0x03); + extid >>= 2; + /* Calc oobsize */ + mtd->oobsize = (8 << (extid & 0x01)) * + (mtd->writesize >> 9); + extid >>= 2; + /* Calc blocksize. Blocksize is multiples of 64KiB */ + mtd->erasesize = (64 * 1024) << (extid & 0x03); + extid >>= 2; + /* Get buswidth information */ + /* Get buswidth information */ + if (extid & 0x1) + chip->options |= NAND_BUSWIDTH_16; + /* - * Field definitions are in the following datasheets: - * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32) - * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22) - * - * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung - * ID to decide what to do. + * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per + * 512B page. For Toshiba SLC, we decode the 5th/6th byte as + * follows: + * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm, + * 110b -> 24nm + * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC */ - if (id_len == 6 && chip->id.data[0] == NAND_MFR_HYNIX && - !nand_is_slc(chip)) { - unsigned int tmp; - - /* Calc pagesize */ - mtd->writesize = 2048 << (extid & 0x03); - extid >>= 2; - /* Calc oobsize */ - switch (((extid >> 2) & 0x04) | (extid & 0x03)) { - case 0: - mtd->oobsize = 128; - break; - case 1: - mtd->oobsize = 224; - break; - case 2: - mtd->oobsize = 448; - break; - case 3: - mtd->oobsize = 64; - break; - case 4: - mtd->oobsize = 32; - break; - case 5: - mtd->oobsize = 16; - break; - default: - mtd->oobsize = 640; - break; - } - extid >>= 2; - /* Calc blocksize */ - tmp = ((extid >> 1) & 0x04) | (extid & 0x03); - if (tmp < 0x03) - mtd->erasesize = (128 * 1024) << tmp; - else if (tmp == 0x03) - mtd->erasesize = 768 * 1024; - else - mtd->erasesize = (64 * 1024) << tmp; - } else { - /* Calc pagesize */ - mtd->writesize = 1024 << (extid & 0x03); - extid >>= 2; - /* Calc oobsize */ - mtd->oobsize = (8 << (extid & 0x01)) * - (mtd->writesize >> 9); - extid >>= 2; - /* Calc blocksize. Blocksize is multiples of 64KiB */ - mtd->erasesize = (64 * 1024) << (extid & 0x03); - extid >>= 2; - /* Get buswidth information */ - /* Get buswidth information */ - if (extid & 0x1) - chip->options |= NAND_BUSWIDTH_16; - - /* - * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per - * 512B page. For Toshiba SLC, we decode the 5th/6th byte as - * follows: - * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm, - * 110b -> 24nm - * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC - */ - if (id_len >= 6 && chip->id.data[0] == NAND_MFR_TOSHIBA && - nand_is_slc(chip) && - (chip->id.data[5] & 0x7) == 0x6 /* 24nm */ && - !(chip->id.data[4] & 0x80) /* !BENAND */) { - mtd->oobsize = 32 * mtd->writesize >> 9; - } - + if (id_len >= 6 && chip->id.data[0] == NAND_MFR_TOSHIBA && + nand_is_slc(chip) && + (chip->id.data[5] & 0x7) == 0x6 /* 24nm */ && + !(chip->id.data[4] & 0x80) /* !BENAND */) { + mtd->oobsize = 32 * mtd->writesize >> 9; } } EXPORT_SYMBOL_GPL(nand_decode_ext_id); @@ -4332,15 +4281,11 @@ static void nand_decode_bbm_options(struct mtd_info *mtd, * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba, * AMD/Spansion, and Macronix. All others scan only the first page. */ - if (!nand_is_slc(chip) && maf_id == NAND_MFR_HYNIX) - chip->bbt_options |= NAND_BBT_SCANLASTPAGE; - else if ((nand_is_slc(chip) && - (maf_id == NAND_MFR_HYNIX || - maf_id == NAND_MFR_TOSHIBA || - maf_id == NAND_MFR_AMD || - maf_id == NAND_MFR_MACRONIX)) || - (mtd->writesize == 2048 && - maf_id == NAND_MFR_MICRON)) + if ((nand_is_slc(chip) && + (maf_id == NAND_MFR_TOSHIBA || + maf_id == NAND_MFR_AMD || + maf_id == NAND_MFR_MACRONIX)) || + (mtd->writesize == 2048 && maf_id == NAND_MFR_MICRON)) chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; } diff --git a/drivers/mtd/nand/raw/nand_hynix.c b/drivers/mtd/nand/raw/nand_hynix.c new file mode 100644 index 0000000000..a5b6a61507 --- /dev/null +++ b/drivers/mtd/nand/raw/nand_hynix.c @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2017 Free Electrons + * Copyright (C) 2017 NextThing Co + * + * Author: Boris Brezillon + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +static void hynix_nand_decode_id(struct nand_chip *chip) +{ + struct mtd_info *mtd = nand_to_mtd(chip); + + /* Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22) */ + if (chip->id.len == 6 && !nand_is_slc(chip)) { + u8 tmp, extid = chip->id.data[3]; + + /* Extract pagesize */ + mtd->writesize = 2048 << (extid & 0x03); + extid >>= 2; + + /* Extract oobsize */ + switch (((extid >> 2) & 0x4) | (extid & 0x3)) { + case 0: + mtd->oobsize = 128; + break; + case 1: + mtd->oobsize = 224; + break; + case 2: + mtd->oobsize = 448; + break; + case 3: + mtd->oobsize = 64; + break; + case 4: + mtd->oobsize = 32; + break; + case 5: + mtd->oobsize = 16; + break; + default: + mtd->oobsize = 640; + break; + } + + /* Extract blocksize */ + extid >>= 2; + tmp = ((extid >> 1) & 0x04) | (extid & 0x03); + if (tmp < 0x03) + mtd->erasesize = (128 * 1024) << tmp; + else if (tmp == 0x03) + mtd->erasesize = 768 * 1024; + else + mtd->erasesize = (64 * 1024) << tmp; + } else { + nand_decode_ext_id(chip); + } +} + +static int hynix_nand_init(struct nand_chip *chip) +{ + if (!nand_is_slc(chip)) + chip->bbt_options |= NAND_BBT_SCANLASTPAGE; + else + chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; + + return 0; +} + +const struct nand_manufacturer_ops hynix_nand_manuf_ops = { + .detect = hynix_nand_decode_id, + .init = hynix_nand_init, +}; diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c index f4126c3a5a..ec263a4327 100644 --- a/drivers/mtd/nand/raw/nand_ids.c +++ b/drivers/mtd/nand/raw/nand_ids.c @@ -194,7 +194,7 @@ struct nand_manufacturers nand_manuf_ids[] = { {NAND_MFR_NATIONAL, "National"}, {NAND_MFR_RENESAS, "Renesas"}, {NAND_MFR_STMICRO, "ST Micro"}, - {NAND_MFR_HYNIX, "Hynix"}, + {NAND_MFR_HYNIX, "Hynix", &hynix_nand_manuf_ops}, {NAND_MFR_MICRON, "Micron"}, {NAND_MFR_AMD, "AMD/Spansion"}, {NAND_MFR_MACRONIX, "Macronix"}, diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index d0312e924b..d35277d187 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -1159,6 +1159,7 @@ extern struct nand_flash_dev nand_flash_ids[]; extern struct nand_manufacturers nand_manuf_ids[]; extern const struct nand_manufacturer_ops samsung_nand_manuf_ops; +extern const struct nand_manufacturer_ops hynix_nand_manuf_ops; int nand_default_bbt(struct mtd_info *mtd); int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); From patchwork Thu Jul 14 07:51:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Trimarchi X-Patchwork-Id: 2150 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f72.google.com (mail-ed1-f72.google.com [209.85.208.72]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 79BC33F013 for ; Thu, 14 Jul 2022 09:51:53 +0200 (CEST) Received: by mail-ed1-f72.google.com with SMTP id m13-20020a056402430d00b0043ac2f27d83sf984501edc.20 for ; Thu, 14 Jul 2022 00:51:53 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1657785113; cv=pass; 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[209.85.220.41]) by mx.google.com with SMTPS id a12-20020a50858c000000b00437bf0baa39sor445872edh.27.2022.07.14.00.51.52 for (Google Transport Security); Thu, 14 Jul 2022 00:51:52 -0700 (PDT) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a05:6402:35cf:b0:43a:d139:ea2b with SMTP id z15-20020a05640235cf00b0043ad139ea2bmr10455468edc.415.1657785111326; Thu, 14 Jul 2022 00:51:51 -0700 (PDT) Received: from panicking.amarulasolutions.com ([2.198.242.86]) by smtp.gmail.com with ESMTPSA id r23-20020a170906a21700b0072b616ade26sm369252ejy.216.2022.07.14.00.51.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 00:51:50 -0700 (PDT) From: Michael Trimarchi To: linux-amarula@amarulasolutions.com, Dario Binacchi , Tommaso Merciai Subject: [PATCH 08/11] mtd: nand: Move Toshiba specific init/detection logic in nand_toshiba.c Date: Thu, 14 Jul 2022 09:51:28 +0200 Message-Id: <20220714075131.411548-8-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220714075131.411548-1-michael@amarulasolutions.com> References: <20220714075131.411548-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=L+lk2DHl; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Upstream commit 9b2d61f80b060ce3ea5af2a99e148b0b214932b2 Move Toshiba specific initialization and detection logic into nand_toshiba.c. This is part of the "separate vendor specific code from core" cleanup process. Signed-off-by: Boris Brezillon Acked-by: Richard Weinberger Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/Makefile | 3 +- drivers/mtd/nand/raw/nand_base.c | 21 ++---------- drivers/mtd/nand/raw/nand_ids.c | 2 +- drivers/mtd/nand/raw/nand_toshiba.c | 53 +++++++++++++++++++++++++++++ include/linux/mtd/rawnand.h | 1 + 5 files changed, 59 insertions(+), 21 deletions(-) create mode 100644 drivers/mtd/nand/raw/nand_toshiba.c diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index d6ba111ab2..2eb08c1a9f 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -14,7 +14,7 @@ obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o obj-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o -obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_hynix.o nand_samsung.o +obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_hynix.o nand_samsung.o nand_toshiba.o obj-$(CONFIG_SPL_NAND_IDENT) += nand_ids.o nand_timings.o obj-$(CONFIG_SPL_NAND_INIT) += nand.o ifeq ($(CONFIG_SPL_ENV_SUPPORT),y) @@ -33,6 +33,7 @@ obj-y += nand_ecc.o obj-y += nand_base.o obj-y += nand_hynix.o obj-y += nand_samsung.o +obj-y += nand_toshiba.o obj-y += nand_timings.o endif # not spl diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index da22cf6e79..c5a5c22b12 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4155,12 +4155,11 @@ static int nand_get_bits_per_cell(u8 cellinfo) void nand_decode_ext_id(struct nand_chip *chip) { struct mtd_info *mtd = &chip->mtd; - int extid, id_len; + int extid; /* The 3rd id byte holds MLC / multichip data */ chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]); /* The 4th id byte is the important one */ extid = chip->id.data[3]; - id_len = chip->id.len; /* Calc pagesize */ mtd->writesize = 1024 << (extid & 0x03); @@ -4176,21 +4175,6 @@ void nand_decode_ext_id(struct nand_chip *chip) /* Get buswidth information */ if (extid & 0x1) chip->options |= NAND_BUSWIDTH_16; - - /* - * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per - * 512B page. For Toshiba SLC, we decode the 5th/6th byte as - * follows: - * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm, - * 110b -> 24nm - * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC - */ - if (id_len >= 6 && chip->id.data[0] == NAND_MFR_TOSHIBA && - nand_is_slc(chip) && - (chip->id.data[5] & 0x7) == 0x6 /* 24nm */ && - !(chip->id.data[4] & 0x80) /* !BENAND */) { - mtd->oobsize = 32 * mtd->writesize >> 9; - } } EXPORT_SYMBOL_GPL(nand_decode_ext_id); @@ -4282,8 +4266,7 @@ static void nand_decode_bbm_options(struct mtd_info *mtd, * AMD/Spansion, and Macronix. All others scan only the first page. */ if ((nand_is_slc(chip) && - (maf_id == NAND_MFR_TOSHIBA || - maf_id == NAND_MFR_AMD || + (maf_id == NAND_MFR_AMD || maf_id == NAND_MFR_MACRONIX)) || (mtd->writesize == 2048 && maf_id == NAND_MFR_MICRON)) chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c index ec263a4327..509652c8e2 100644 --- a/drivers/mtd/nand/raw/nand_ids.c +++ b/drivers/mtd/nand/raw/nand_ids.c @@ -188,7 +188,7 @@ struct nand_flash_dev nand_flash_ids[] = { /* Manufacturer IDs */ struct nand_manufacturers nand_manuf_ids[] = { - {NAND_MFR_TOSHIBA, "Toshiba"}, + {NAND_MFR_TOSHIBA, "Toshiba", &toshiba_nand_manuf_ops}, {NAND_MFR_SAMSUNG, "Samsung", &samsung_nand_manuf_ops}, {NAND_MFR_FUJITSU, "Fujitsu"}, {NAND_MFR_NATIONAL, "National"}, diff --git a/drivers/mtd/nand/raw/nand_toshiba.c b/drivers/mtd/nand/raw/nand_toshiba.c new file mode 100644 index 0000000000..1ac80df651 --- /dev/null +++ b/drivers/mtd/nand/raw/nand_toshiba.c @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2017 Free Electrons + * Copyright (C) 2017 NextThing Co + * + * Author: Boris Brezillon + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +static void toshiba_nand_decode_id(struct nand_chip *chip) +{ + struct mtd_info *mtd = nand_to_mtd(chip); + + nand_decode_ext_id(chip); + + /* + * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per + * 512B page. For Toshiba SLC, we decode the 5th/6th byte as + * follows: + * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm, + * 110b -> 24nm + * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC + */ + if (chip->id.len >= 6 && nand_is_slc(chip) && + (chip->id.data[5] & 0x7) == 0x6 /* 24nm */ && + !(chip->id.data[4] & 0x80) /* !BENAND */) + mtd->oobsize = 32 * mtd->writesize >> 9; +} + +static int toshiba_nand_init(struct nand_chip *chip) +{ + if (nand_is_slc(chip)) + chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; + + return 0; +} + +const struct nand_manufacturer_ops toshiba_nand_manuf_ops = { + .detect = toshiba_nand_decode_id, + .init = toshiba_nand_init, +}; diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index d35277d187..73abb34016 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -1158,6 +1158,7 @@ struct nand_manufacturers { extern struct nand_flash_dev nand_flash_ids[]; extern struct nand_manufacturers nand_manuf_ids[]; +extern const struct nand_manufacturer_ops toshiba_nand_manuf_ops; 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[209.85.220.41]) by mx.google.com with SMTPS id y89-20020a50bb62000000b0043b0e7d0ba4sor440357ede.5.2022.07.14.00.51.54 for (Google Transport Security); Thu, 14 Jul 2022 00:51:54 -0700 (PDT) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a50:fd08:0:b0:43a:7890:9c54 with SMTP id i8-20020a50fd08000000b0043a78909c54mr10503073eds.52.1657785113943; Thu, 14 Jul 2022 00:51:53 -0700 (PDT) Received: from panicking.amarulasolutions.com ([2.198.242.86]) by smtp.gmail.com with ESMTPSA id r23-20020a170906a21700b0072b616ade26sm369252ejy.216.2022.07.14.00.51.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 00:51:53 -0700 (PDT) From: Michael Trimarchi To: linux-amarula@amarulasolutions.com, Dario Binacchi , Tommaso Merciai Subject: [PATCH 09/11] mtd: nand: Move Micron specific init logic in nand_micron.c Date: Thu, 14 Jul 2022 09:51:29 +0200 Message-Id: <20220714075131.411548-9-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220714075131.411548-1-michael@amarulasolutions.com> References: <20220714075131.411548-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=XVqM+ySH; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Upstream commit 10d4e75c36f6c16311dde1461f318210da357219 Move Micron specific initialization logic into nand_micron.c. This is part of the "separate vendor specific code from core" cleanup process. Signed-off-by: Boris Brezillon Acked-by: Richard Weinberger Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/Makefile | 3 +- drivers/mtd/nand/raw/nand_base.c | 33 +---------- drivers/mtd/nand/raw/nand_ids.c | 2 +- drivers/mtd/nand/raw/nand_micron.c | 88 ++++++++++++++++++++++++++++++ include/linux/mtd/rawnand.h | 21 +------ 5 files changed, 94 insertions(+), 53 deletions(-) create mode 100644 drivers/mtd/nand/raw/nand_micron.c diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 2eb08c1a9f..bb20a04616 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -14,7 +14,7 @@ obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o obj-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o -obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_hynix.o nand_samsung.o nand_toshiba.o +obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_hynix.o nand_micron.o nand_samsung.o nand_toshiba.o obj-$(CONFIG_SPL_NAND_IDENT) += nand_ids.o nand_timings.o obj-$(CONFIG_SPL_NAND_INIT) += nand.o ifeq ($(CONFIG_SPL_ENV_SUPPORT),y) @@ -32,6 +32,7 @@ obj-y += nand_util.o obj-y += nand_ecc.o obj-y += nand_base.o obj-y += nand_hynix.o +obj-y += nand_micron.o obj-y += nand_samsung.o obj-y += nand_toshiba.o obj-y += nand_timings.o diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index c5a5c22b12..9024948ded 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -3863,30 +3863,6 @@ ext_out: return ret; } -static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode}; - - return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY, - feature); -} - -/* - * Configure chip properties from Micron vendor-specific ONFI table - */ -static void nand_onfi_detect_micron(struct nand_chip *chip, - struct nand_onfi_params *p) -{ - struct nand_onfi_vendor_micron *micron = (void *)p->vendor; - - if (le16_to_cpu(p->vendor_revision) < 1) - return; - - chip->read_retries = micron->read_retry_options; - chip->setup_read_retry = nand_setup_read_retry_micron; -} - /* * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise. */ @@ -3986,9 +3962,6 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip) pr_warn("Could not retrieve ONFI ECC requirements\n"); } - if (p->jedec_id == NAND_MFR_MICRON) - nand_onfi_detect_micron(chip, p); - return 1; } #else @@ -4265,10 +4238,8 @@ static void nand_decode_bbm_options(struct mtd_info *mtd, * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba, * AMD/Spansion, and Macronix. All others scan only the first page. */ - if ((nand_is_slc(chip) && - (maf_id == NAND_MFR_AMD || - maf_id == NAND_MFR_MACRONIX)) || - (mtd->writesize == 2048 && maf_id == NAND_MFR_MICRON)) + if (nand_is_slc(chip) && + (maf_id == NAND_MFR_AMD || maf_id == NAND_MFR_MACRONIX)) chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; } diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c index 509652c8e2..bb5ac8337f 100644 --- a/drivers/mtd/nand/raw/nand_ids.c +++ b/drivers/mtd/nand/raw/nand_ids.c @@ -195,7 +195,7 @@ struct nand_manufacturers nand_manuf_ids[] = { {NAND_MFR_RENESAS, "Renesas"}, {NAND_MFR_STMICRO, "ST Micro"}, {NAND_MFR_HYNIX, "Hynix", &hynix_nand_manuf_ops}, - {NAND_MFR_MICRON, "Micron"}, + {NAND_MFR_MICRON, "Micron", µn_nand_manuf_ops}, {NAND_MFR_AMD, "AMD/Spansion"}, {NAND_MFR_MACRONIX, "Macronix"}, {NAND_MFR_EON, "Eon"}, diff --git a/drivers/mtd/nand/raw/nand_micron.c b/drivers/mtd/nand/raw/nand_micron.c new file mode 100644 index 0000000000..a99bf8bbec --- /dev/null +++ b/drivers/mtd/nand/raw/nand_micron.c @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2017 Free Electrons + * Copyright (C) 2017 NextThing Co + * + * Author: Boris Brezillon + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +struct nand_onfi_vendor_micron { + u8 two_plane_read; + u8 read_cache; + u8 read_unique_id; + u8 dq_imped; + u8 dq_imped_num_settings; + u8 dq_imped_feat_addr; + u8 rb_pulldown_strength; + u8 rb_pulldown_strength_feat_addr; + u8 rb_pulldown_strength_num_settings; + u8 otp_mode; + u8 otp_page_start; + u8 otp_data_prot_addr; + u8 otp_num_pages; + u8 otp_feat_addr; + u8 read_retry_options; + u8 reserved[72]; + u8 param_revision; +} __packed; + +static int micron_nand_setup_read_retry(struct mtd_info *mtd, int retry_mode) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + u8 feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode}; + + return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY, + feature); +} + +/* + * Configure chip properties from Micron vendor-specific ONFI table + */ +static int micron_nand_onfi_init(struct nand_chip *chip) +{ + struct nand_onfi_params *p = &chip->onfi_params; + struct nand_onfi_vendor_micron *micron = (void *)p->vendor; + + if (!chip->onfi_version) + return 0; + + if (le16_to_cpu(p->vendor_revision) < 1) + return 0; + + chip->read_retries = micron->read_retry_options; + chip->setup_read_retry = micron_nand_setup_read_retry; + + return 0; +} + +static int micron_nand_init(struct nand_chip *chip) +{ + struct mtd_info *mtd = nand_to_mtd(chip); + int ret; + + ret = micron_nand_onfi_init(chip); + if (ret) + return ret; + + if (mtd->writesize == 2048) + chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; + + return 0; +} + +const struct nand_manufacturer_ops micron_nand_manuf_ops = { + .init = micron_nand_init, +}; diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 73abb34016..ec0f77b24b 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -388,26 +388,6 @@ struct onfi_ext_param_page { */ } __packed; -struct nand_onfi_vendor_micron { - u8 two_plane_read; - u8 read_cache; - u8 read_unique_id; - u8 dq_imped; - u8 dq_imped_num_settings; - u8 dq_imped_feat_addr; - u8 rb_pulldown_strength; - u8 rb_pulldown_strength_feat_addr; - u8 rb_pulldown_strength_num_settings; - u8 otp_mode; - u8 otp_page_start; - u8 otp_data_prot_addr; - u8 otp_num_pages; - u8 otp_feat_addr; - u8 read_retry_options; - u8 reserved[72]; - u8 param_revision; -} __packed; - struct jedec_ecc_info { u8 ecc_bits; u8 codeword_size; @@ -1161,6 +1141,7 @@ extern struct nand_manufacturers nand_manuf_ids[]; extern const struct nand_manufacturer_ops toshiba_nand_manuf_ops; extern const struct nand_manufacturer_ops samsung_nand_manuf_ops; extern const struct nand_manufacturer_ops hynix_nand_manuf_ops; +extern const struct nand_manufacturer_ops micron_nand_manuf_ops; int nand_default_bbt(struct mtd_info *mtd); int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); From patchwork Thu Jul 14 07:51:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Trimarchi X-Patchwork-Id: 2152 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f69.google.com (mail-ed1-f69.google.com [209.85.208.69]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 6F19A3F013 for ; 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[209.85.220.41]) by mx.google.com with SMTPS id yk19-20020a17090770d300b0072b8fc09908sor272473ejb.133.2022.07.14.00.51.56 for (Google Transport Security); Thu, 14 Jul 2022 00:51:56 -0700 (PDT) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:907:2808:b0:72b:4d49:b2e9 with SMTP id eb8-20020a170907280800b0072b4d49b2e9mr7889053ejc.176.1657785116031; Thu, 14 Jul 2022 00:51:56 -0700 (PDT) Received: from panicking.amarulasolutions.com ([2.198.242.86]) by smtp.gmail.com with ESMTPSA id r23-20020a170906a21700b0072b616ade26sm369252ejy.216.2022.07.14.00.51.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 00:51:55 -0700 (PDT) From: Michael Trimarchi To: linux-amarula@amarulasolutions.com, Dario Binacchi , Tommaso Merciai Subject: [PATCH 10/11] mtd: nand: Move AMD/Spansion specific init/detection logic in nand_amd.c Date: Thu, 14 Jul 2022 09:51:30 +0200 Message-Id: <20220714075131.411548-10-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220714075131.411548-1-michael@amarulasolutions.com> References: <20220714075131.411548-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=o7KrrUvm; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Upstream commit 229204da53b31d576fcc1c93a33626943ea8202c Move AMD/Spansion specific initialization/detection logic into nand_amd.c. This is part of the "separate vendor specific code from core" cleanup process. Signed-off-by: Boris Brezillon Acked-by: Richard Weinberger Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/Makefile | 4 ++- drivers/mtd/nand/raw/nand_amd.c | 53 ++++++++++++++++++++++++++++++++ drivers/mtd/nand/raw/nand_base.c | 17 +--------- drivers/mtd/nand/raw/nand_ids.c | 2 +- include/linux/mtd/rawnand.h | 1 + 5 files changed, 59 insertions(+), 18 deletions(-) create mode 100644 drivers/mtd/nand/raw/nand_amd.c diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index bb20a04616..090bb413f7 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -14,7 +14,8 @@ obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o obj-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o -obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_hynix.o nand_micron.o nand_samsung.o nand_toshiba.o +obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_amd.o nand_hynix.o nand_micron.o \ + nand_samsung.o nand_toshiba.o obj-$(CONFIG_SPL_NAND_IDENT) += nand_ids.o nand_timings.o obj-$(CONFIG_SPL_NAND_INIT) += nand.o ifeq ($(CONFIG_SPL_ENV_SUPPORT),y) @@ -31,6 +32,7 @@ obj-y += nand_ids.o obj-y += nand_util.o obj-y += nand_ecc.o obj-y += nand_base.o +obj-y += nand_amd.o obj-y += nand_hynix.o obj-y += nand_micron.o obj-y += nand_samsung.o diff --git a/drivers/mtd/nand/raw/nand_amd.c b/drivers/mtd/nand/raw/nand_amd.c new file mode 100644 index 0000000000..f11166f361 --- /dev/null +++ b/drivers/mtd/nand/raw/nand_amd.c @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2017 Free Electrons + * Copyright (C) 2017 NextThing Co + * + * Author: Boris Brezillon + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +static void amd_nand_decode_id(struct nand_chip *chip) +{ + struct mtd_info *mtd = nand_to_mtd(chip); + + nand_decode_ext_id(chip); + + /* + * Check for Spansion/AMD ID + repeating 5th, 6th byte since + * some Spansion chips have erasesize that conflicts with size + * listed in nand_ids table. + * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) + */ + if (chip->id.data[4] != 0x00 && chip->id.data[5] == 0x00 && + chip->id.data[6] == 0x00 && chip->id.data[7] == 0x00 && + mtd->writesize == 512) { + mtd->erasesize = 128 * 1024; + mtd->erasesize <<= ((chip->id.data[3] & 0x03) << 1); + } +} + +static int amd_nand_init(struct nand_chip *chip) +{ + if (nand_is_slc(chip)) + chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; + + return 0; +} + +const struct nand_manufacturer_ops amd_nand_manuf_ops = { + .detect = amd_nand_decode_id, + .init = amd_nand_init, +}; diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 9024948ded..baa7618923 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4193,7 +4193,6 @@ static void nand_decode_id(struct nand_chip *chip, struct nand_flash_dev *type) { struct mtd_info *mtd = &chip->mtd; - int maf_id = chip->id.data[0]; mtd->erasesize = type->erasesize; mtd->writesize = type->pagesize; @@ -4201,19 +4200,6 @@ static void nand_decode_id(struct nand_chip *chip, /* All legacy ID NAND are small-page, SLC */ chip->bits_per_cell = 1; - - /* - * Check for Spansion/AMD ID + repeating 5th, 6th byte since - * some Spansion chips have erasesize that conflicts with size - * listed in nand_ids table. - * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) - */ - if (maf_id == NAND_MFR_AMD && chip->id.data[4] != 0x00 && chip->id.data[5] == 0x00 - && chip->id.data[6] == 0x00 && chip->id.data[7] == 0x00 - && mtd->writesize == 512) { - mtd->erasesize = 128 * 1024; - mtd->erasesize <<= ((chip->id.data[3] & 0x03) << 1); - } } /* @@ -4238,8 +4224,7 @@ static void nand_decode_bbm_options(struct mtd_info *mtd, * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba, * AMD/Spansion, and Macronix. All others scan only the first page. */ - if (nand_is_slc(chip) && - (maf_id == NAND_MFR_AMD || maf_id == NAND_MFR_MACRONIX)) + if (nand_is_slc(chip) && maf_id == NAND_MFR_MACRONIX) chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; } diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c index bb5ac8337f..c78f2e0880 100644 --- a/drivers/mtd/nand/raw/nand_ids.c +++ b/drivers/mtd/nand/raw/nand_ids.c @@ -196,7 +196,7 @@ struct nand_manufacturers nand_manuf_ids[] = { {NAND_MFR_STMICRO, "ST Micro"}, {NAND_MFR_HYNIX, "Hynix", &hynix_nand_manuf_ops}, {NAND_MFR_MICRON, "Micron", µn_nand_manuf_ops}, - {NAND_MFR_AMD, "AMD/Spansion"}, + {NAND_MFR_AMD, "AMD/Spansion", &amd_nand_manuf_ops}, {NAND_MFR_MACRONIX, "Macronix"}, {NAND_MFR_EON, "Eon"}, {NAND_MFR_SANDISK, "SanDisk"}, diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index ec0f77b24b..bb1a359a9c 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -1142,6 +1142,7 @@ extern const struct nand_manufacturer_ops toshiba_nand_manuf_ops; extern const struct nand_manufacturer_ops samsung_nand_manuf_ops; extern const struct nand_manufacturer_ops hynix_nand_manuf_ops; extern const struct nand_manufacturer_ops micron_nand_manuf_ops; +extern const struct nand_manufacturer_ops amd_nand_manuf_ops; int nand_default_bbt(struct mtd_info *mtd); int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); From patchwork Thu Jul 14 07:51:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Trimarchi X-Patchwork-Id: 2153 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ej1-f72.google.com (mail-ej1-f72.google.com [209.85.218.72]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 576B13F013 for ; Thu, 14 Jul 2022 09:52:00 +0200 (CEST) Received: by mail-ej1-f72.google.com with SMTP id gr1-20020a170906e2c100b006fefea3ec0asf424060ejb.14 for ; Thu, 14 Jul 2022 00:52:00 -0700 (PDT) ARC-Seal: i=2; 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[209.85.220.41]) by mx.google.com with SMTPS id dv3-20020a170906b80300b0072b5f614ddcsor306557ejb.41.2022.07.14.00.51.58 for (Google Transport Security); Thu, 14 Jul 2022 00:51:58 -0700 (PDT) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:906:6989:b0:726:f129:1748 with SMTP id i9-20020a170906698900b00726f1291748mr7318783ejr.495.1657785118147; Thu, 14 Jul 2022 00:51:58 -0700 (PDT) Received: from panicking.amarulasolutions.com ([2.198.242.86]) by smtp.gmail.com with ESMTPSA id r23-20020a170906a21700b0072b616ade26sm369252ejy.216.2022.07.14.00.51.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 00:51:57 -0700 (PDT) From: Michael Trimarchi To: linux-amarula@amarulasolutions.com, Dario Binacchi , Tommaso Merciai Subject: [PATCH 11/11] mtd: nand: Move Macronix specific initialization in nand_macronix.c Date: Thu, 14 Jul 2022 09:51:31 +0200 Message-Id: <20220714075131.411548-11-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220714075131.411548-1-michael@amarulasolutions.com> References: <20220714075131.411548-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=lqvgGs5H; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Upstream commit 3b5206f4be9b65d2f0f85b3239cf117a1d0de7ce Move Macronix specific initialization logic into nand_macronix.c. This is part of the "separate vendor specific code from core" cleanup process. Signed-off-by: Boris Brezillon Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/Makefile | 4 +++- drivers/mtd/nand/raw/nand_base.c | 11 ---------- drivers/mtd/nand/raw/nand_ids.c | 2 +- drivers/mtd/nand/raw/nand_macronix.c | 32 ++++++++++++++++++++++++++++ include/linux/mtd/rawnand.h | 1 + 5 files changed, 37 insertions(+), 13 deletions(-) create mode 100644 drivers/mtd/nand/raw/nand_macronix.c diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 090bb413f7..d888eb2be5 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -14,7 +14,8 @@ obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o obj-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o -obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_amd.o nand_hynix.o nand_micron.o \ +obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_amd.o nand_hynix.o \ + nand_macronix.o nand_micron.o \ nand_samsung.o nand_toshiba.o obj-$(CONFIG_SPL_NAND_IDENT) += nand_ids.o nand_timings.o obj-$(CONFIG_SPL_NAND_INIT) += nand.o @@ -34,6 +35,7 @@ obj-y += nand_ecc.o obj-y += nand_base.o obj-y += nand_amd.o obj-y += nand_hynix.o +obj-y += nand_macronix.o obj-y += nand_micron.o obj-y += nand_samsung.o obj-y += nand_toshiba.o diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index baa7618923..b16300c304 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4210,22 +4210,11 @@ static void nand_decode_id(struct nand_chip *chip, static void nand_decode_bbm_options(struct mtd_info *mtd, struct nand_chip *chip) { - int maf_id = chip->id.data[0]; - /* Set the bad block position */ if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16)) chip->badblockpos = NAND_LARGE_BADBLOCK_POS; else chip->badblockpos = NAND_SMALL_BADBLOCK_POS; - - /* - * Bad block marker is stored in the last page of each block on Samsung - * and Hynix MLC devices; stored in first two pages of each block on - * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba, - * AMD/Spansion, and Macronix. All others scan only the first page. - */ - if (nand_is_slc(chip) && maf_id == NAND_MFR_MACRONIX) - chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; } static inline bool is_full_id_nand(struct nand_flash_dev *type) diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c index c78f2e0880..7602dd30f1 100644 --- a/drivers/mtd/nand/raw/nand_ids.c +++ b/drivers/mtd/nand/raw/nand_ids.c @@ -197,7 +197,7 @@ struct nand_manufacturers nand_manuf_ids[] = { {NAND_MFR_HYNIX, "Hynix", &hynix_nand_manuf_ops}, {NAND_MFR_MICRON, "Micron", µn_nand_manuf_ops}, {NAND_MFR_AMD, "AMD/Spansion", &amd_nand_manuf_ops}, - {NAND_MFR_MACRONIX, "Macronix"}, + {NAND_MFR_MACRONIX, "Macronix", ¯onix_nand_manuf_ops}, {NAND_MFR_EON, "Eon"}, {NAND_MFR_SANDISK, "SanDisk"}, {NAND_MFR_INTEL, "Intel"}, diff --git a/drivers/mtd/nand/raw/nand_macronix.c b/drivers/mtd/nand/raw/nand_macronix.c new file mode 100644 index 0000000000..3cccb5869a --- /dev/null +++ b/drivers/mtd/nand/raw/nand_macronix.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2017 Free Electrons + * Copyright (C) 2017 NextThing Co + * + * Author: Boris Brezillon + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +static int macronix_nand_init(struct nand_chip *chip) +{ + if (nand_is_slc(chip)) + chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; + + return 0; +} + +const struct nand_manufacturer_ops macronix_nand_manuf_ops = { + .init = macronix_nand_init, +}; diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index bb1a359a9c..aa45558b3d 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -1143,6 +1143,7 @@ extern const struct nand_manufacturer_ops samsung_nand_manuf_ops; extern const struct nand_manufacturer_ops hynix_nand_manuf_ops; extern const struct nand_manufacturer_ops micron_nand_manuf_ops; extern const struct nand_manufacturer_ops amd_nand_manuf_ops; +extern const struct nand_manufacturer_ops macronix_nand_manuf_ops; int nand_default_bbt(struct mtd_info *mtd); int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);