From patchwork Thu Jul 14 07:51:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Nazzareno Trimarchi X-Patchwork-Id: 2143 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ej1-f69.google.com (mail-ej1-f69.google.com [209.85.218.69]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id CD45D3F013 for ; Thu, 14 Jul 2022 09:51:37 +0200 (CEST) Received: by mail-ej1-f69.google.com with SMTP id nb10-20020a1709071c8a00b006e8f89863cesf423821ejc.18 for ; Thu, 14 Jul 2022 00:51:37 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1657785097; cv=pass; d=google.com; s=arc-20160816; b=E+oZwpdDEg6g89N5nl3T4E1DTpvAmfmixMLlva3C/Li1a+5LEGeu1PYMOMNEs0pGWf giNuZH7E+TwU9YP3xKYVsA0B5+cgJsW3f043vHkTxBEvhw92DvxDD7FLtqH7Rro/oiEu TmQQWCDhc08Wr54i4AQjk/pUm/6q8GPZq1SzK0+xjNNC5kGwSEcyGMhy+5arSoIccYuW uU7NZQ6RRhJ24TQVEbmrMyzFN/Hn51N/YN19+BgFYKUi8NJ9HYl8g+AtmYW749SmNPTN dPhmZr2tzUqrJ8s6GXS/2v9QrELIV1CnUPJHm6qAWyb4VM1LzHp5nB54Bh1OktxLA2TE SOFw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:message-id:date:subject:to :from:dkim-signature; bh=68Fw0VstvOJ5KRce9Fl2UJr5HAM04X4dIRBClvxSJGU=; b=ucGVyzTNpoGqiNws1AJtawredhWCMOzHAQPrYpjy0eFEIJWr/2s60IXSoE3pF45y5/ JopLaYq3yorcAvIM8Bz+c4/1a8+2zeWvweE7HX+maWND8bN9kDFxvLStzk3YpXCdZhx6 FWDqYZYexryo3oIybduorwNADAbiDVFohNB3mYcyFEoIeHC6xtKYcwJ4k9YG1Sw+1S5H dO8UP7Qpitgx/yHXnyznbDVGURwtvpHqs0G+q8aL4mVY1VqLJvmRpWmqNx0YL/0ZOR2j KIiuAt0jZVAFXHwbel0nTQ/Z5FjuSecJGewQ7crwGr9CXsscV5HfI9Q3zVX9G5GsEz7o mvGA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=didIiQ2b; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:subject:date:message-id:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=68Fw0VstvOJ5KRce9Fl2UJr5HAM04X4dIRBClvxSJGU=; b=cPhpkWaqAycnzRiNQWsnbQSuOw6M/HwJfAfLlLIKdabLh6AUxfcmv8s5M4LJ8TpvZ6 AHuOR5qJ1C+gqv5cr4iiNJ0P2V7WnoOGOXaGzJQnZaGkoXKdP2YmHctMMCKBX0Uvfwcj SuYFGDyMlMiFGefKPCGCRxBow/m2AJNk42bIg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:mime-version :x-original-sender:x-original-authentication-results:precedence :mailing-list:list-id:x-spam-checked-in-group:list-post:list-help :list-archive:list-unsubscribe; bh=68Fw0VstvOJ5KRce9Fl2UJr5HAM04X4dIRBClvxSJGU=; b=X+lQzeivD8KfMJggfrm/TlsIBrBK79Wt82aj65g2BumSp5tbcgtIsy82k6fvjFbbll jC0Yt0w6LRJ0o4Ls1JDXBCfAKTQYznR8oUqVXqDUeGBpQqMGPVqY1GOkleQ6lM5a4in9 a01VD3sYokiAO3twClSMDCaMesqtb+dHGeyQHBe1YDU6NZ/QV34q9+A+m+63E/RTTf1A cHtsNDcsvpJbpmuYYWEFA3do2FE7Dtc/52gesa1X7czagfoQjw5cy2ENHejPAbpneYZM sRdP/TW5k51TjgcAQWNfNZkz06AByjFno3ifJYDeyLn1bFv0uhz48sf/V2mIiJYCG4OQ JlSg== X-Gm-Message-State: AJIora9WODskaaWD445vFBceJw/wmNsmuK/us4Cae+XbL+uEfzSUf0/W p+5MshtAcHOO+kB5gRBBpM4W1daA X-Google-Smtp-Source: AGRyM1ud22Ox85u1QnQ1xJd4sIOiISh6pAQuyPGVp/QuvJYsBV210GZrJ5OWS0/ZrxQhZ+gc4f7sEw== X-Received: by 2002:a17:907:a056:b0:72b:1964:fbcc with SMTP id gz22-20020a170907a05600b0072b1964fbccmr7663655ejc.489.1657785097381; Thu, 14 Jul 2022 00:51:37 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a05:6402:34cc:b0:43a:d872:b6aa with SMTP id w12-20020a05640234cc00b0043ad872b6aals143160edc.0.gmail; Thu, 14 Jul 2022 00:51:36 -0700 (PDT) X-Received: by 2002:a05:6402:5c9:b0:420:aac6:257b with SMTP id n9-20020a05640205c900b00420aac6257bmr10542726edx.128.1657785096014; Thu, 14 Jul 2022 00:51:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657785096; cv=none; d=google.com; s=arc-20160816; b=zj561S0T60DCujs3T3ENfPYcCZhUCTZaklLpsdQdWDOrQMUchAfKlD2zH2d+sdHyE5 89tc1l30Gr91D3YtyYDZhw71qBBYzVrMUU9hfpsUsgyAJkn7wen5eu+YTzU+wpb0vC2V 0mxVQmnWbUvPhObUVg9eSZz1QoOd5ZgFVPqb63UU9Dlvcr/SG5mqAd5qEyXTnDZUVr1S k+0ck374e8raYkDvgd4r+BOLyuJlLfcticHqeeSXoHJwGwaSP+/sxDKiKE3eIHaRFPYe 9HeRJd9CCfDy9al9aXjDpthVBX2G+6FKnGkCNwafjbOzJs0IIHpeZBKXerqT8BcOtvwg w90w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:message-id:date:subject:to :from:dkim-signature; bh=N7/sSWXem3bN7xJUzqI7RvbQX3kYUU7XoPk2vsJB6V0=; b=oGjg//Ms413OGKCmZgdRPOwcqA0AfS3xJe3BDzXPhf/LNEHMHIjik94FN9bIKb5roW JedFPukLMQvBDr9YKhTPvGsSmBdjheSSd4pvcU0STfOQp0DU0VLj/4ZxKt69SQkPlqLM wXJb2X+OrdbbU15AqFSU35Kh8dXWuU11SeS8o43CncbHpog3kiG1zUVFiRhDmR5K/5BI Y1ng6KgF91aG8Rk5bz1L2oO4hR8dXWcinzkXMqJyC9YEnMWQ7CEBEAC4U3VJ5MRUTQhM pmxnJFPYdvMSFIt5Bmq/CKKZqoveqEu7kCSdAMDc8lxawiSNT4DOt4tEDOgIbmTrxICL dyZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=didIiQ2b; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id sc17-20020a1709078a1100b0072b67a5f3e1sor287227ejc.70.2022.07.14.00.51.35 for (Google Transport Security); Thu, 14 Jul 2022 00:51:36 -0700 (PDT) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:906:9b0a:b0:72b:4fc2:4b07 with SMTP id eo10-20020a1709069b0a00b0072b4fc24b07mr7639277ejc.700.1657785095299; Thu, 14 Jul 2022 00:51:35 -0700 (PDT) Received: from panicking.amarulasolutions.com ([2.198.242.86]) by smtp.gmail.com with ESMTPSA id r23-20020a170906a21700b0072b616ade26sm369252ejy.216.2022.07.14.00.51.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 00:51:34 -0700 (PDT) From: Michael Trimarchi To: linux-amarula@amarulasolutions.com, Dario Binacchi , Tommaso Merciai Subject: [PATCH 01/11] mtd: nand: Get rid of busw parameter Date: Thu, 14 Jul 2022 09:51:21 +0200 Message-Id: <20220714075131.411548-1-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=didIiQ2b; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Upstream commit 29a198a1592d83f2bc1be3b2631b3bcf3d5b380f Auto-detection functions are passed a busw parameter to retrieve the actual NAND bus width and eventually set the correct value in chip->options. Rework the nand_get_flash_type() function to get rid of this extra parameter and let detection code directly set the NAND_BUSWIDTH_16 flag in chip->options if needed. Signed-off-by: Boris Brezillon Acked-by: Richard Weinberger Reviewed-by: Marek Vasut Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/nand_base.c | 59 +++++++++++++++++--------------- 1 file changed, 32 insertions(+), 27 deletions(-) diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 6f81257cf1..9244287b10 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -3890,8 +3890,7 @@ static void nand_onfi_detect_micron(struct nand_chip *chip, /* * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise. */ -static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, - int *busw) +static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip) { struct nand_onfi_params *p = &chip->onfi_params; char id[4]; @@ -3963,9 +3962,7 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, chip->bits_per_cell = p->bits_per_cell; if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS) - *busw = NAND_BUSWIDTH_16; - else - *busw = 0; + chip->options |= NAND_BUSWIDTH_16; if (p->ecc_bits != 0xff) { chip->ecc_strength_ds = p->ecc_bits; @@ -3995,8 +3992,7 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, return 1; } #else -static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, - int *busw) +static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip) { return 0; } @@ -4005,8 +4001,7 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, /* * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise. */ -static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip, - int *busw) +static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip) { struct nand_jedec_params *p = &chip->jedec_params; struct jedec_ecc_info *ecc; @@ -4068,9 +4063,7 @@ static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip, chip->bits_per_cell = p->bits_per_cell; if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS) - *busw = NAND_BUSWIDTH_16; - else - *busw = 0; + chip->options |= NAND_BUSWIDTH_16; /* ECC info */ ecc = &p->ecc_info[0]; @@ -4160,7 +4153,7 @@ static int nand_get_bits_per_cell(u8 cellinfo) * manufacturer-specific "extended ID" decoding patterns. */ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, - u8 id_data[8], int *busw) + u8 id_data[8]) { int extid, id_len; /* The 3rd id byte holds MLC / multichip data */ @@ -4213,7 +4206,6 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, /* Calc blocksize */ mtd->erasesize = (128 * 1024) << (((extid >> 1) & 0x04) | (extid & 0x03)); - *busw = 0; } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX && !nand_is_slc(chip)) { unsigned int tmp; @@ -4254,7 +4246,6 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, mtd->erasesize = 768 * 1024; else mtd->erasesize = (64 * 1024) << tmp; - *busw = 0; } else { /* Calc pagesize */ mtd->writesize = 1024 << (extid & 0x03); @@ -4267,7 +4258,9 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, mtd->erasesize = (64 * 1024) << (extid & 0x03); extid >>= 2; /* Get buswidth information */ - *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; + /* Get buswidth information */ + if (extid & 0x1) + chip->options |= NAND_BUSWIDTH_16; /* * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per @@ -4293,15 +4286,13 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, * the chip. */ static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, - struct nand_flash_dev *type, u8 id_data[8], - int *busw) + struct nand_flash_dev *type, u8 id_data[8]) { int maf_id = id_data[0]; mtd->erasesize = type->erasesize; mtd->writesize = type->pagesize; mtd->oobsize = mtd->writesize / 32; - *busw = type->options & NAND_BUSWIDTH_16; /* All legacy ID NAND are small-page, SLC */ chip->bits_per_cell = 1; @@ -4363,7 +4354,7 @@ static inline bool is_full_id_nand(struct nand_flash_dev *type) } static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, - struct nand_flash_dev *type, u8 *id_data, int *busw) + struct nand_flash_dev *type, u8 *id_data) { if (!strncmp((char *)type->id, (char *)id_data, type->id_len)) { mtd->writesize = type->pagesize; @@ -4378,8 +4369,6 @@ static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, chip->onfi_timing_mode_default = type->onfi_timing_mode_default; - *busw = type->options & NAND_BUSWIDTH_16; - if (!mtd->name) mtd->name = type->name; @@ -4441,9 +4430,24 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, if (!type) type = nand_flash_ids; + /* + * Save the NAND_BUSWIDTH_16 flag before letting auto-detection logic + * override it. + * This is required to make sure initial NAND bus width set by the + * NAND controller driver is coherent with the real NAND bus width + * (extracted by auto-detection code). + */ + busw = chip->options & NAND_BUSWIDTH_16; + + /* + * The flag is only set (never cleared), reset it to its default value + * before starting auto-detection. + */ + chip->options &= ~NAND_BUSWIDTH_16; + for (; type->name != NULL; type++) { if (is_full_id_nand(type)) { - if (find_full_id_nand(mtd, chip, type, id_data, &busw)) + if (find_full_id_nand(mtd, chip, type, id_data)) goto ident_done; } else if (*dev_id == type->dev_id) { break; @@ -4453,11 +4457,11 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, chip->onfi_version = 0; if (!type->name || !type->pagesize) { /* Check if the chip is ONFI compliant */ - if (nand_flash_detect_onfi(mtd, chip, &busw)) + if (nand_flash_detect_onfi(mtd, chip)) goto ident_done; /* Check if the chip is JEDEC compliant */ - if (nand_flash_detect_jedec(mtd, chip, &busw)) + if (nand_flash_detect_jedec(mtd, chip)) goto ident_done; } @@ -4471,10 +4475,11 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, if (!type->pagesize) { /* Decode parameters from extended ID */ - nand_decode_ext_id(mtd, chip, id_data, &busw); + nand_decode_ext_id(mtd, chip, id_data); } else { - nand_decode_id(mtd, chip, type, id_data, &busw); + nand_decode_id(mtd, chip, type, id_data); } + /* Get chip options */ chip->options |= type->options; From patchwork Thu Jul 14 07:51:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Nazzareno Trimarchi X-Patchwork-Id: 2144 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ej1-f69.google.com (mail-ej1-f69.google.com [209.85.218.69]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id C63253F013 for ; Thu, 14 Jul 2022 09:51:39 +0200 (CEST) Received: by mail-ej1-f69.google.com with SMTP id hs16-20020a1709073e9000b0072b73a28465sf422372ejc.17 for ; Thu, 14 Jul 2022 00:51:39 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1657785099; cv=pass; d=google.com; s=arc-20160816; b=IgmoegOWQ64gSeCuwuJvp6AlNQehiE38lxt8zk3rS8lG4q8x0LFM1mjZDpIV09YhmS S/4psvengY2Dxla53Rk6zWlrXyav78CCRLIgdx1sYclr6nOkPd6j/B0CrEbfZC7kqGo8 l+Etildo4lskJzXW9R85Jrs/QhQyw+ulwT+bOJIl7EPl7l2OSSNbPCK/mpNiRFCKi/Dg PmnMITXmG1RI5ru49QsHNU0z6+rMyt34kgShmI0GxDfoJFcAnS35Scob083FGXb5aJlU gF+PsGKlUnfEMnCEkYOrTWjFswBhl0bFfNQSjZGGAjmQ2IDaO7O2bxWuFBLByQh/MnSp BExw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=zG6wjqM5pKhjIObcbq+1697BitA63oTxB0xoc3v5vjg=; b=bcBH3hfsxJWGhQNfuNiVWILhbnBeR6vJ++rQvXniGpkV/yFGDh9GyhL4l+/5Y55Qu0 gUYQS5ni4Kn+0rG5WdOS0P2Te0bgbTo1uhck21+/fM9h880RvFrHERXgszcIG4E5sHoM RJqsEaJJU8GWbfNwwWGjH2wu5UPbPZ9jToRx0RAlD9XqGCEsic7o8fDuQ5pDdOuKBTSm QskBTFS27xFcE0MQ6nm/CPg6WTFYl22VzAxVmC7jFIG7+N+BDHS9XHs34SfCaCKZHJjk GKJKUn3S3HTsdeavBnfYiO0YXgGqCL91sS4iZ0fvzLounJgyNp61L7xANbSDWb4f/QT+ WSzw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=htSvhErT; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :x-original-sender:x-original-authentication-results:precedence :mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=zG6wjqM5pKhjIObcbq+1697BitA63oTxB0xoc3v5vjg=; b=T/EVXIFUC+aQTc2uSNYwJFe9vYQf+CKNYn4LEXV1Jw3laXnsaN4aHQC/Lr4PjtlLHd YYSl6RR2dFJtn2PIa4zBkpL/0+MYEfcR3oS+Bvs++e38OFHwVfkxUjQXfA5gC/9ACZrn Rb/VbNeeyqIzUr4WnxOhbJ2Sgvl7nJ+d2TRys= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=zG6wjqM5pKhjIObcbq+1697BitA63oTxB0xoc3v5vjg=; b=knI+K8Cm/cpXfMexDmVuCE9rD5Jrv+YzmFA1OtbkNOukl1OavY/kF+1nux46jPF1ut L3OVKAAjYf3sdndDqF4VdGoSS1y7jEogi2hM1rgC2wxdbLkWy0G9Lh+ovK54Pw1BfVoa bpUSi29hgpijWjCy19hXzHtKEj9HHmkn6qVsJ9akjBomREi9rLzdbiFfI4WAO/ixdl1Y bwmPRPck6/NT/oS1ezYm3vjDKGvIbgXpyIGIOcp2Wm0f0mmiMHEpWMl5HmoalbAIcWT7 ChF8zlqGalXyWcrZvEe3F/UW92QF4QBFtYRFqbpwAO2nmvQaZJPmUnLbbzvmvTWZLHoy qWFg== X-Gm-Message-State: AJIora83ebFVqwCUYG8Ovtk7e4Bv4U5QJTUiV0xCkKPKezR1dEfR1M+0 taMuQFE2hsECkoEt1G+k/36uE7ZJ X-Google-Smtp-Source: AGRyM1uUWiAajOd7qkOVJkD5v6Xy54lX87YVcGgZIQnBvXCjqjL9tLiivIzJNfD9DCbB3qGvdbN15A== X-Received: by 2002:a05:6402:248f:b0:43a:b89c:20e3 with SMTP id q15-20020a056402248f00b0043ab89c20e3mr10732527eda.335.1657785099437; Thu, 14 Jul 2022 00:51:39 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a05:6402:35d5:b0:43a:7724:247e with SMTP id z21-20020a05640235d500b0043a7724247els186139edc.2.gmail; Thu, 14 Jul 2022 00:51:38 -0700 (PDT) X-Received: by 2002:a05:6402:2553:b0:43a:caa2:4956 with SMTP id l19-20020a056402255300b0043acaa24956mr10442277edb.406.1657785098061; Thu, 14 Jul 2022 00:51:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657785098; cv=none; d=google.com; s=arc-20160816; b=YjZntV1jEoyc/pKBX+GQMgS8f+GINknTeAPkyiwG0D8X0qQcKMs4KB2IG4toHdsYtz wMIjnJ3Q1t9iI0l8hH1y7OmZXWnr8BlLFzjpj1PSKLhBFZickjhSoVi8H64odpkk3NsP ek0/FEjmz9qpiVnI6t0Qz2ArJXw9SrFjFhrg8p92U1VfG1FHDURIg8b1fNCELTZn/t6D PJ9vP59e+R2Yn3dC8ga/rrRSqMlOLnQ/dwAkmSTHtWLISvLlephQZ4JrC3F5Qe6xnjSp IFC4EqGn6E+V2INvQt/EKrQAMb9BxCOD9mMzU8Pqr8OSddQkpQJM779KgJ8Zi1UMulNt uS9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=Gv8SBLd9l2dLRbvszGJpHjk1PR74fLOlZSaAeCY0NBQ=; b=J6Tab+MMegvD1WXQH+X/W4SWAU9a2dyFzSeMKUGUcswHuJwOIdm0aNsLRvEs/83GQe s5L6UMycEUTA5UtZN/B3aF96C5v0tma/ASSh22bvXZaHcQ+n87PW1PoJ7ZwX5k3jo/nV 2iS2AwBToD+3f0q2SIOPD3unvNnNBqDyGALT/8woELbgwkB0eBZnmJ7C6xurszH99cxU Ty3ZorRbtVqb0M9Mvvj3G2Yyu15gI4/92ieUkS1gs+mWiFgLB/5Z9irSMg1cNknDrkUX zTtl3tBZSZyLsGhZRfStD3odnnOcUZBKQ0SqqAaKZyTYnEEe2bfZO4wQ6xoVx/JLaDRm Z/WA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=htSvhErT; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id dk4-20020a170906f0c400b0071d538ee4dfsor297183ejb.46.2022.07.14.00.51.38 for (Google Transport Security); Thu, 14 Jul 2022 00:51:38 -0700 (PDT) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:907:948e:b0:72d:3fd2:5da0 with SMTP id dm14-20020a170907948e00b0072d3fd25da0mr5337596ejc.225.1657785097316; Thu, 14 Jul 2022 00:51:37 -0700 (PDT) Received: from panicking.amarulasolutions.com ([2.198.242.86]) by smtp.gmail.com with ESMTPSA id r23-20020a170906a21700b0072b616ade26sm369252ejy.216.2022.07.14.00.51.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 00:51:36 -0700 (PDT) From: Michael Trimarchi To: linux-amarula@amarulasolutions.com, Dario Binacchi , Tommaso Merciai Subject: [PATCH 02/11] mtd: nand: Store nand ID in struct nand_chip Date: Thu, 14 Jul 2022 09:51:22 +0200 Message-Id: <20220714075131.411548-2-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220714075131.411548-1-michael@amarulasolutions.com> References: <20220714075131.411548-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=htSvhErT; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Upstream commit 7f501f0a72036dc29ad9a53811474c393634b401 Store the NAND ID in struct nand_chip to avoid passing id_data and id_len as function parameters. Signed-off-by: Boris Brezillon Acked-by: Richard Weinberger Reviewed-by: Marek Vasut Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/nand_base.c | 54 ++++++++++++++++---------------- include/linux/mtd/rawnand.h | 15 +++++++++ 2 files changed, 42 insertions(+), 27 deletions(-) diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 9244287b10..6e964275e5 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4152,16 +4152,14 @@ static int nand_get_bits_per_cell(u8 cellinfo) * chip. The rest of the parameters must be decoded according to generic or * manufacturer-specific "extended ID" decoding patterns. */ -static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, - u8 id_data[8]) +static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip) { int extid, id_len; /* The 3rd id byte holds MLC / multichip data */ - chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); + chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]); /* The 4th id byte is the important one */ - extid = id_data[3]; - - id_len = nand_id_len(id_data, 8); + extid = chip->id.data[3]; + id_len = chip->id.len; /* * Field definitions are in the following datasheets: @@ -4172,8 +4170,8 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung * ID to decide what to do. */ - if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG && - !nand_is_slc(chip) && id_data[5] != 0x00) { + if (id_len == 6 && chip->id.data[0] == NAND_MFR_SAMSUNG && + !nand_is_slc(chip) && chip->id.data[5] != 0x00) { /* Calc pagesize */ mtd->writesize = 2048 << (extid & 0x03); extid >>= 2; @@ -4206,7 +4204,7 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, /* Calc blocksize */ mtd->erasesize = (128 * 1024) << (((extid >> 1) & 0x04) | (extid & 0x03)); - } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX && + } else if (id_len == 6 && chip->id.data[0] == NAND_MFR_HYNIX && !nand_is_slc(chip)) { unsigned int tmp; @@ -4270,10 +4268,10 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, * 110b -> 24nm * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC */ - if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA && + if (id_len >= 6 && chip->id.data[0] == NAND_MFR_TOSHIBA && nand_is_slc(chip) && - (id_data[5] & 0x7) == 0x6 /* 24nm */ && - !(id_data[4] & 0x80) /* !BENAND */) { + (chip->id.data[5] & 0x7) == 0x6 /* 24nm */ && + !(chip->id.data[4] & 0x80) /* !BENAND */) { mtd->oobsize = 32 * mtd->writesize >> 9; } @@ -4286,9 +4284,9 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, * the chip. */ static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, - struct nand_flash_dev *type, u8 id_data[8]) + struct nand_flash_dev *type) { - int maf_id = id_data[0]; + int maf_id = chip->id.data[0]; mtd->erasesize = type->erasesize; mtd->writesize = type->pagesize; @@ -4303,11 +4301,11 @@ static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, * listed in nand_ids table. * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) */ - if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00 - && id_data[6] == 0x00 && id_data[7] == 0x00 + if (maf_id == NAND_MFR_AMD && chip->id.data[4] != 0x00 && chip->id.data[5] == 0x00 + && chip->id.data[6] == 0x00 && chip->id.data[7] == 0x00 && mtd->writesize == 512) { mtd->erasesize = 128 * 1024; - mtd->erasesize <<= ((id_data[3] & 0x03) << 1); + mtd->erasesize <<= ((chip->id.data[3] & 0x03) << 1); } } @@ -4317,9 +4315,9 @@ static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, * page size, cell-type information). */ static void nand_decode_bbm_options(struct mtd_info *mtd, - struct nand_chip *chip, u8 id_data[8]) + struct nand_chip *chip) { - int maf_id = id_data[0]; + int maf_id = chip->id.data[0]; /* Set the bad block position */ if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16)) @@ -4354,14 +4352,14 @@ static inline bool is_full_id_nand(struct nand_flash_dev *type) } static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, - struct nand_flash_dev *type, u8 *id_data) + struct nand_flash_dev *type) { - if (!strncmp((char *)type->id, (char *)id_data, type->id_len)) { + if (!strncmp((char *)type->id, (char *)chip->id.data, type->id_len)) { mtd->writesize = type->pagesize; mtd->erasesize = type->erasesize; mtd->oobsize = type->oobsize; - chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); + chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]); chip->chipsize = (uint64_t)type->chipsize << 20; chip->options |= type->options; chip->ecc_strength_ds = NAND_ECC_STRENGTH(type); @@ -4387,7 +4385,7 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, { int busw, ret; int maf_idx; - u8 id_data[8]; + u8 *id_data = chip->id.data; /* * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) @@ -4445,9 +4443,11 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, */ chip->options &= ~NAND_BUSWIDTH_16; + chip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data)); + for (; type->name != NULL; type++) { if (is_full_id_nand(type)) { - if (find_full_id_nand(mtd, chip, type, id_data)) + if (find_full_id_nand(mtd, chip, type)) goto ident_done; } else if (*dev_id == type->dev_id) { break; @@ -4475,9 +4475,9 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, if (!type->pagesize) { /* Decode parameters from extended ID */ - nand_decode_ext_id(mtd, chip, id_data); + nand_decode_ext_id(mtd, chip); } else { - nand_decode_id(mtd, chip, type, id_data); + nand_decode_id(mtd, chip, type); } /* Get chip options */ @@ -4515,7 +4515,7 @@ ident_done: return ERR_PTR(-EINVAL); } - nand_decode_bbm_options(mtd, chip, id_data); + nand_decode_bbm_options(mtd, chip); /* Calculate the address shift from the page size */ chip->page_shift = ffs(mtd->writesize) - 1; diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 3417ca2a0d..f2c6a978cb 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -507,6 +507,19 @@ static inline void nand_hw_control_init(struct nand_hw_control *nfc) init_waitqueue_head(&nfc->wq); } +/* The maximum expected count of bytes in the NAND ID sequence */ +#define NAND_MAX_ID_LEN 8 + +/** + * struct nand_id - NAND id structure + * @data: buffer containing the id bytes. + * @len: ID length. + */ +struct nand_id { + u8 data[NAND_MAX_ID_LEN]; + int len; +}; + /** * struct nand_ecc_step_info - ECC step information of ECC engine * @stepsize: data bytes per ECC step @@ -888,6 +901,8 @@ nand_get_sdr_timings(const struct nand_data_interface *conf) struct nand_chip { struct mtd_info mtd; + struct nand_id id; + void __iomem *IO_ADDR_R; void __iomem *IO_ADDR_W; From patchwork Thu Jul 14 07:51:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Nazzareno Trimarchi X-Patchwork-Id: 2145 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f70.google.com (mail-ed1-f70.google.com [209.85.208.70]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id C6DDD3F013 for ; Thu, 14 Jul 2022 09:51:41 +0200 (CEST) Received: by mail-ed1-f70.google.com with SMTP id z14-20020a056402274e00b0043ae5c003c1sf985081edd.9 for ; Thu, 14 Jul 2022 00:51:41 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1657785101; cv=pass; d=google.com; s=arc-20160816; b=Ai41rQnStM+ic01W6Sg+spfOGYf10OMTC2S4/c3DCe0kHkYWrMt5aI41zQS++9Zjrz Py6Q9pP6MhzZm9scPL5s/XCgVxuR9jt4Rne46b1w7lNpkrJIgqMACC8Ha31HKP3XCHvL 9+OjtvTxo4+jqrjvvfSeiydlcyU77fXIzHywREYw6H867bkuk/BD9mA3N1LSdXSEQE9f KHQaPgLkZA5kkufk10xHxFpyN+uwfMcarIBfrz8tk5cmBfohwRWCWUFznvm2wl2x1pMi ZSjvvOvAQxx9NEIcbuHCIs7Q9ujPhXoa00M5SmSRTqCMPbvrDGjhP0+gr3pvPyxaNnBl xyuw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=JpXqIHIv235h6o++wG12BeZEvn5KaWZoPpEUGWFr7cE=; b=qqSh4vd4hYdh8xwYNMFizC1/XsuBmWy+ve2TgzHX6e6DhqmXL2lJZ7douQXS69NuIp i7PtdnxS70eQBjR93wkrdIA0NaE/6IX4o4s++wrxvwPwXVNA1kwRmO60dlf5xBdY924g pwzuh094s8izAXLQ5Q0evEeorSa9lpPdPwllxs3wxclWum/Cmn4UDC7QfasbXr2tOPQl yoA2E4YngdJiX6OHfg+bDKifIx6YtGNu/7Hg4wMjebZzuBRWptFazmKhGAI9WPEVi0gq KPGk6PxRvSXrw53GAqbepQnmEHWA+elR8ZxcCJC+k8XWNndA2VIeAGRLDhhib0t6Czeb x/2g== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=pnztSpIq; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :x-original-sender:x-original-authentication-results:precedence :mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=JpXqIHIv235h6o++wG12BeZEvn5KaWZoPpEUGWFr7cE=; b=JnJO5K0khAjOHHHdGPCt6/BQOUZ9rwivd3/7xH6XZkvWVJoq+Q9Rh07yCV/x38URDC HKcQUiet3FZrTpR/DVP4Xtj54i8w7276bG+xwIuMXwJoxp5E7IXMxmkVi2jgP5OHfDWU 8ABA9vxRMq7mxnoQ20PHXfHqKF23jPOULXr8E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=JpXqIHIv235h6o++wG12BeZEvn5KaWZoPpEUGWFr7cE=; b=nOcmQYzcub1pRlq1IQRn9q/ykaB77hVFoJfojadEHmYiiEsrDkJoXBd98NRW5hPBEm 3RrgyXh6gqrn0/rhJA1YyyhZMe1Qe1JQIlRt5IePxLisPZWhsxZdJhippZNEyd7WjwbJ FzDoAPjqhCDwRmqw4/SOIRH7cXTpUvbDgKQKS7GBcskdJTmb2OOOC5RNw0QAbKpjqji4 M/0ojW1A7JppkpVCNKgKaBuzldUnPWIVse/vztQh8jG9oU/f0GmXSuu+u8Rpzr8tfR+J uHOlEMGBtvkwL2zW6ZAFH0xvQGQiHjDHmRfwd1WthjBSmFkneFGDgrzKHewu0QSfMfhL 7UHQ== X-Gm-Message-State: AJIora8jK8fW80RYUN5f5YThD4Xh5GbZ1yOhWvxzneluCxAC/6aHkE3W nfsc2WamdZetaq+zMtrC9zc3YFGr X-Google-Smtp-Source: AGRyM1s3pOg8AwpLOZEXglUgAIgZJmIc3FQirpM74YOKTmntY0LpCVMf+J2W0y8tQpFR/hNGIWri+A== X-Received: by 2002:a17:907:6e02:b0:72b:9f16:1bc5 with SMTP id sd2-20020a1709076e0200b0072b9f161bc5mr6609690ejc.676.1657785101486; Thu, 14 Jul 2022 00:51:41 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:907:7f27:b0:72b:6e70:8c8c with SMTP id qf39-20020a1709077f2700b0072b6e708c8cls2307209ejc.10.gmail; Thu, 14 Jul 2022 00:51:40 -0700 (PDT) X-Received: by 2002:a17:907:3e07:b0:72e:e1e2:1415 with SMTP id hp7-20020a1709073e0700b0072ee1e21415mr952080ejc.596.1657785100097; Thu, 14 Jul 2022 00:51:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657785100; cv=none; d=google.com; s=arc-20160816; b=k5mBz7pPn3QxjU+YZWUvLVWr1WR80M0SlEicCO3z02AsBbywFm7NTjBNYGeipGgZso oqZsdQiAYxvXYycFR4l8OX+7o35kdMsPsoqS5VBae2jAj9Beh2C3WveJQ7gqbitqMXnt ej01nJ96snCUZsmBJxLhKKy+/SrFcT9v6PAsweEXbpJ5rPCpZLSwE639P97ViaPfdJzI enYRiJn//kjREjpPr7zh6I1qls7IxX1UJ9+pJN6+wXVWzPwPE31QGc7SlsrBxB12+2eW ZNM25EZ+x9Q3g773Y/AaV7665Kc89SPNjkA2IlYmkPiRLk42jwdSC+pfCBNbZCMh9nNY ck2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=ygNrYdotaJQDkfnb9m1VDTVvYwwV3uPyyciPN0sEPOM=; b=ZyJtK377KfM8zOP7KDY3/o9QrftjJH+EfoWxzktMIdl/U1hRNbzORa+fwGOeDyrhL5 4CNQg9wz29mOkwpfng5KZyaGwCqUSp0AzWsrw4dsOj87LDbh1u9ZjODQeVHrFklj6XPt lKga2lAuuxnjpesvK7N7rXhwIDkK8CrqgfqrOOMfSbd5lAX/2jycsF7jQcOdqcMTvqfz Qxtwmlx0l4fReA3N9SI4wuariHVVbAxeSrTYE0Qrkv6UJ8UzumC96TM21fnnLIgz/609 8mPyHK262G6u/VY5UYVCVi1RtKZy0Iww69CzwIg0ivlYwDg3gmeRdzvLHSiUWKJCHZlF UeMw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=pnztSpIq; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id hq26-20020a1709073f1a00b006f3a0bc0cf1sor313287ejc.128.2022.07.14.00.51.40 for (Google Transport Security); Thu, 14 Jul 2022 00:51:40 -0700 (PDT) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:907:28d4:b0:72b:49c0:d04a with SMTP id en20-20020a17090728d400b0072b49c0d04amr7613123ejc.141.1657785099346; Thu, 14 Jul 2022 00:51:39 -0700 (PDT) Received: from panicking.amarulasolutions.com ([2.198.242.86]) by smtp.gmail.com with ESMTPSA id r23-20020a170906a21700b0072b616ade26sm369252ejy.216.2022.07.14.00.51.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 00:51:38 -0700 (PDT) From: Michael Trimarchi To: linux-amarula@amarulasolutions.com, Dario Binacchi , Tommaso Merciai Subject: [PATCH 03/11] mtd: nand: Add manufacturer specific initialization/detection steps Date: Thu, 14 Jul 2022 09:51:23 +0200 Message-Id: <20220714075131.411548-3-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220714075131.411548-1-michael@amarulasolutions.com> References: <20220714075131.411548-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=pnztSpIq; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Upstream commit abbe26d144ec22bb067fa414d717b9f7ca2e12bd A lot of NANDs are implementing generic features in a non-generic way, or are providing advanced auto-detection logic where the NAND ID bytes meaning changes with the NAND generation. Providing this vendor specific initialization step will allow us to get rid of full-id entries in the nand_ids table or all the vendor specific cases added over the time in the generic NAND ID decoding logic. Signed-off-by: Boris Brezillon Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/nand_base.c | 90 +++++++++++++++++++++++++------- include/linux/mtd/rawnand.h | 30 +++++++++++ 2 files changed, 102 insertions(+), 18 deletions(-) diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 6e964275e5..d9024432b7 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4278,6 +4278,39 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip) } } +/* + * Manufacturer detection. Only used when the NAND is not ONFI or JEDEC + * compliant and does not have a full-id or legacy-id entry in the nand_ids + * table. + */ +static void nand_manufacturer_detect(struct mtd_info *mtd, struct nand_chip *chip) +{ + /* + * Try manufacturer detection if available and use + * nand_decode_ext_id() otherwise. + */ + if (chip->manufacturer.desc && chip->manufacturer.desc->ops && + chip->manufacturer.desc->ops->detect) + chip->manufacturer.desc->ops->detect(chip); + else + nand_decode_ext_id(mtd, chip); +} + +/* + * Manufacturer initialization. This function is called for all NANDs including + * ONFI and JEDEC compliant ones. + * Manufacturer drivers should put all their specific initialization code in + * their ->init() hook. + */ +static int nand_manufacturer_init(struct nand_chip *chip) +{ + if (!chip->manufacturer.desc || !chip->manufacturer.desc->ops || + !chip->manufacturer.desc->ops->init) + return 0; + + return chip->manufacturer.desc->ops->init(chip); +} + /* * Old devices have chip data hardcoded in the device ID table. nand_decode_id * decodes a matching ID table entry and assigns the MTD size parameters for @@ -4375,6 +4408,26 @@ static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, return false; } +/** + * nand_get_manufacturer_desc - Get manufacturer information from the + * manufacturer ID + * @id: manufacturer ID + * + * Returns a nand_manufacturer_desc object if the manufacturer is defined + * in the NAND manufacturers database, NULL otherwise. + */ +static const struct nand_manufacturers *nand_get_manufacturer_desc(u8 id) +{ + int i; + + for (i = 0; nand_manuf_ids[i].id != 0x0; i++) { + if (nand_manuf_ids[i].id == id) + return &nand_manuf_ids[i]; + } + + return NULL; +} + /* * Get the flash and manufacturer id and lookup if the type is supported. */ @@ -4383,8 +4436,8 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, int *maf_id, int *dev_id, struct nand_flash_dev *type) { + const struct nand_manufacturers *manufacturer_desc; int busw, ret; - int maf_idx; u8 *id_data = chip->id.data; /* @@ -4425,6 +4478,12 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, return ERR_PTR(-ENODEV); } + chip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data)); + + /* Try to identify manufacturer */ + manufacturer_desc = nand_get_manufacturer_desc(*maf_id); + chip->manufacturer.desc = manufacturer_desc; + if (!type) type = nand_flash_ids; @@ -4443,8 +4502,6 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, */ chip->options &= ~NAND_BUSWIDTH_16; - chip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data)); - for (; type->name != NULL; type++) { if (is_full_id_nand(type)) { if (find_full_id_nand(mtd, chip, type)) @@ -4474,8 +4531,7 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, chip->chipsize = (uint64_t)type->chipsize << 20; if (!type->pagesize) { - /* Decode parameters from extended ID */ - nand_decode_ext_id(mtd, chip); + nand_manufacturer_detect(mtd, chip); } else { nand_decode_id(mtd, chip, type); } @@ -4491,12 +4547,6 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, chip->options &= ~NAND_SAMSUNG_LP_OPTIONS; ident_done: - /* Try to identify manufacturer */ - for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) { - if (nand_manuf_ids[maf_idx].id == *maf_id) - break; - } - if (chip->options & NAND_BUSWIDTH_AUTO) { WARN_ON(chip->options & NAND_BUSWIDTH_16); chip->options |= busw; @@ -4508,7 +4558,7 @@ ident_done: */ pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", *maf_id, *dev_id); - pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name); + pr_info("%s %s\n", manufacturer_desc->name, mtd->name); pr_warn("bus width %d instead %d bit\n", (chip->options & NAND_BUSWIDTH_16) ? 16 : 8, busw ? 16 : 8); @@ -4541,28 +4591,32 @@ ident_done: if (mtd->writesize > 512 && chip->cmdfunc == nand_command) chip->cmdfunc = nand_command_lp; + ret = nand_manufacturer_init(chip); + if (ret) + return ERR_PTR(ret); + pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", *maf_id, *dev_id); #ifdef CONFIG_SYS_NAND_ONFI_DETECTION if (chip->onfi_version) - pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, + pr_info("%s %s\n", manufacturer_desc->name, chip->onfi_params.model); else if (chip->jedec_version) - pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, + pr_info("%s %s\n", manufacturer_desc->name, chip->jedec_params.model); else - pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, + pr_info("%s %s\n", manufacturer_desc->name, type->name); #else if (chip->jedec_version) - pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, + pr_info("%s %s\n", manufacturer_desc->name, chip->jedec_params.model); else - pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, + pr_info("%s %s\n", manufacturer_desc->name, type->name); - pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, + pr_info("%s %s\n", manufacturer_desc->name, type->name); #endif diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index f2c6a978cb..57fe7fb47b 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -796,6 +796,17 @@ nand_get_sdr_timings(const struct nand_data_interface *conf) return &conf->timings.sdr; } +/** + * struct nand_manufacturer_ops - NAND Manufacturer operations + * @detect: detect the NAND memory organization and capabilities + * @init: initialize all vendor specific fields (like the ->read_retry() + * implementation) if any. + */ +struct nand_manufacturer_ops { + void (*detect)(struct nand_chip *chip); + int (*init)(struct nand_chip *chip); +}; + /** * struct nand_chip - NAND Private Flash Chip Data * @mtd: MTD device registered to the MTD framework @@ -897,6 +908,7 @@ nand_get_sdr_timings(const struct nand_data_interface *conf) * devices. * @priv: [OPTIONAL] pointer to private chip data * @write_page: [REPLACEABLE] High-level page write function + * @manufacturer: [INTERN] Contains manufacturer information */ struct nand_chip { @@ -983,6 +995,11 @@ struct nand_chip { struct nand_bbt_descr *badblock_pattern; void *priv; + + struct { + const struct nand_manufacturers *desc; + void *priv; + } manufacturer; }; static inline void nand_set_flash_node(struct nand_chip *chip, @@ -1016,6 +1033,17 @@ static inline void nand_set_controller_data(struct nand_chip *chip, void *priv) chip->priv = priv; } +static inline void nand_set_manufacturer_data(struct nand_chip *chip, + void *priv) +{ + chip->manufacturer.priv = priv; +} + +static inline void *nand_get_manufacturer_data(struct nand_chip *chip) +{ + return chip->manufacturer.priv; +} + /* * NAND Flash Manufacturer ID Codes */ @@ -1120,10 +1148,12 @@ struct nand_flash_dev { * struct nand_manufacturers - NAND Flash Manufacturer ID Structure * @name: Manufacturer name * @id: manufacturer ID code of device. + * @ops: manufacturer operations */ struct nand_manufacturers { int id; char *name; + const struct nand_manufacturer_ops *ops; }; extern struct nand_flash_dev nand_flash_ids[]; From patchwork Thu Jul 14 07:51:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Nazzareno Trimarchi X-Patchwork-Id: 2146 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ej1-f70.google.com (mail-ej1-f70.google.com [209.85.218.70]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id EF78C3F013 for ; Thu, 14 Jul 2022 09:51:43 +0200 (CEST) Received: by mail-ej1-f70.google.com with SMTP id gb37-20020a170907962500b0072b820af09dsf431746ejc.20 for ; Thu, 14 Jul 2022 00:51:43 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1657785103; cv=pass; d=google.com; s=arc-20160816; b=XiOAVovKd1bUtd6r4HTR9NbvUqnGXvbahZIzigsvCywVh6fd2F6kNcs3pDp5m/bHW1 BaCgmsxHgkcTEF9hlvOhj2gyPedZfhq8E2vfwLEl/PSA2B+Gmk/RvVMFUXSegn+SRxcr sWrJPbQtHAQCLXTOITdCOkg7HzrEpWXnZIdVGadLSR6TSdtNP1c2ptpEObb02iwlBQM9 Z0niQDK8ewVEbyRC3oSM7PYFoV8REcwE/GNWrk7QKUGrvW29rDE61yzWnsKFg1p8HVo+ mRK0JP4/6hDv3M7Kd57/TPRYw4x+vCi8ktyzMcLw/2vBzm1hzDcvYM+UgTiW+YsNGmoi AgoQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=aYPMDydZmLi411lOWXdUZW3qBs8z8UWYv5Ae3OedAHI=; b=gn3r9VBiHNHg9GIU+qHzefgzWwmMyu0sxp6JTj7o2A+8olIkF0IFt2ZkpdAJfYoduB UX6mxlImxusMrofpahGf5mTYFszzuiZ4BceMqs46KobqjwcLqLBG7D+pHF/M5BCV0vVr SRzGFMtH+kHaJHX/1E4Sv36VWdNnTs6widxJhh3pBkDF5o12fNgYDK2LV+KaaCLa7T18 Rr4B1ahZH/N4uF5aePh8y5NdTNE2XzpzoSQUi9NXJIMlASkLZ6k9WXW/ZfB7ibsXPozk t/Vhpf8oGQbdW9mkMJKHZqwRIsMtsCpXHcGWxtUla34L+tVe/uMWSBkTH5FjvfI2mhfu 5yOg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=mEpoWws5; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :x-original-sender:x-original-authentication-results:precedence :mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=aYPMDydZmLi411lOWXdUZW3qBs8z8UWYv5Ae3OedAHI=; b=mGlUcc+OPeD5gezHeh+YasHQI5GAPrEaG/A6jI66WJZdJ3IQS0tvc1gBxujJnV5aPj dfmlPPaGUR1JbjCQ4nnU8VgKNctDyKiC1LFTlPR47D6X9QPqkx6IO6RdemkSSIt+Z9u3 zhtftB+kIqDyxseVwp1/KVl4ZSs0nWz1ryI1I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=aYPMDydZmLi411lOWXdUZW3qBs8z8UWYv5Ae3OedAHI=; b=My5Yj70CvrfAvuEYimI92/HyDhcDbuMYTagiGwbyF8tjXR5ZHehgLyTOFJigbw+jch uZBDySRLN7zVQqspd4vBX3L4hR5HvL3j1Dd2L5kjlrQtVmLDASlSuGQSIaMa+cabUpvM 9/VAXcIvJTlcBOFS4HqC9IFg/MSIpEGJVl1OPQmFKMX8JLL/AWL+x+aT6OD62IdCiG4l 3M33SkRulNRUX9WQceN72ePkfmsJlvCTzE+a8fdwY6WNd42P02eCAX8G2ti35pnTM+YB lPCrrYKSC3swXzZ8cPtOI3EsAgUVtWCy7ACuDYDS2ghVTB+/xKHtUGPN44mWdHN8r2Uu Elow== X-Gm-Message-State: AJIora8IyDB310U6JZUOX+xwxL4lMouCd9zsV0nZfcO75dMh41bvaFsP Mho1zaVwWDP0XQMX8ANfcEzWLkJA X-Google-Smtp-Source: AGRyM1txX5gPjmOa1R5YZflz8qcSeouHdxh08V2EUQHM+FSp3cmzGBTxAavvkpCoFZVEb4p6agQJxQ== X-Received: by 2002:a05:6402:5510:b0:43a:76ff:b044 with SMTP id fi16-20020a056402551000b0043a76ffb044mr10736344edb.197.1657785103799; Thu, 14 Jul 2022 00:51:43 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:907:9603:b0:6ff:232a:2406 with SMTP id gb3-20020a170907960300b006ff232a2406ls4180959ejc.0.gmail; Thu, 14 Jul 2022 00:51:42 -0700 (PDT) X-Received: by 2002:a17:906:844b:b0:72b:54b9:b97d with SMTP id e11-20020a170906844b00b0072b54b9b97dmr7664226ejy.229.1657785102443; Thu, 14 Jul 2022 00:51:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657785102; cv=none; d=google.com; s=arc-20160816; b=LoqjPhenqaut8Yw1TD/SVWQ9F8GqQRXw79G5uhTTllNc0YyBwn8Jp4Uy2No0v/Hp1U PT32ergKQlxcIztA/ttHqVV0vFh1WhGmjMglQf7Qh6LHtrs1luOswxykiaoE2p1+UbiZ et9VbTAuvelV80BgxcCmHhMwTlpGXws7Q4CzEGoka7VIOO9kOrNKSU38eLzTHWZl6Qs0 Ufy5xKcYaax+uGfktcimclBMuaYbqGYX1xiMW3BbWeRS9FAnOybq6iqtcNfuLaAUr2PN F60qupdzCsXCIVwebCOeBCtDNOwyRH85PZk7WZTOJbj1+G6t3T55o+DhpKsZ9bsV8S8n oJQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=L+7ysmT4HEHTHKLZ7Cn7atYvU0yakssT+CAnPDUwQbY=; b=ZlY1AkrhQKdqzQb0DSi7XEqsMChBLR9M5iHTiRUBmUBTpOzWC1VIo9ncIr94OUKVSg D81u8iC7k6rE22enXdzQoJV6x26GJTJhQ1xKasLAeO3NQzM9G2oZEkxpWx3Q+kEAIMHv FhAYUwb1Yh3E/d7IxwGwtENk7acnceB89pl8Wdp1JYoDgPLXrPtfYNIdCYWZyG5tFPHF 9Nk7t9QonVL1ReNRWvX6ZR1cXqPqb1bRRHrjSi6AgHnxUuCHVKhiPGnJLdbnFpZjMe4G 0jFuXxSltDvHbNM1VYnLFscSAThJSoz0s8Qes/inMCd8qAGHV55xK/JqWy+WtV5kJ5g+ pj1Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=mEpoWws5; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id h22-20020a1709060f5600b007263150e3a6sor285430ejj.51.2022.07.14.00.51.42 for (Google Transport Security); Thu, 14 Jul 2022 00:51:42 -0700 (PDT) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:906:3f51:b0:712:3945:8c0d with SMTP id f17-20020a1709063f5100b0071239458c0dmr7487955ejj.302.1657785101736; Thu, 14 Jul 2022 00:51:41 -0700 (PDT) Received: from panicking.amarulasolutions.com ([2.198.242.86]) by smtp.gmail.com with ESMTPSA id r23-20020a170906a21700b0072b616ade26sm369252ejy.216.2022.07.14.00.51.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 00:51:41 -0700 (PDT) From: Michael Trimarchi To: linux-amarula@amarulasolutions.com, Dario Binacchi , Tommaso Merciai Subject: [PATCH 04/11] mtd: nand: Get rid of mtd variable in function calls Date: Thu, 14 Jul 2022 09:51:24 +0200 Message-Id: <20220714075131.411548-4-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220714075131.411548-1-michael@amarulasolutions.com> References: <20220714075131.411548-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=mEpoWws5; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , chip points to mtd. Passing chip is enough to have a reference to mtd when is necessary Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/nand_base.c | 20 +++++++++++--------- include/linux/mtd/rawnand.h | 3 +-- 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index d9024432b7..be1a6738c1 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4152,8 +4152,9 @@ static int nand_get_bits_per_cell(u8 cellinfo) * chip. The rest of the parameters must be decoded according to generic or * manufacturer-specific "extended ID" decoding patterns. */ -static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip) +static void nand_decode_ext_id(struct nand_chip *chip) { + struct mtd_info *mtd = &chip->mtd; int extid, id_len; /* The 3rd id byte holds MLC / multichip data */ chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]); @@ -4283,7 +4284,7 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip) * compliant and does not have a full-id or legacy-id entry in the nand_ids * table. */ -static void nand_manufacturer_detect(struct mtd_info *mtd, struct nand_chip *chip) +static void nand_manufacturer_detect(struct nand_chip *chip) { /* * Try manufacturer detection if available and use @@ -4293,7 +4294,7 @@ static void nand_manufacturer_detect(struct mtd_info *mtd, struct nand_chip *chi chip->manufacturer.desc->ops->detect) chip->manufacturer.desc->ops->detect(chip); else - nand_decode_ext_id(mtd, chip); + nand_decode_ext_id(chip); } /* @@ -4316,9 +4317,10 @@ static int nand_manufacturer_init(struct nand_chip *chip) * decodes a matching ID table entry and assigns the MTD size parameters for * the chip. */ -static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, +static void nand_decode_id(struct nand_chip *chip, struct nand_flash_dev *type) { + struct mtd_info *mtd = &chip->mtd; int maf_id = chip->id.data[0]; mtd->erasesize = type->erasesize; @@ -4431,11 +4433,11 @@ static const struct nand_manufacturers *nand_get_manufacturer_desc(u8 id) /* * Get the flash and manufacturer id and lookup if the type is supported. */ -struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, - struct nand_chip *chip, +struct nand_flash_dev *nand_get_flash_type(struct nand_chip *chip, int *maf_id, int *dev_id, struct nand_flash_dev *type) { + struct mtd_info *mtd = &chip->mtd; const struct nand_manufacturers *manufacturer_desc; int busw, ret; u8 *id_data = chip->id.data; @@ -4531,9 +4533,9 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, chip->chipsize = (uint64_t)type->chipsize << 20; if (!type->pagesize) { - nand_manufacturer_detect(mtd, chip); + nand_manufacturer_detect(chip); } else { - nand_decode_id(mtd, chip, type); + nand_decode_id(chip, type); } /* Get chip options */ @@ -4723,7 +4725,7 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips, nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16); /* Read the flash type */ - type = nand_get_flash_type(mtd, chip, &nand_maf_id, + type = nand_get_flash_type(chip, &nand_maf_id, &nand_dev_id, table); if (IS_ERR(type)) { diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 57fe7fb47b..d8141cb4d1 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -29,8 +29,7 @@ struct nand_flash_dev; struct device_node; /* Get the flash and manufacturer id and lookup if the type is supported. */ -struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, - struct nand_chip *chip, +struct nand_flash_dev *nand_get_flash_type(struct nand_chip *chip, int *maf_id, int *dev_id, struct nand_flash_dev *type); From patchwork Thu Jul 14 07:51:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Nazzareno Trimarchi X-Patchwork-Id: 2147 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f71.google.com (mail-ed1-f71.google.com [209.85.208.71]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id B84143F013 for ; Thu, 14 Jul 2022 09:51:45 +0200 (CEST) Received: by mail-ed1-f71.google.com with SMTP id n8-20020a05640205c800b00434fb0c150csf960485edx.19 for ; Thu, 14 Jul 2022 00:51:45 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1657785105; cv=pass; d=google.com; s=arc-20160816; b=L7ABFGeNZPReeGJZrDzw9T3n84HG4XAGvzNwUZ+9MkQW9rF/lkX9v+kCxteUgp7iFX skV0tykBNmvNGrWjlRfjd850zOn0ANAxydKqD5b+i96ssy+YQvmEK/zITTUJGoRGorhP EYDEs7uP6ORHgxbap1A1OThZv0XnYqn7MELosF/aV7qwkYabVe/5287Qx051LSPI5dtX eiVnfcQoVxmBc5upUnaZWsPTzB+QQ7ZKeJbjWAIXbpRuByZ32urlGQvza8JOXwI8FsDq +Jj8TBPrwZs3O8dAHsuGpcmG0wHjX89ITgH7BxVhoiZW086lxdaArwCmR9jxWNA7p6SI dzhA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=cYzKJjsY3u6TeHrlxCITAU4kuqViXCgubZkTJzQQFSo=; b=p0Zv39P5YkW48T4VRfU2G6ZHVFi2GqAE17RSwp28sefxfHMM7wkPUwc08KEdigN6o9 h2geE6AxPR09mI48Fw7TarhA81hd7XXwp0MBFsfolMDVCs0UTt3/MLmqsC0gY9l/yqML 7rDK8SGt+sXypt2S6kOHD4C0i5rnZEs2AW/BYIM1gALJfBud07wleRSUBeym9wi8hY3I YlFNs9q5AkIed3C1FIav2xaJDHgn17jAV+ApTeg45VTYl4wuTWrIu2nsn3Z9fKSn6BDT ONUNo5YjF4tpoleGoFnLwGBM/qMhzogASS5W0S1khCCNKAkSv8/Bj1m+WXvWbls6GqRZ RhaA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=rmdiUWnj; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :x-original-sender:x-original-authentication-results:precedence :mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=cYzKJjsY3u6TeHrlxCITAU4kuqViXCgubZkTJzQQFSo=; b=UK8gguX1ytZ7O4BWPbs00Mxg+CaaVG7uXAH9S8ngiaE9IARSh/QfHKXjRpKWRaX5wA Cq3KRZgI3NyAA5wH4kn5TgFXXy7p7pE6ze4EgfLcum4Nm/4lurfGbDJ7ykmySoKRRe5F nNMesn3Wnvk0Tc4tGmAoeJbSxYuZNbHAyCcpw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=cYzKJjsY3u6TeHrlxCITAU4kuqViXCgubZkTJzQQFSo=; b=7FC+gCKvinpCDNnBIfOHvlfCSxWi0jCFvwz02MNurSHUwLYwqJU4DdHwD6xVUNnyVs +avfxJHChB7wPqnslpcEizkGG0N/EjBhIBf1gkew5KmOvjk9DF2Ko8BAaw72mgG7zoQB u+oz/RjYs5jabIsSpJmlm8ta8HA8++WCn/CjYhBcB7hmizvj7er65CC1H70/xcwpoGos YkUGTlr3bTaOxs0yGRZIWKql2Jp17saeINHjrmxyNETpHRNg8+yLttG6sTfLbR8by0r/ w1sORpTAY38QPwc7vwTQt0y2qsK1nDiAZQVifiL0CZbKsR44vwRz1u85HyaIE/4uEr+6 a7yg== X-Gm-Message-State: AJIora8dubMZ9X1uicCHNH53UFvBQ2rq2Rm34Eb8er26zofIrfV/afRd z9JVz8TdpHIQAB3aVy3/CWwdamdV X-Google-Smtp-Source: AGRyM1sYWP19/AHVZTF+xCUumGoSt9xvvab1fMdHyCS8pr1403GAX1+0uM3fMdndpu/jM1mR9lLr2g== X-Received: by 2002:a05:6402:2b88:b0:43a:6c58:6c64 with SMTP id fj8-20020a0564022b8800b0043a6c586c64mr10831810edb.348.1657785105590; Thu, 14 Jul 2022 00:51:45 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a05:6402:34cc:b0:43a:d872:b6aa with SMTP id w12-20020a05640234cc00b0043ad872b6aals143516edc.0.gmail; Thu, 14 Jul 2022 00:51:44 -0700 (PDT) X-Received: by 2002:a05:6402:e85:b0:434:f9d9:3b18 with SMTP id h5-20020a0564020e8500b00434f9d93b18mr10828537eda.37.1657785104364; Thu, 14 Jul 2022 00:51:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657785104; cv=none; d=google.com; s=arc-20160816; b=P+fMbGyMDwwWsEowTu3IyB4Jw6yu0lQsbCPrynqCHJ4lBzmjSEGUPnjUlP1yWEsONu 6ecobbfl8iBmukS6tRtsIW5oq2h6v19ryNrXKqWMMhXxFCao35p9Fykq96kE9gZDGSis seIP9VzMlGQNIpu76ScQqqFTMUV6sswIwWwT5zIC9FECc79jM4GFiiuLCV+ERzZtIHEQ 1Hmh5hWwap8iKg8LssD1v7vfFhcH7Bn6NaDWeaiPV3BR5feI8Urcf9G940ogxDcesySp QTSHSI5Ca2yVx8pTdLATPXT2wwgwth4H5Z0JHRU4kKKOvRr1i7QDXm3SpQ/mcdJjaq43 pn6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=Wpdt+COOKHXEpR+08DmOXQXCpR/U8hBWkNJWEsLZGVA=; b=nqNRhCuOBpM4u/unCSZl1XCq/puheOetQ8echeiCZTPXDyqHlTFVAX0XBXsNiewFNN PhlOne78fk6CL2kNXFR+NJbsgzCyMXVzAHNIq9aqDO7N8ax5hhZ4qY0WuYQneSw9/AUE ERFtt5Fd4RF0LMFFPl6qJY9scXtVXS4ovQy90ciCZYaIxjPLpuAh4TNnJ259VgTSdKHj Gsm8yDokf1qO+MPYsMwmLD+obrxyUcY63ZjldxZGTKw3OGBbtmgzQhXS9MKeXNxcIa6E zz8nFzsqpFZ6kcXLg9hJFH3n8qcp83ifGpb0ZZj5z6WJEl0QOLzoR/1V8Y8ZE2GozDr5 mISQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=rmdiUWnj; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id 10-20020a170906058a00b007033fef81a4sor312486ejn.56.2022.07.14.00.51.44 for (Google Transport Security); Thu, 14 Jul 2022 00:51:44 -0700 (PDT) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:907:2bde:b0:72b:4da0:6f3c with SMTP id gv30-20020a1709072bde00b0072b4da06f3cmr7289712ejc.623.1657785103706; Thu, 14 Jul 2022 00:51:43 -0700 (PDT) Received: from panicking.amarulasolutions.com ([2.198.242.86]) by smtp.gmail.com with ESMTPSA id r23-20020a170906a21700b0072b616ade26sm369252ejy.216.2022.07.14.00.51.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 00:51:43 -0700 (PDT) From: Michael Trimarchi To: linux-amarula@amarulasolutions.com, Dario Binacchi , Tommaso Merciai Subject: [PATCH 05/11] mtd: nand: Export symbol nand_decode_ext_id Date: Thu, 14 Jul 2022 09:51:25 +0200 Message-Id: <20220714075131.411548-5-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220714075131.411548-1-michael@amarulasolutions.com> References: <20220714075131.411548-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=rmdiUWnj; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , In preparation of moving specific nand support that are not jedec or onfi Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/nand_base.c | 3 ++- include/linux/mtd/rawnand.h | 3 +++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index be1a6738c1..fa9ffb56fd 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4152,7 +4152,7 @@ static int nand_get_bits_per_cell(u8 cellinfo) * chip. The rest of the parameters must be decoded according to generic or * manufacturer-specific "extended ID" decoding patterns. */ -static void nand_decode_ext_id(struct nand_chip *chip) +void nand_decode_ext_id(struct nand_chip *chip) { struct mtd_info *mtd = &chip->mtd; int extid, id_len; @@ -4278,6 +4278,7 @@ static void nand_decode_ext_id(struct nand_chip *chip) } } +EXPORT_SYMBOL_GPL(nand_decode_ext_id); /* * Manufacturer detection. Only used when the NAND is not ONFI or JEDEC diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index d8141cb4d1..8fb2a43296 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -1374,4 +1374,7 @@ int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len, int nand_write_data_op(struct nand_chip *chip, const void *buf, unsigned int len, bool force_8bit); +/* Default extended ID decoding function */ +void nand_decode_ext_id(struct nand_chip *chip); + #endif /* __LINUX_MTD_RAWNAND_H */ From patchwork Thu Jul 14 07:51:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Nazzareno Trimarchi X-Patchwork-Id: 2148 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ej1-f69.google.com (mail-ej1-f69.google.com [209.85.218.69]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id BCF263F013 for ; Thu, 14 Jul 2022 09:51:48 +0200 (CEST) Received: by mail-ej1-f69.google.com with SMTP id hq20-20020a1709073f1400b0072b9824f0a2sf427421ejc.23 for ; Thu, 14 Jul 2022 00:51:48 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1657785108; cv=pass; d=google.com; s=arc-20160816; b=NjGTCiK1aEJtJkzzNfUfZBDuEQBwHib2dtRiSgzUCDI5soMHiqWu/lMe/EsdIfDelW cGSX9wOo4Tm3x9liKXkj5nvjED3p6Pv50fl7kdk87ZA09pttqEss9C7cwkHADm6CVXRq YYln/z0Mlw7NNKxCqJ61xBgNz1Yf/Z4biLdEN6cSGw8M1TszpaW6KsAe6MzVsvK/3Gja inVRsW/oa/3mdgxVKGOMX8cCA270osByhc3wykHkD+qVf8Gzz8qntdcK256IaHuJ8Av8 L1zMSToO4RtDh+DAcxiBcEGDPiLW49VOIPbSlsnZrYlV8suKPgWwJzRpNqHfZVrddKRh I5hw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=lUURo71CXNNH6NgzYUdQa2jpyFQkVAn9mQhSeR/myjE=; b=XkFtxTTMMOxiGPZ1X1F0aw7cwiAaxWJxMOq/A/54/cZSRbpxg60wqSO5Exgg0GP7GY fIoBYlxL47b6W1Z6to9VsjhhpyAahVDqy0vFu9tSxN9L71+JslzAhvfFPHA5csG0Qa2R Xav136kr7AM/j1MFE3BHc6+cdemXO5w0u3j7E6hi0M2LAf5sUb+msCm0y7GV4Rgiy9H8 P/vYtPhmYF91/imDh952BSB+Zc/Gdrt0DjkBaXU0wH/gtBi23D5wtUcmP/XnFoUcQW7V 3PYNUcHAPfY26dGAoS08UXnh0cizlV3nHmeFA9woYMvCiGK0VszRJ4Q5ZEApomXgtlL8 XhVw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=qtjsbO2A; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :x-original-sender:x-original-authentication-results:precedence :mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=lUURo71CXNNH6NgzYUdQa2jpyFQkVAn9mQhSeR/myjE=; b=VatssiAjRGVNtIdo/NwyHQ262qNqUa9pxMz16XuXRtMY7hMkOryh8oNvboVQWb9mtJ cXsw8+V/ee8s0XR7StYxaf1VxMiZ/mhfdlbyYXk79+3NS915GUtZHA+ReCe5QueIGo/L UXQ/ikOAMkiQKaEWmVRlP3usG8HB/Y+aJqgBU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=lUURo71CXNNH6NgzYUdQa2jpyFQkVAn9mQhSeR/myjE=; b=gewCatEMJs0mhxb4h87yeDB0hANew+ZLWtzJP6EaIhtg2RQz/0NArABJBaEJKRkGWK QYaHxkYgeBUVt3Clxeh6ug6NCZP6hv0e0A1JfWYMGRbvexee/4ReKV1Qn6jH3d2nrafy /NvAsh7agvdqnCiDjiDn3VVJDRHWl3/aINPR19vmbEw8f3Qz8kq/M+QRgtcNXwToUc7Z pLe9LqEEMBUwjaj132PP4d8wiAjfRSBQnSfHKY8bnUKTV7myDz84kgAx6rt6r6Qu7AB3 6XGQ8BDLktw8YoHKFU/g1gSsjka5s1F4Fge0FXQx9qwGocCkhEM7LHoC5VVQSy0akbwB AgvQ== X-Gm-Message-State: AJIora8M4gN3edcJWiYcfoeXlAWQo6pvL9ut4EBuq/CEmkf29i6aSGgO 7H+9jJi2IxarznNmjhdO7zGJlfkc X-Google-Smtp-Source: AGRyM1te3Tq5Lkj9YMHDZptJTJElt9b2t72/haDZGpaQiMhfJyLot4C4uzolLns2lRerpBzc4t3azQ== X-Received: by 2002:a17:906:106:b0:722:e997:a365 with SMTP id 6-20020a170906010600b00722e997a365mr7543189eje.169.1657785108593; Thu, 14 Jul 2022 00:51:48 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:906:95c1:b0:6ff:45d:c05d with SMTP id n1-20020a17090695c100b006ff045dc05dls4167214ejy.5.gmail; Thu, 14 Jul 2022 00:51:47 -0700 (PDT) X-Received: by 2002:a17:907:97d3:b0:726:a5db:3a3a with SMTP id js19-20020a17090797d300b00726a5db3a3amr7720314ejc.654.1657785107241; Thu, 14 Jul 2022 00:51:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657785107; cv=none; d=google.com; s=arc-20160816; b=WAkvRoUvFL+WnTUH+4a0Scv+Cla2EPx20fbz4L3IV00sjN5ZdYFxkMtAIiSRsHas/+ erGptDNVQibefDWlVLemXF220VDLS7kKISUaNNkWjmJZXBEDNcKZg+4W5tS6SpxJRVUD gISg4RWVRxuM2jycGFlH7XNZVBkPXF+lDlEzpDx5QQLzD7cKkg8EOtZu7EWpgmGVOclM W0Fg0jhXDackFzTssyDf4XBKpD4cqKYzZdfVjE/YLprSXZZqCwiKVbcVn4BBuI/cWwTD fmhGwPGoGidU0xdaXcTSHYn2rbHOqa0bksr3QjeTjx+LjTeHwPdFhPYXig4/mOnYYMZi YjoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=FHlXD7ZEyDTlrhB050ZzDFGzqeIGjI258AB/tQepPiM=; b=lmdCVC/+CC7e5cfJOanRkAfUIQ3VfcM8niPgEzoFsqnQq0Nm190hFwJTJi4wrQ73Tl Vnqd0lxfThkvmi70qgg+aRCbp/bV6UncW88hLUCPeiVvCcp5wFWYXJ0/lD9rEep5aLKD UhRBNk62Ol5RhXbVffqGaDajUOBVl1viKiJKAmtH1ip4ceOfLhultTwU/QNe2Uz3Fx6D ngTdS0qk5Io/I+nW5jtHFGGFkKXW1zx0E4ih028e1IA7CrQl85aG5zDQayxTPJOxaeCj LRS/LzfWUrTDqwvuOkKoRgJ1ezvbtkQqTS+Nu/CUUze+CLeIz6cBLLt75Y3qy+l0HgzT fMlg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=qtjsbO2A; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id ga38-20020a1709070c2600b00722fce50938sor294831ejc.132.2022.07.14.00.51.47 for (Google Transport Security); Thu, 14 Jul 2022 00:51:47 -0700 (PDT) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:906:3f49:b0:722:e1d2:f857 with SMTP id f9-20020a1709063f4900b00722e1d2f857mr7425680ejj.15.1657785106474; Thu, 14 Jul 2022 00:51:46 -0700 (PDT) Received: from panicking.amarulasolutions.com ([2.198.242.86]) by smtp.gmail.com with ESMTPSA id r23-20020a170906a21700b0072b616ade26sm369252ejy.216.2022.07.14.00.51.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 00:51:45 -0700 (PDT) From: Michael Trimarchi To: linux-amarula@amarulasolutions.com, Dario Binacchi , Tommaso Merciai Subject: [PATCH 06/11] mtd: nand: Move Samsung specific init/detection logic in nand_samsung.c Date: Thu, 14 Jul 2022 09:51:26 +0200 Message-Id: <20220714075131.411548-6-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220714075131.411548-1-michael@amarulasolutions.com> References: <20220714075131.411548-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=qtjsbO2A; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Upstream commit c51d0ac59f24200dfdccc897ff7c3c9446c7599a Move Samsung specific initialization and detection logic into nand_samsung.c. This is part of the "separate vendor specific code from core" cleanup process. Signed-off-by: Boris Brezillon Acked-by: Richard Weinberger Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/Makefile | 3 +- drivers/mtd/nand/raw/nand_base.c | 50 +--------------- drivers/mtd/nand/raw/nand_ids.c | 4 +- drivers/mtd/nand/raw/nand_samsung.c | 90 +++++++++++++++++++++++++++++ include/linux/mtd/rawnand.h | 2 + 5 files changed, 99 insertions(+), 50 deletions(-) create mode 100644 drivers/mtd/nand/raw/nand_samsung.c diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 6ec3581d20..c023c3cb68 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -14,7 +14,7 @@ obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o obj-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o -obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o +obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_samsung.o obj-$(CONFIG_SPL_NAND_IDENT) += nand_ids.o nand_timings.o obj-$(CONFIG_SPL_NAND_INIT) += nand.o ifeq ($(CONFIG_SPL_ENV_SUPPORT),y) @@ -31,6 +31,7 @@ obj-y += nand_ids.o obj-y += nand_util.o obj-y += nand_ecc.o obj-y += nand_base.o +obj-y += nand_samsung.o obj-y += nand_timings.o endif # not spl diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index fa9ffb56fd..d4a91b5fcc 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4165,47 +4165,12 @@ void nand_decode_ext_id(struct nand_chip *chip) /* * Field definitions are in the following datasheets: * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32) - * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44) * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22) * * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung * ID to decide what to do. */ - if (id_len == 6 && chip->id.data[0] == NAND_MFR_SAMSUNG && - !nand_is_slc(chip) && chip->id.data[5] != 0x00) { - /* Calc pagesize */ - mtd->writesize = 2048 << (extid & 0x03); - extid >>= 2; - /* Calc oobsize */ - switch (((extid >> 2) & 0x04) | (extid & 0x03)) { - case 1: - mtd->oobsize = 128; - break; - case 2: - mtd->oobsize = 218; - break; - case 3: - mtd->oobsize = 400; - break; - case 4: - mtd->oobsize = 436; - break; - case 5: - mtd->oobsize = 512; - break; - case 6: - mtd->oobsize = 640; - break; - case 7: - default: /* Other cases are "reserved" (unknown) */ - mtd->oobsize = 1024; - break; - } - extid >>= 2; - /* Calc blocksize */ - mtd->erasesize = (128 * 1024) << - (((extid >> 1) & 0x04) | (extid & 0x03)); - } else if (id_len == 6 && chip->id.data[0] == NAND_MFR_HYNIX && + if (id_len == 6 && chip->id.data[0] == NAND_MFR_HYNIX && !nand_is_slc(chip)) { unsigned int tmp; @@ -4367,13 +4332,10 @@ static void nand_decode_bbm_options(struct mtd_info *mtd, * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba, * AMD/Spansion, and Macronix. All others scan only the first page. */ - if (!nand_is_slc(chip) && - (maf_id == NAND_MFR_SAMSUNG || - maf_id == NAND_MFR_HYNIX)) + if (!nand_is_slc(chip) && maf_id == NAND_MFR_HYNIX) chip->bbt_options |= NAND_BBT_SCANLASTPAGE; else if ((nand_is_slc(chip) && - (maf_id == NAND_MFR_SAMSUNG || - maf_id == NAND_MFR_HYNIX || + (maf_id == NAND_MFR_HYNIX || maf_id == NAND_MFR_TOSHIBA || maf_id == NAND_MFR_AMD || maf_id == NAND_MFR_MACRONIX)) || @@ -4542,12 +4504,6 @@ struct nand_flash_dev *nand_get_flash_type(struct nand_chip *chip, /* Get chip options */ chip->options |= type->options; - /* - * Check if chip is not a Samsung device. Do not clear the - * options for chips which do not have an extended id. - */ - if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize) - chip->options &= ~NAND_SAMSUNG_LP_OPTIONS; ident_done: if (chip->options & NAND_BUSWIDTH_AUTO) { diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c index 2a50f0b214..f4126c3a5a 100644 --- a/drivers/mtd/nand/raw/nand_ids.c +++ b/drivers/mtd/nand/raw/nand_ids.c @@ -10,7 +10,7 @@ #include #include -#define LP_OPTIONS NAND_SAMSUNG_LP_OPTIONS +#define LP_OPTIONS 0 #define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16) #define SP_OPTIONS NAND_NEED_READRDY @@ -189,7 +189,7 @@ struct nand_flash_dev nand_flash_ids[] = { /* Manufacturer IDs */ struct nand_manufacturers nand_manuf_ids[] = { {NAND_MFR_TOSHIBA, "Toshiba"}, - {NAND_MFR_SAMSUNG, "Samsung"}, + {NAND_MFR_SAMSUNG, "Samsung", &samsung_nand_manuf_ops}, {NAND_MFR_FUJITSU, "Fujitsu"}, {NAND_MFR_NATIONAL, "National"}, {NAND_MFR_RENESAS, "Renesas"}, diff --git a/drivers/mtd/nand/raw/nand_samsung.c b/drivers/mtd/nand/raw/nand_samsung.c new file mode 100644 index 0000000000..3dfbbec382 --- /dev/null +++ b/drivers/mtd/nand/raw/nand_samsung.c @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2017 Free Electrons + * Copyright (C) 2017 NextThing Co + * + * Author: Boris Brezillon + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +static void samsung_nand_decode_id(struct nand_chip *chip) +{ + struct mtd_info *mtd = nand_to_mtd(chip); + + /* New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44) */ + if (chip->id.len == 6 && !nand_is_slc(chip) && + chip->id.data[5] != 0x00) { + u8 extid = chip->id.data[3]; + + /* Get pagesize */ + mtd->writesize = 2048 << (extid & 0x03); + + extid >>= 2; + + /* Get oobsize */ + switch (((extid >> 2) & 0x4) | (extid & 0x3)) { + case 1: + mtd->oobsize = 128; + break; + case 2: + mtd->oobsize = 218; + break; + case 3: + mtd->oobsize = 400; + break; + case 4: + mtd->oobsize = 436; + break; + case 5: + mtd->oobsize = 512; + break; + case 6: + mtd->oobsize = 640; + break; + case 7: + default: /* Other cases are "reserved" (unknown) */ + WARN(1, "Invalid OOB size value"); + mtd->oobsize = 1024; + break; + } + + /* Get blocksize */ + extid >>= 2; + mtd->erasesize = (128 * 1024) << + (((extid >> 1) & 0x04) | (extid & 0x03)); + } else { + nand_decode_ext_id(chip); + } +} + +static int samsung_nand_init(struct nand_chip *chip) +{ + struct mtd_info *mtd = nand_to_mtd(chip); + + if (mtd->writesize > 512) + chip->options |= NAND_SAMSUNG_LP_OPTIONS; + + if (!nand_is_slc(chip)) + chip->bbt_options |= NAND_BBT_SCANLASTPAGE; + else + chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; + + return 0; +} + +const struct nand_manufacturer_ops samsung_nand_manuf_ops = { + .detect = samsung_nand_decode_id, + .init = samsung_nand_init, +}; diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 8fb2a43296..d0312e924b 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -1158,6 +1158,8 @@ struct nand_manufacturers { extern struct nand_flash_dev nand_flash_ids[]; extern struct nand_manufacturers nand_manuf_ids[]; +extern const struct nand_manufacturer_ops samsung_nand_manuf_ops; + int nand_default_bbt(struct mtd_info *mtd); int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs); From patchwork Thu Jul 14 07:51:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Nazzareno Trimarchi X-Patchwork-Id: 2149 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f72.google.com (mail-ed1-f72.google.com [209.85.208.72]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 781443F013 for ; Thu, 14 Jul 2022 09:51:51 +0200 (CEST) Received: by mail-ed1-f72.google.com with SMTP id j6-20020a05640211c600b0043a8ea2c138sf999231edw.2 for ; Thu, 14 Jul 2022 00:51:51 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1657785111; cv=pass; d=google.com; s=arc-20160816; b=ioCqYASU+ygY4+Om9cGXQsf8n/YgjUXQIQ6NPCHxTWRTknmBBQwwz+fPAQem6QIaH4 SGwpnBQFoZ2NplwXj6We3RPDYV5etRsOkLmHHVeej0asjpNK9DH9gnQ9DLx4v9tRB0Xh URTnBRxmphal8ertSIPlNp2QBWtpgHmRLJDxM996FWHA/6II4XXCglp9oZUeUKD2e6vx CfjldU+FERxAZNprWRNfGhk6DTOuqxo0dxbwRYUe6K7jlGuv0rc3p4vfHIxebsMdT6At Em1Z9KuwPFZytk4OyiMA6vdo8Bm1gnWlwL+BcrkTddGKOptr3elt2Utlsc8L/7Dvjaof 0A0w== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=fZgshh+DUSK+eyEbjlYQprwRuBP8CDXGWx7L5/ct9W8=; b=mn6s12cL4JZjqSws5hkIInLTYvRqOLlpg28Fp9dN7JayWfavKzaVtCxmYrvIwrqFyw bwdjLGC2uORIYgOeFzcLiF5JYCXj+SGaK2TezOiVift3kLkdyGfKqS1jm0SjIZgcwsGt 5SWo7Vgx+mNmvGabEvz/SxLrIP8HjcwEGebSQd2Usy8eb0MbU21i/rXHUOPXaqOrafEz LyL44DpjEjtnnab4FJszAbbuYM+J1xPG745vRoOc5enLeKjU4JguxtQsjRuwaKR1h8SG YmTFgluJb3Rgq378ApIUzMVVbGonOIjd8eX7ZluZ0Cqo26v7YFAXZQKB7zEpvkc0kgSV HqXw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=TExNNOyZ; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :x-original-sender:x-original-authentication-results:precedence :mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=fZgshh+DUSK+eyEbjlYQprwRuBP8CDXGWx7L5/ct9W8=; b=PLglZ+LgMKzzRJjhk5y53lfPeaDBXFFqCpglVVtxOcNdfeyMRSKbjjwNpP3Nzy6ku2 +65ShRJE8aen+E8zsgKEKIIWJ7swPvWfbvllvcxShczpgGNvw01efQbY6SilB2/rvSU/ DFsbNRWfxW1S05aHTr2ZiE2DUm5btMsDkoodY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=fZgshh+DUSK+eyEbjlYQprwRuBP8CDXGWx7L5/ct9W8=; b=HOR0TUO+Az4Sl7E5+9PevfKW+aihOfSL94CFnBLGnjmuYkPersC+z+az0JwmLM1VVI b2N3stb9L+wOCE53ppHvKSJZQjGMZOXOPa3MsKovzjlbXOlCwyIpILhxLrS4Ukj+8lv3 S7JUrLrOBQbCkr9FVxpjsWhoEeQCjHeIRMljmQ/UE1jyJ5h5cTpKyzld6kVgLRV4suNM fbHcpjyIjkMvJswQFnK8Fc3pUlPuIDcll+ZZm3IwG/xJx0+hcEiZ5wizTyjrt7Xdj4OE yJI4ZfQPKi4L8wAK2jMrhl0mewr61c//Z2otqOz9IL8hL4ZrNyPIHaty5aVscgR2a9Su kOAQ== X-Gm-Message-State: AJIora9frZCopNyEMqHiMV/0oVjjZIUvSDQp5Hf5I8aZvbQVgAFHoZv6 4rcngJ/Tr66ht6ixbt7qMS2YgeUA X-Google-Smtp-Source: AGRyM1taOISnM8vsClGaX7x65QTwOyqYkBRfwXTn8XAb33l/YLDPsPVPKNsDwKjw95xqOs3Yg8BHMw== X-Received: by 2002:a17:907:6ea4:b0:72b:8550:90db with SMTP id sh36-20020a1709076ea400b0072b855090dbmr7456157ejc.135.1657785111304; Thu, 14 Jul 2022 00:51:51 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a05:6402:35d5:b0:43a:7724:247e with SMTP id z21-20020a05640235d500b0043a7724247els186624edc.2.gmail; Thu, 14 Jul 2022 00:51:50 -0700 (PDT) X-Received: by 2002:a05:6402:48c:b0:43a:8bc7:f440 with SMTP id k12-20020a056402048c00b0043a8bc7f440mr10433665edv.8.1657785110052; Thu, 14 Jul 2022 00:51:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657785110; cv=none; d=google.com; s=arc-20160816; b=iuEPWnJPbmfHIPobwPyWlGIV/4eEH69it3zl1azsxfsw/Xia8ThCuM6fSScpL6vUF0 BlWh9QwmzG6UNImJY1csjN/3XK2dCwX/zyA1COneZuzB08VUh4lwoiKruY8XtXIbNMgc q2k/uVJ9cYi6TgRjcpUe7KvalTzss6ywEnvbehgCz8TpOOPdNlq9XeDNGaBgctsLTCsn SlI18CLwLkkcUHvhKB2JqrXkgdogvl2Jvsv9+v5amCWR/f7p1sjL/Y6hwy/NRZc1g+yk FoZqz5eSfVkxiFVQjfSeuC4YmBI2rTPlsjU5MECvF9AQvtPARiGDxEm7vwXtbBMARFAs MeRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=DBWdmXOBr2JiFEVxyfmGtxDTDvGsrk8azgxHk7v0c/s=; b=fT8VqS53WlSHRZbP/MlwPMRImAGaQFIyCyercohEFIHiCz/J+V6r5O6nFiO59w5yFN yVaVLm9jx5tL+HEh5PWQkQgnMI6nD8Ag+NZDE3RQbnm3KaIjbEtsSFu//hnds072VyQy gd1Lzaj3F8EQGSiDxSAEAo1hvPFBccfZ4pj/+Rv7+6ZjYbIbl6ae4oSI8vC8o7BwxyxW iz0x0UD/cNgj5v+4t7evwtKzEqwXKfp42Uh5Rg1cTfbqNOiIm3mRHBbgQevLoqlVeUVP u0B+1Yanx3uRA/Y9MFg43tAJ/049oiiA+Ed9h61p8aBupcywh5WGcLP/td6IuELgFvdn 9cjA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=TExNNOyZ; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id b15-20020a170906660f00b0072b4c50a9c0sor291249ejp.66.2022.07.14.00.51.50 for (Google Transport Security); Thu, 14 Jul 2022 00:51:50 -0700 (PDT) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:907:7395:b0:72b:86f2:4fd5 with SMTP id er21-20020a170907739500b0072b86f24fd5mr7800303ejc.332.1657785109353; Thu, 14 Jul 2022 00:51:49 -0700 (PDT) Received: from panicking.amarulasolutions.com ([2.198.242.86]) by smtp.gmail.com with ESMTPSA id r23-20020a170906a21700b0072b616ade26sm369252ejy.216.2022.07.14.00.51.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 00:51:48 -0700 (PDT) From: Michael Trimarchi To: linux-amarula@amarulasolutions.com, Dario Binacchi , Tommaso Merciai Subject: [PATCH 07/11] mtd: nand: Move Hynix specific init/detection logic in nand_hynix.c Date: Thu, 14 Jul 2022 09:51:27 +0200 Message-Id: <20220714075131.411548-7-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220714075131.411548-1-michael@amarulasolutions.com> References: <20220714075131.411548-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=TExNNOyZ; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Upstream commit 01389b6bd2f4f7649cdbb4a99a15d9e0c05d6f8c Move Hynix specific initialization and detection logic into nand_hynix.c. This is part of the "separate vendor specific code from core" cleanup process. Signed-off-by: Boris Brezillon Acked-by: Richard Weinberger Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/Makefile | 3 +- drivers/mtd/nand/raw/nand_base.c | 117 ++++++++---------------------- drivers/mtd/nand/raw/nand_hynix.c | 86 ++++++++++++++++++++++ drivers/mtd/nand/raw/nand_ids.c | 2 +- include/linux/mtd/rawnand.h | 1 + 5 files changed, 121 insertions(+), 88 deletions(-) create mode 100644 drivers/mtd/nand/raw/nand_hynix.c diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index c023c3cb68..d6ba111ab2 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -14,7 +14,7 @@ obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o obj-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o -obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_samsung.o +obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_hynix.o nand_samsung.o obj-$(CONFIG_SPL_NAND_IDENT) += nand_ids.o nand_timings.o obj-$(CONFIG_SPL_NAND_INIT) += nand.o ifeq ($(CONFIG_SPL_ENV_SUPPORT),y) @@ -31,6 +31,7 @@ obj-y += nand_ids.o obj-y += nand_util.o obj-y += nand_ecc.o obj-y += nand_base.o +obj-y += nand_hynix.o obj-y += nand_samsung.o obj-y += nand_timings.o diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index d4a91b5fcc..da22cf6e79 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4162,85 +4162,34 @@ void nand_decode_ext_id(struct nand_chip *chip) extid = chip->id.data[3]; id_len = chip->id.len; + /* Calc pagesize */ + mtd->writesize = 1024 << (extid & 0x03); + extid >>= 2; + /* Calc oobsize */ + mtd->oobsize = (8 << (extid & 0x01)) * + (mtd->writesize >> 9); + extid >>= 2; + /* Calc blocksize. Blocksize is multiples of 64KiB */ + mtd->erasesize = (64 * 1024) << (extid & 0x03); + extid >>= 2; + /* Get buswidth information */ + /* Get buswidth information */ + if (extid & 0x1) + chip->options |= NAND_BUSWIDTH_16; + /* - * Field definitions are in the following datasheets: - * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32) - * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22) - * - * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung - * ID to decide what to do. + * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per + * 512B page. For Toshiba SLC, we decode the 5th/6th byte as + * follows: + * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm, + * 110b -> 24nm + * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC */ - if (id_len == 6 && chip->id.data[0] == NAND_MFR_HYNIX && - !nand_is_slc(chip)) { - unsigned int tmp; - - /* Calc pagesize */ - mtd->writesize = 2048 << (extid & 0x03); - extid >>= 2; - /* Calc oobsize */ - switch (((extid >> 2) & 0x04) | (extid & 0x03)) { - case 0: - mtd->oobsize = 128; - break; - case 1: - mtd->oobsize = 224; - break; - case 2: - mtd->oobsize = 448; - break; - case 3: - mtd->oobsize = 64; - break; - case 4: - mtd->oobsize = 32; - break; - case 5: - mtd->oobsize = 16; - break; - default: - mtd->oobsize = 640; - break; - } - extid >>= 2; - /* Calc blocksize */ - tmp = ((extid >> 1) & 0x04) | (extid & 0x03); - if (tmp < 0x03) - mtd->erasesize = (128 * 1024) << tmp; - else if (tmp == 0x03) - mtd->erasesize = 768 * 1024; - else - mtd->erasesize = (64 * 1024) << tmp; - } else { - /* Calc pagesize */ - mtd->writesize = 1024 << (extid & 0x03); - extid >>= 2; - /* Calc oobsize */ - mtd->oobsize = (8 << (extid & 0x01)) * - (mtd->writesize >> 9); - extid >>= 2; - /* Calc blocksize. Blocksize is multiples of 64KiB */ - mtd->erasesize = (64 * 1024) << (extid & 0x03); - extid >>= 2; - /* Get buswidth information */ - /* Get buswidth information */ - if (extid & 0x1) - chip->options |= NAND_BUSWIDTH_16; - - /* - * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per - * 512B page. For Toshiba SLC, we decode the 5th/6th byte as - * follows: - * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm, - * 110b -> 24nm - * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC - */ - if (id_len >= 6 && chip->id.data[0] == NAND_MFR_TOSHIBA && - nand_is_slc(chip) && - (chip->id.data[5] & 0x7) == 0x6 /* 24nm */ && - !(chip->id.data[4] & 0x80) /* !BENAND */) { - mtd->oobsize = 32 * mtd->writesize >> 9; - } - + if (id_len >= 6 && chip->id.data[0] == NAND_MFR_TOSHIBA && + nand_is_slc(chip) && + (chip->id.data[5] & 0x7) == 0x6 /* 24nm */ && + !(chip->id.data[4] & 0x80) /* !BENAND */) { + mtd->oobsize = 32 * mtd->writesize >> 9; } } EXPORT_SYMBOL_GPL(nand_decode_ext_id); @@ -4332,15 +4281,11 @@ static void nand_decode_bbm_options(struct mtd_info *mtd, * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba, * AMD/Spansion, and Macronix. All others scan only the first page. */ - if (!nand_is_slc(chip) && maf_id == NAND_MFR_HYNIX) - chip->bbt_options |= NAND_BBT_SCANLASTPAGE; - else if ((nand_is_slc(chip) && - (maf_id == NAND_MFR_HYNIX || - maf_id == NAND_MFR_TOSHIBA || - maf_id == NAND_MFR_AMD || - maf_id == NAND_MFR_MACRONIX)) || - (mtd->writesize == 2048 && - maf_id == NAND_MFR_MICRON)) + if ((nand_is_slc(chip) && + (maf_id == NAND_MFR_TOSHIBA || + maf_id == NAND_MFR_AMD || + maf_id == NAND_MFR_MACRONIX)) || + (mtd->writesize == 2048 && maf_id == NAND_MFR_MICRON)) chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; } diff --git a/drivers/mtd/nand/raw/nand_hynix.c b/drivers/mtd/nand/raw/nand_hynix.c new file mode 100644 index 0000000000..a5b6a61507 --- /dev/null +++ b/drivers/mtd/nand/raw/nand_hynix.c @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2017 Free Electrons + * Copyright (C) 2017 NextThing Co + * + * Author: Boris Brezillon + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +static void hynix_nand_decode_id(struct nand_chip *chip) +{ + struct mtd_info *mtd = nand_to_mtd(chip); + + /* Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22) */ + if (chip->id.len == 6 && !nand_is_slc(chip)) { + u8 tmp, extid = chip->id.data[3]; + + /* Extract pagesize */ + mtd->writesize = 2048 << (extid & 0x03); + extid >>= 2; + + /* Extract oobsize */ + switch (((extid >> 2) & 0x4) | (extid & 0x3)) { + case 0: + mtd->oobsize = 128; + break; + case 1: + mtd->oobsize = 224; + break; + case 2: + mtd->oobsize = 448; + break; + case 3: + mtd->oobsize = 64; + break; + case 4: + mtd->oobsize = 32; + break; + case 5: + mtd->oobsize = 16; + break; + default: + mtd->oobsize = 640; + break; + } + + /* Extract blocksize */ + extid >>= 2; + tmp = ((extid >> 1) & 0x04) | (extid & 0x03); + if (tmp < 0x03) + mtd->erasesize = (128 * 1024) << tmp; + else if (tmp == 0x03) + mtd->erasesize = 768 * 1024; + else + mtd->erasesize = (64 * 1024) << tmp; + } else { + nand_decode_ext_id(chip); + } +} + +static int hynix_nand_init(struct nand_chip *chip) +{ + if (!nand_is_slc(chip)) + chip->bbt_options |= NAND_BBT_SCANLASTPAGE; + else + chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; + + return 0; +} + +const struct nand_manufacturer_ops hynix_nand_manuf_ops = { + .detect = hynix_nand_decode_id, + .init = hynix_nand_init, +}; diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c index f4126c3a5a..ec263a4327 100644 --- a/drivers/mtd/nand/raw/nand_ids.c +++ b/drivers/mtd/nand/raw/nand_ids.c @@ -194,7 +194,7 @@ struct nand_manufacturers nand_manuf_ids[] = { {NAND_MFR_NATIONAL, "National"}, {NAND_MFR_RENESAS, "Renesas"}, {NAND_MFR_STMICRO, "ST Micro"}, - {NAND_MFR_HYNIX, "Hynix"}, + {NAND_MFR_HYNIX, "Hynix", &hynix_nand_manuf_ops}, {NAND_MFR_MICRON, "Micron"}, {NAND_MFR_AMD, "AMD/Spansion"}, {NAND_MFR_MACRONIX, "Macronix"}, diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index d0312e924b..d35277d187 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -1159,6 +1159,7 @@ extern struct nand_flash_dev nand_flash_ids[]; extern struct nand_manufacturers nand_manuf_ids[]; extern const struct nand_manufacturer_ops samsung_nand_manuf_ops; +extern const struct nand_manufacturer_ops hynix_nand_manuf_ops; int nand_default_bbt(struct mtd_info *mtd); int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); From patchwork Thu Jul 14 07:51:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Nazzareno Trimarchi X-Patchwork-Id: 2150 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f72.google.com (mail-ed1-f72.google.com [209.85.208.72]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 79BC33F013 for ; Thu, 14 Jul 2022 09:51:53 +0200 (CEST) Received: by mail-ed1-f72.google.com with SMTP id m13-20020a056402430d00b0043ac2f27d83sf984501edc.20 for ; Thu, 14 Jul 2022 00:51:53 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1657785113; cv=pass; d=google.com; s=arc-20160816; b=y4Q0dkcvUsfZBtGhpUq7HXiGiGY4hIV9UMo+IiKHe0olb5O0ISX7BOppLZBaEUKM93 K3+s9SF7/HobBW2slGDUdmx6DrpWunzA9Nx869sDAuhLP2b4h1eGKbYuZ3UMvEZtSz6G oYUXEhvBVmu3JUUBA04sCMRXR/ylboqntjod5XZurVK8uBifTsnCVrFCvhDiQePhLDPN uc09KuCO01FFUNU6cExSTXDtnoqfOR5YIsq7jiFWzm02ozvwnOI7NMqHXjfUrx3odKZa Hf7RpT6TkCnbcU26xmaMJp5U9DZyU7a8EBfLOub7zy+08ZuZoviYiE1HoZfW74reQ8bA GN1A== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=5UlBYJvcxSJd72uwza9H7OPBTUq37ecz8UQhkVW70Uc=; b=f4+TwmtPBTVCtHN5STl7atKGEsCIzBEH86Iawc0OdGF7VRJbxGhl96EXvvHeZjp891 CwNqo+hitovu19UHtRJqJZp5OQKfjU+Y0dG3wmwcB9/RQ0sc+K22a+CfOQgRlZb2RIQE ZqMZxtH79Eysg3dWNK4IHqLq4QOA6wfVDKCAQ0lcAOMLdf7hbxhqmpVy6Pag1nOcYDSO xMs5+y7B9rPYWwtZhJN7ufFI1JfrLuyLCApbf3/Co/dMojivC//Hent4vIz2LIA0F9Yg yKkwtKvXZMa3MZc4lX7m/n4XGp9Q0Ei7jcK0gSl2IrZQ57z19FZK1SsmhYIXk7DnIqK6 5MGw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=L+lk2DHl; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :x-original-sender:x-original-authentication-results:precedence :mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=5UlBYJvcxSJd72uwza9H7OPBTUq37ecz8UQhkVW70Uc=; b=izd9GYYv00TlMWD5QZUrkJbAOFcH9tXKkBy0o6rsXfayb6uzGETdr1Rw8oZ7e1xZHj RLUXOgJM4pTEhzBYJ7JLZM1DFw4fsvVS8WsXEeIIEbfPgBtqzej7dKtHAzSI8Sx7WTtL TgQYqsDmKlFF+WrfcDG4WqYA7XIZ4Fey8FqrM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=5UlBYJvcxSJd72uwza9H7OPBTUq37ecz8UQhkVW70Uc=; b=GbuBoyfa4Uh3CurlAbx0EWtLreoxrPjh3/Qs/u1r0Fj45+PgCY1kH/K/iJ/0LY8Isd Q7sdAWjEGvBTc5Q00iBkm7stgjL1typZGBwvoHxJmgq5+ieLPIGYHWVHj8eP7CQ0usCP sdk0//9ECcVMDW1WwlShJnabRlMAavOfsSG4DlHlIdR/4KguUT1Sq8s+wqS+8/KOo8zI yljLuACAq7aAqXA1cyUblQNsNU7wyotH0d20ZtI1sPmIxLqvDlr+VmrVw+80nfuWDWfF SejpPhIYwj557xoCqtcscMGIYIs+AXwaSDnDZvXHrkkcUpxpAh4dhSm6sGiTlB/EEdFW BZKg== X-Gm-Message-State: AJIora+1wtIybTjlEsgPNfyIkNL2xvQ3YcNbEb5EoESwv5vZp6+acOqz V4/rhTpvUJuST2eenXNTd25saXtp X-Google-Smtp-Source: AGRyM1vqJHUp/dcXUIq5UtxGXA+KiOwo4dd9vf8NTWk0QyRHJyB0uXWYQl3jyvTcbBMUjJYB1e40Eg== X-Received: by 2002:a17:907:160a:b0:72b:51e0:d90b with SMTP id hb10-20020a170907160a00b0072b51e0d90bmr7146849ejc.609.1657785113332; Thu, 14 Jul 2022 00:51:53 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:906:95c1:b0:6ff:45d:c05d with SMTP id n1-20020a17090695c100b006ff045dc05dls4167332ejy.5.gmail; Thu, 14 Jul 2022 00:51:52 -0700 (PDT) X-Received: by 2002:a17:907:6287:b0:6e1:6ac:c769 with SMTP id nd7-20020a170907628700b006e106acc769mr7646609ejc.388.1657785112045; Thu, 14 Jul 2022 00:51:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657785112; cv=none; d=google.com; s=arc-20160816; b=CN1vSa7Y3HJbaZKaSs1UgVBm84jLshppmCVfzlXk51Gjjqdk55hQs4kB1yS7OlrWm5 hz/jkRb6VAq/nB6woZfj4NyHNR4dDG+7uKPTidZgRcabNNxn/pPjBWm/be6AfiG3Ozf7 cqhGO5ImiVLVp6Eu3pKmdt762+H+rzBx6VjBdb4OFzKrELeSsZbUEfdNHQ2miIybC50o 88QfDofum/F6CEuD+njc8JsUmZm4bZaNDugKEd9CHgkO9f4ulnOR+nwYypYBhoaijcxn ojagpWS9lT/YCYEPxHYQ+J24IC7vYMCl174pDCFOfDv7ez2ff07SD6P5RORV+pr/YXrV XfIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=7WJQ34WHiB9ZcLkc6WULNrMmO5gkck6lDeSVwV+13/E=; b=opxhq/Z50je313vMPyL9nZw47+6VEeV4TO2gBwkhVuT+I2WCBRdJUF8t7zbfa/d4Fd /WAtLkOxD+NNUGqYFkglTyc7x98XkUgjwIPrwegF3F1x5xAMogtAEQ9NW3VxwGgb9vYM JtE8Rff0o23ShYHJY7QfGDt77vHxJWMaRdSylV13zjFzGJjl8eu0Nzu9eJviCiGkFvaX IKc7O/uG56K5zAsCb606yk/AlIhgmloqnGPw6kMs7V9XEuwHxNDFa7CX1j7ZUvUd1JBY k8oTmfW099RxFhEI/AjCF+Jj1GFioGTRulmP6JWRLnng6aZeD0l3zelGAgNbSx93Y371 MpuA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=L+lk2DHl; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id a12-20020a50858c000000b00437bf0baa39sor445872edh.27.2022.07.14.00.51.52 for (Google Transport Security); Thu, 14 Jul 2022 00:51:52 -0700 (PDT) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a05:6402:35cf:b0:43a:d139:ea2b with SMTP id z15-20020a05640235cf00b0043ad139ea2bmr10455468edc.415.1657785111326; Thu, 14 Jul 2022 00:51:51 -0700 (PDT) Received: from panicking.amarulasolutions.com ([2.198.242.86]) by smtp.gmail.com with ESMTPSA id r23-20020a170906a21700b0072b616ade26sm369252ejy.216.2022.07.14.00.51.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 00:51:50 -0700 (PDT) From: Michael Trimarchi To: linux-amarula@amarulasolutions.com, Dario Binacchi , Tommaso Merciai Subject: [PATCH 08/11] mtd: nand: Move Toshiba specific init/detection logic in nand_toshiba.c Date: Thu, 14 Jul 2022 09:51:28 +0200 Message-Id: <20220714075131.411548-8-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220714075131.411548-1-michael@amarulasolutions.com> References: <20220714075131.411548-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=L+lk2DHl; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Upstream commit 9b2d61f80b060ce3ea5af2a99e148b0b214932b2 Move Toshiba specific initialization and detection logic into nand_toshiba.c. This is part of the "separate vendor specific code from core" cleanup process. Signed-off-by: Boris Brezillon Acked-by: Richard Weinberger Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/Makefile | 3 +- drivers/mtd/nand/raw/nand_base.c | 21 ++---------- drivers/mtd/nand/raw/nand_ids.c | 2 +- drivers/mtd/nand/raw/nand_toshiba.c | 53 +++++++++++++++++++++++++++++ include/linux/mtd/rawnand.h | 1 + 5 files changed, 59 insertions(+), 21 deletions(-) create mode 100644 drivers/mtd/nand/raw/nand_toshiba.c diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index d6ba111ab2..2eb08c1a9f 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -14,7 +14,7 @@ obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o obj-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o -obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_hynix.o nand_samsung.o +obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_hynix.o nand_samsung.o nand_toshiba.o obj-$(CONFIG_SPL_NAND_IDENT) += nand_ids.o nand_timings.o obj-$(CONFIG_SPL_NAND_INIT) += nand.o ifeq ($(CONFIG_SPL_ENV_SUPPORT),y) @@ -33,6 +33,7 @@ obj-y += nand_ecc.o obj-y += nand_base.o obj-y += nand_hynix.o obj-y += nand_samsung.o +obj-y += nand_toshiba.o obj-y += nand_timings.o endif # not spl diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index da22cf6e79..c5a5c22b12 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4155,12 +4155,11 @@ static int nand_get_bits_per_cell(u8 cellinfo) void nand_decode_ext_id(struct nand_chip *chip) { struct mtd_info *mtd = &chip->mtd; - int extid, id_len; + int extid; /* The 3rd id byte holds MLC / multichip data */ chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]); /* The 4th id byte is the important one */ extid = chip->id.data[3]; - id_len = chip->id.len; /* Calc pagesize */ mtd->writesize = 1024 << (extid & 0x03); @@ -4176,21 +4175,6 @@ void nand_decode_ext_id(struct nand_chip *chip) /* Get buswidth information */ if (extid & 0x1) chip->options |= NAND_BUSWIDTH_16; - - /* - * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per - * 512B page. For Toshiba SLC, we decode the 5th/6th byte as - * follows: - * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm, - * 110b -> 24nm - * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC - */ - if (id_len >= 6 && chip->id.data[0] == NAND_MFR_TOSHIBA && - nand_is_slc(chip) && - (chip->id.data[5] & 0x7) == 0x6 /* 24nm */ && - !(chip->id.data[4] & 0x80) /* !BENAND */) { - mtd->oobsize = 32 * mtd->writesize >> 9; - } } EXPORT_SYMBOL_GPL(nand_decode_ext_id); @@ -4282,8 +4266,7 @@ static void nand_decode_bbm_options(struct mtd_info *mtd, * AMD/Spansion, and Macronix. All others scan only the first page. */ if ((nand_is_slc(chip) && - (maf_id == NAND_MFR_TOSHIBA || - maf_id == NAND_MFR_AMD || + (maf_id == NAND_MFR_AMD || maf_id == NAND_MFR_MACRONIX)) || (mtd->writesize == 2048 && maf_id == NAND_MFR_MICRON)) chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c index ec263a4327..509652c8e2 100644 --- a/drivers/mtd/nand/raw/nand_ids.c +++ b/drivers/mtd/nand/raw/nand_ids.c @@ -188,7 +188,7 @@ struct nand_flash_dev nand_flash_ids[] = { /* Manufacturer IDs */ struct nand_manufacturers nand_manuf_ids[] = { - {NAND_MFR_TOSHIBA, "Toshiba"}, + {NAND_MFR_TOSHIBA, "Toshiba", &toshiba_nand_manuf_ops}, {NAND_MFR_SAMSUNG, "Samsung", &samsung_nand_manuf_ops}, {NAND_MFR_FUJITSU, "Fujitsu"}, {NAND_MFR_NATIONAL, "National"}, diff --git a/drivers/mtd/nand/raw/nand_toshiba.c b/drivers/mtd/nand/raw/nand_toshiba.c new file mode 100644 index 0000000000..1ac80df651 --- /dev/null +++ b/drivers/mtd/nand/raw/nand_toshiba.c @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2017 Free Electrons + * Copyright (C) 2017 NextThing Co + * + * Author: Boris Brezillon + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +static void toshiba_nand_decode_id(struct nand_chip *chip) +{ + struct mtd_info *mtd = nand_to_mtd(chip); + + nand_decode_ext_id(chip); + + /* + * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per + * 512B page. For Toshiba SLC, we decode the 5th/6th byte as + * follows: + * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm, + * 110b -> 24nm + * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC + */ + if (chip->id.len >= 6 && nand_is_slc(chip) && + (chip->id.data[5] & 0x7) == 0x6 /* 24nm */ && + !(chip->id.data[4] & 0x80) /* !BENAND */) + mtd->oobsize = 32 * mtd->writesize >> 9; +} + +static int toshiba_nand_init(struct nand_chip *chip) +{ + if (nand_is_slc(chip)) + chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; + + return 0; +} + +const struct nand_manufacturer_ops toshiba_nand_manuf_ops = { + .detect = toshiba_nand_decode_id, + .init = toshiba_nand_init, +}; diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index d35277d187..73abb34016 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -1158,6 +1158,7 @@ struct nand_manufacturers { extern struct nand_flash_dev nand_flash_ids[]; extern struct nand_manufacturers nand_manuf_ids[]; +extern const struct nand_manufacturer_ops toshiba_nand_manuf_ops; extern const struct nand_manufacturer_ops samsung_nand_manuf_ops; extern const struct nand_manufacturer_ops hynix_nand_manuf_ops; From patchwork Thu Jul 14 07:51:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Nazzareno Trimarchi X-Patchwork-Id: 2151 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f72.google.com (mail-ed1-f72.google.com [209.85.208.72]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 1BCA23F013 for ; Thu, 14 Jul 2022 09:51:56 +0200 (CEST) Received: by mail-ed1-f72.google.com with SMTP id j6-20020a05640211c600b0043a8ea2c138sf999333edw.2 for ; Thu, 14 Jul 2022 00:51:56 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1657785116; cv=pass; d=google.com; s=arc-20160816; b=UZ+ESl/QP5BPCAJemXQIfLHzhbnh82AWj4tsaVmgLe7GspBydxpbHZasvi2+slLqi9 dkH+fbrRwQes11F00qURnule95hgBNhK3dYklkAKnQSvu0gGEWyIdrupGzi6MbdC6+3+ Zf9MsZnHzoqvcIMKbPM4A2Bhhwzm3d162ndFyBYhfzxOCTsvxTK6SHNKDOCzAEXiLaCf 8wOg3hpUW7NtMQ85LInDQ57k2vofhdV14LC4wkDBGZ3bUJcMwhtaJ/3SbUsItFi3ZojC Vb25xrdhbMcptsQWnYcjMnhC/hcJ1IFM1v3wRzsZuDWm6Q5+p05LY9OdZFeSStTsvzc/ g1lw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=OgVPachqagnBDNSeX/3jXDGME1qhlZYNNy6w6lGKdJY=; b=di7QzMH6+wDRr91m1MKPZlyjJ1GZAs3MvG/rl8sWuqEygE1XBeom7HTPmEn0nGIGKM pISfffvdDZKPx38sHYdhqybMjhAkdbKhQVBcIXCLx2hYCJhUrBlomkTZztYZRztqnDbF S48IHtVbCkogxA1Rn0Rx5TGmBpR8I6BGyTTUM1ricwI1lUP4qZv5RZghIAxXduep27n/ b9KZQ5ZmSLNg84qzehh9ZL9Tt2gG0PxPtUTAmmVk1r6qof+PXKyFbhLVaG2tkJPZaOQ8 dFgYHtiUyLY+zsUcj1XfmaYR/XSU4W7eY1r90BEjkJKSqNBv7MsbelRzz7S+tbO9Tir6 GpWg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=XVqM+ySH; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :x-original-sender:x-original-authentication-results:precedence :mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=OgVPachqagnBDNSeX/3jXDGME1qhlZYNNy6w6lGKdJY=; b=Pt0ept9WmwnI1aZCGivO80PhGlrRr2xlRw3N/tMCvRd47lXAF0GhCWy1coQqzi3gom u0/S+huko1XzBqbrpxpYihCqmCqJs42kAh9LOWANEPQH+i2LdS3PtJUOwSBLGXwmSzvV nYuELcz4iY+OX24he7HU+XDBoJHgnUGV+ShuU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=OgVPachqagnBDNSeX/3jXDGME1qhlZYNNy6w6lGKdJY=; b=heiY/kQ7+SqvdkacfbtcPYocCoQ9GS5PIwI5zzmCj9nodVX+fvQ0k1nDjX+Ojn1saa RA7kOytzp9SDtT+tc9B/Bi2LL5HUwxCO/wAt/qAIv600WYF3+9gROyp2GYLDhwvBoo3T C4s/YXMwDmFIuz4DrIF9QCCYZIWSWGbAFrfoGU3klqIKMjEcFypgz+FB9GCGR+OSvC+Q UuN6hZBQ+YdRoWISzEyzxH+Ujtb3QyPZLHiPBuJZRJL1CwohzUwCEO/8eB7MspaIXeEo vVNRZkD/x5p9c9B0FNQIaxlP2gyRp3Qnrlm2Dawv4FbtMblUJZFAkC5MeEBC+ucgDxWc SDnw== X-Gm-Message-State: AJIora89ZC1A711Gz+qEPiILrKo2ifMgbz9h0qrRpCp+DCicAIP05Y/L fKQZD9vpoklVQpHZel3ra/StEhk0 X-Google-Smtp-Source: AGRyM1sKk8WY+T5M/viZ7thRxlSGfP6/wIQfJ+NzzywrqhuhtzNTKxcXdkN+jlZk+7KIaeTjm/Oq9A== X-Received: by 2002:a17:907:2e01:b0:72b:764f:ea1a with SMTP id ig1-20020a1709072e0100b0072b764fea1amr7420009ejc.666.1657785115982; Thu, 14 Jul 2022 00:51:55 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:906:5ac1:b0:6ff:ab8:e8f with SMTP id x1-20020a1709065ac100b006ff0ab80e8fls4167354ejs.6.gmail; Thu, 14 Jul 2022 00:51:54 -0700 (PDT) X-Received: by 2002:a17:907:720e:b0:72b:9cfe:21da with SMTP id dr14-20020a170907720e00b0072b9cfe21damr6510344ejc.575.1657785114601; Thu, 14 Jul 2022 00:51:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657785114; cv=none; d=google.com; s=arc-20160816; b=ud5thh9kMsF88GnpB0z8E4XcHGmJQofnZdw4gzZhyVbHdWjmR3oF9JDe7sUkrQhw2V 3w1t4gILsCTgFa2OXF/XyDkSNHC1nNLmB2XYpHew8gD+RfE7j7M7aLCeS8EO0MAsdcsy qm8iL6QfFjsHPWJhGedC5887BtFChl0VxwpI7sttbJQOEFpu1kS5vPKEwtQkXD1mEyRB jC7ojqF0Xkv36s42WygvvkaVpEqjWhstEydScI7a8TI/To+Im6xsVwk/+uMJh389zTas LPGnaVk7+NpyQVxGX1/dOTaLWmWdgUPidGxAAowuKkHMYbFCmq4I9l9ZeUxe/Rcbgr/2 zs8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=xTWhGhVKd/y2r3mBKI9X4AM5rGu1tPmetWYUpZZyazw=; b=ufW7gXcZbRGvWKn3Uag3nKKmymtrIzmPwM3iJTZ/J0UztaffFsbS/ZrjB1rj8gPCbM a1yrCEeGkcY8zTntcaIsxeRaD/uSV1EQpbcnn9Hs36BR/nexwvn/eSzuoaUkG8VDNDOZ 2KwqXiYeUaTXhciGWpE0jnnFVtTLO+SyqEaEtM5pVKISkDZWGW8JPyi7Fa59HAuIO1EL LpQNCZX6Z5AZH2ZLfUypCAnWhgmow2hkUXECvUXX2otfitoDeRo8G+l/SHI/kJBiu3A4 b6CCn8zGOmTPQz8Yl0Ahc46wY8F3UtM5vxZ/1lqyypxVP+CEpfuGtHTW52KWlB5FOcTa w2Qg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=XVqM+ySH; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id y89-20020a50bb62000000b0043b0e7d0ba4sor440357ede.5.2022.07.14.00.51.54 for (Google Transport Security); Thu, 14 Jul 2022 00:51:54 -0700 (PDT) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a50:fd08:0:b0:43a:7890:9c54 with SMTP id i8-20020a50fd08000000b0043a78909c54mr10503073eds.52.1657785113943; Thu, 14 Jul 2022 00:51:53 -0700 (PDT) Received: from panicking.amarulasolutions.com ([2.198.242.86]) by smtp.gmail.com with ESMTPSA id r23-20020a170906a21700b0072b616ade26sm369252ejy.216.2022.07.14.00.51.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 00:51:53 -0700 (PDT) From: Michael Trimarchi To: linux-amarula@amarulasolutions.com, Dario Binacchi , Tommaso Merciai Subject: [PATCH 09/11] mtd: nand: Move Micron specific init logic in nand_micron.c Date: Thu, 14 Jul 2022 09:51:29 +0200 Message-Id: <20220714075131.411548-9-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220714075131.411548-1-michael@amarulasolutions.com> References: <20220714075131.411548-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=XVqM+ySH; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Upstream commit 10d4e75c36f6c16311dde1461f318210da357219 Move Micron specific initialization logic into nand_micron.c. This is part of the "separate vendor specific code from core" cleanup process. Signed-off-by: Boris Brezillon Acked-by: Richard Weinberger Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/Makefile | 3 +- drivers/mtd/nand/raw/nand_base.c | 33 +---------- drivers/mtd/nand/raw/nand_ids.c | 2 +- drivers/mtd/nand/raw/nand_micron.c | 88 ++++++++++++++++++++++++++++++ include/linux/mtd/rawnand.h | 21 +------ 5 files changed, 94 insertions(+), 53 deletions(-) create mode 100644 drivers/mtd/nand/raw/nand_micron.c diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 2eb08c1a9f..bb20a04616 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -14,7 +14,7 @@ obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o obj-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o -obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_hynix.o nand_samsung.o nand_toshiba.o +obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_hynix.o nand_micron.o nand_samsung.o nand_toshiba.o obj-$(CONFIG_SPL_NAND_IDENT) += nand_ids.o nand_timings.o obj-$(CONFIG_SPL_NAND_INIT) += nand.o ifeq ($(CONFIG_SPL_ENV_SUPPORT),y) @@ -32,6 +32,7 @@ obj-y += nand_util.o obj-y += nand_ecc.o obj-y += nand_base.o obj-y += nand_hynix.o +obj-y += nand_micron.o obj-y += nand_samsung.o obj-y += nand_toshiba.o obj-y += nand_timings.o diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index c5a5c22b12..9024948ded 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -3863,30 +3863,6 @@ ext_out: return ret; } -static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode}; - - return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY, - feature); -} - -/* - * Configure chip properties from Micron vendor-specific ONFI table - */ -static void nand_onfi_detect_micron(struct nand_chip *chip, - struct nand_onfi_params *p) -{ - struct nand_onfi_vendor_micron *micron = (void *)p->vendor; - - if (le16_to_cpu(p->vendor_revision) < 1) - return; - - chip->read_retries = micron->read_retry_options; - chip->setup_read_retry = nand_setup_read_retry_micron; -} - /* * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise. */ @@ -3986,9 +3962,6 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip) pr_warn("Could not retrieve ONFI ECC requirements\n"); } - if (p->jedec_id == NAND_MFR_MICRON) - nand_onfi_detect_micron(chip, p); - return 1; } #else @@ -4265,10 +4238,8 @@ static void nand_decode_bbm_options(struct mtd_info *mtd, * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba, * AMD/Spansion, and Macronix. All others scan only the first page. */ - if ((nand_is_slc(chip) && - (maf_id == NAND_MFR_AMD || - maf_id == NAND_MFR_MACRONIX)) || - (mtd->writesize == 2048 && maf_id == NAND_MFR_MICRON)) + if (nand_is_slc(chip) && + (maf_id == NAND_MFR_AMD || maf_id == NAND_MFR_MACRONIX)) chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; } diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c index 509652c8e2..bb5ac8337f 100644 --- a/drivers/mtd/nand/raw/nand_ids.c +++ b/drivers/mtd/nand/raw/nand_ids.c @@ -195,7 +195,7 @@ struct nand_manufacturers nand_manuf_ids[] = { {NAND_MFR_RENESAS, "Renesas"}, {NAND_MFR_STMICRO, "ST Micro"}, {NAND_MFR_HYNIX, "Hynix", &hynix_nand_manuf_ops}, - {NAND_MFR_MICRON, "Micron"}, + {NAND_MFR_MICRON, "Micron", µn_nand_manuf_ops}, {NAND_MFR_AMD, "AMD/Spansion"}, {NAND_MFR_MACRONIX, "Macronix"}, {NAND_MFR_EON, "Eon"}, diff --git a/drivers/mtd/nand/raw/nand_micron.c b/drivers/mtd/nand/raw/nand_micron.c new file mode 100644 index 0000000000..a99bf8bbec --- /dev/null +++ b/drivers/mtd/nand/raw/nand_micron.c @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2017 Free Electrons + * Copyright (C) 2017 NextThing Co + * + * Author: Boris Brezillon + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +struct nand_onfi_vendor_micron { + u8 two_plane_read; + u8 read_cache; + u8 read_unique_id; + u8 dq_imped; + u8 dq_imped_num_settings; + u8 dq_imped_feat_addr; + u8 rb_pulldown_strength; + u8 rb_pulldown_strength_feat_addr; + u8 rb_pulldown_strength_num_settings; + u8 otp_mode; + u8 otp_page_start; + u8 otp_data_prot_addr; + u8 otp_num_pages; + u8 otp_feat_addr; + u8 read_retry_options; + u8 reserved[72]; + u8 param_revision; +} __packed; + +static int micron_nand_setup_read_retry(struct mtd_info *mtd, int retry_mode) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + u8 feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode}; + + return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY, + feature); +} + +/* + * Configure chip properties from Micron vendor-specific ONFI table + */ +static int micron_nand_onfi_init(struct nand_chip *chip) +{ + struct nand_onfi_params *p = &chip->onfi_params; + struct nand_onfi_vendor_micron *micron = (void *)p->vendor; + + if (!chip->onfi_version) + return 0; + + if (le16_to_cpu(p->vendor_revision) < 1) + return 0; + + chip->read_retries = micron->read_retry_options; + chip->setup_read_retry = micron_nand_setup_read_retry; + + return 0; +} + +static int micron_nand_init(struct nand_chip *chip) +{ + struct mtd_info *mtd = nand_to_mtd(chip); + int ret; + + ret = micron_nand_onfi_init(chip); + if (ret) + return ret; + + if (mtd->writesize == 2048) + chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; + + return 0; +} + +const struct nand_manufacturer_ops micron_nand_manuf_ops = { + .init = micron_nand_init, +}; diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 73abb34016..ec0f77b24b 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -388,26 +388,6 @@ struct onfi_ext_param_page { */ } __packed; -struct nand_onfi_vendor_micron { - u8 two_plane_read; - u8 read_cache; - u8 read_unique_id; - u8 dq_imped; - u8 dq_imped_num_settings; - u8 dq_imped_feat_addr; - u8 rb_pulldown_strength; - u8 rb_pulldown_strength_feat_addr; - u8 rb_pulldown_strength_num_settings; - u8 otp_mode; - u8 otp_page_start; - u8 otp_data_prot_addr; - u8 otp_num_pages; - u8 otp_feat_addr; - u8 read_retry_options; - u8 reserved[72]; - u8 param_revision; -} __packed; - struct jedec_ecc_info { u8 ecc_bits; u8 codeword_size; @@ -1161,6 +1141,7 @@ extern struct nand_manufacturers nand_manuf_ids[]; extern const struct nand_manufacturer_ops toshiba_nand_manuf_ops; extern const struct nand_manufacturer_ops samsung_nand_manuf_ops; extern const struct nand_manufacturer_ops hynix_nand_manuf_ops; +extern const struct nand_manufacturer_ops micron_nand_manuf_ops; int nand_default_bbt(struct mtd_info *mtd); int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); From patchwork Thu Jul 14 07:51:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Nazzareno Trimarchi X-Patchwork-Id: 2152 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f69.google.com (mail-ed1-f69.google.com [209.85.208.69]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 6F19A3F013 for ; Thu, 14 Jul 2022 09:51:58 +0200 (CEST) Received: by mail-ed1-f69.google.com with SMTP id s17-20020a056402521100b0043ade613038sf969598edd.17 for ; Thu, 14 Jul 2022 00:51:58 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1657785118; cv=pass; d=google.com; s=arc-20160816; b=NVeDr8/NnOQlgRmd3fk7dJJPD/pOFwIyuas4t64TIN4ln3rgVm4ktIUuZi1HQ8vj8c P4jFKrCz7L7l039bcKByQHXerDRkqIZFQKilwtpSDOWDNInNUGC7BmLaiXJ+K2EFi4W6 annAQ75UoJ3jL2/8b6sSMxSJ5FeFp3sEXkqET8eX2UZzm8AA3KGAigvBiA9j1ARjrvbM vTcE4FwvGx1ZwnGOHflNtYs4Dol2VmAVPdZjDMUkDX6erigJ43UungtwOaiGAyKeAv8n Otb2EDu43GF4gOyHQ1FLgxdcYkV69RmY7IGdDgX2+MJYJF45SY4peavikWv4cXB5N8mM +qxg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=gqT29FCCkJRcL4pI2o3Zjl0mgFzpTIepUGlxsujYces=; b=yp2bzUNAfNVKI/V8lWXnvlDa/zHc3kGqkPmBRB7aK9DmWCFIVfrnmoFoHl/Rid1XDp m//k6TveA9y4xT9wP44iA43oQ/UI49lzU45MQZTD/rCyhCR17UYXTz+37Ms+Np9d7lKN BUGoYOhRGHonR5HnNx490NWKIrxDBMkzGjL++rrkb/Mg+4oFIb+aJ/1HVyjfUznrLzZr U6v45DX1HnaBfVPdcbtfZL9XI4p4Ag1xSWUHf4w7ZPYSr24eU0dzpDM3D3yDfMq6v0yb J2pir0LGDyyWid4O73iCy3GKwag1fPoSF214QksSLmxxZNCdtQQqSE6aL6w1HPGjhgmC xbEw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=o7KrrUvm; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :x-original-sender:x-original-authentication-results:precedence :mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=gqT29FCCkJRcL4pI2o3Zjl0mgFzpTIepUGlxsujYces=; b=F1sxSP858v57ZLC+0ccr4o9WPggJKmsRel5OgC3iGbSyQ9UdlCZoHWRUwQA+F2eH2j IzeqNAPmbhN+EuKXnE36KEEq59vPq7W6U3W8QxYYvTlBZk5dhKikpPgLZTtd2fSgUIFc Q54IAM20SyOLO6/YYoqh23lfQ32cTArR5SWck= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=gqT29FCCkJRcL4pI2o3Zjl0mgFzpTIepUGlxsujYces=; b=uAPsoyQ1fzNB4wijTyRq/+pAezFaDuqTrRmz02rAuAQ1EL65/5x7ub+vCJ/a4G5aOs jDomzTELEl2R9VHzDeGesXcjFFx5gGNMtA/xse98frKs4iEL6xAzUUP4L4KO6IfyPrj8 u2x/HXMNncvU4UZkpOOd1CYsX2fm0n4NEJcyA7wBCzVCW6lRJ87dGiZaFbQmnim7+hoo 19RsdMtAgEY2zP+5cu5KcTHqyOmji/OrkyTtVEd1vL44gaRdv/DEEy2SJeU0SEHhqsd8 AhvR9/VKIacLhmLPYyG3S/lPudG7/m7k84WwswjG8t/ZsU9kZbizkgvIrCDC8NNMlF1J 8lGg== X-Gm-Message-State: AJIora+g5646Wn2g18/4b6uuP+RoK/tXslBtnXNJV/dT3sJCqsCZHlM5 TFee2Mmt1nLXmPyf+IbcS7vDQM8B X-Google-Smtp-Source: AGRyM1t62Ev0+7NciFNomVCone/3Fes4N4r+DtWrkZrRb7dRi2WAwQiHM6VDnf08ylbhHz7QOk6JHg== X-Received: by 2002:a17:907:e90:b0:72b:d0a7:9dd5 with SMTP id ho16-20020a1709070e9000b0072bd0a79dd5mr6693885ejc.18.1657785118158; Thu, 14 Jul 2022 00:51:58 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:907:1c89:b0:72b:5b68:a7e with SMTP id nb9-20020a1709071c8900b0072b5b680a7els1730974ejc.1.gmail; Thu, 14 Jul 2022 00:51:57 -0700 (PDT) X-Received: by 2002:a17:906:974c:b0:72b:8cea:95c2 with SMTP id o12-20020a170906974c00b0072b8cea95c2mr7476877ejy.65.1657785116723; Thu, 14 Jul 2022 00:51:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657785116; cv=none; d=google.com; s=arc-20160816; b=bF0IKgvC+sZo53lgBy08CIsuyK0/Y00fnEqKK04ydozZFVXlkO6VZBJhrtG4Qep7d3 Q+iK1c7ORsuo/FVfMH3iPnP8DyzAS8JyoF7z4QrTUuiKmKCUraowSgtnuPtXoGw6uOIc wgBJGcXqrPIyEA5Q16itTkAp8MiezHxYUKpbhRnBf+44//ETElYGPZjm5yPVrqU0j28g eJFcIat0TLOdsiYW/QyRWitEXzoWxFl0HL5vwLheHzqFaIHdsF8JCQTYFgQHywx83Dlq ky/XIwmUjwSZ7rlP9t3sH8MdXjSfABuqb4F3ugH8R8//JkhkPjwmmyXT2ok9uEXjaQ+Y W/LA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=c811TSPnRtdsguqzLEDKEgLrXxq7i3L2gV2EHdYemL4=; b=jGj12ZFx0ulW4arAPS4FSCua6gy83chnNGm2xlnTrk8jYTMUcGRfu4g2zygTJmMf1n obQ1XEtVfyJqJ0VDIlSh2OzTsPaNhJgLsq37vail226oZ0IH9ncP4888Jkgu+/IcGHyA Hs404zWMvvQ40tSupMSnc6uKQgLoDNuWkPD1XF30dWp9++YfR6z3KSpTq35VNYrKvGbZ AglubAHTK32MhaHw3Jm6sifehV/wNEiDBCjSirF1VRGCEVR6EJ+bXGOhZy1IQyAUwmcx mny0ZQgRJCk+QDNU/AeHkkoi5Mt8JrAImwuAwyM1jZ+YvnAtE8Uh0ciqmBkEP6wuXeeR GkGA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=o7KrrUvm; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id yk19-20020a17090770d300b0072b8fc09908sor272473ejb.133.2022.07.14.00.51.56 for (Google Transport Security); Thu, 14 Jul 2022 00:51:56 -0700 (PDT) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:907:2808:b0:72b:4d49:b2e9 with SMTP id eb8-20020a170907280800b0072b4d49b2e9mr7889053ejc.176.1657785116031; Thu, 14 Jul 2022 00:51:56 -0700 (PDT) Received: from panicking.amarulasolutions.com ([2.198.242.86]) by smtp.gmail.com with ESMTPSA id r23-20020a170906a21700b0072b616ade26sm369252ejy.216.2022.07.14.00.51.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 00:51:55 -0700 (PDT) From: Michael Trimarchi To: linux-amarula@amarulasolutions.com, Dario Binacchi , Tommaso Merciai Subject: [PATCH 10/11] mtd: nand: Move AMD/Spansion specific init/detection logic in nand_amd.c Date: Thu, 14 Jul 2022 09:51:30 +0200 Message-Id: <20220714075131.411548-10-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220714075131.411548-1-michael@amarulasolutions.com> References: <20220714075131.411548-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=o7KrrUvm; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Upstream commit 229204da53b31d576fcc1c93a33626943ea8202c Move AMD/Spansion specific initialization/detection logic into nand_amd.c. This is part of the "separate vendor specific code from core" cleanup process. Signed-off-by: Boris Brezillon Acked-by: Richard Weinberger Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/Makefile | 4 ++- drivers/mtd/nand/raw/nand_amd.c | 53 ++++++++++++++++++++++++++++++++ drivers/mtd/nand/raw/nand_base.c | 17 +--------- drivers/mtd/nand/raw/nand_ids.c | 2 +- include/linux/mtd/rawnand.h | 1 + 5 files changed, 59 insertions(+), 18 deletions(-) create mode 100644 drivers/mtd/nand/raw/nand_amd.c diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index bb20a04616..090bb413f7 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -14,7 +14,8 @@ obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o obj-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o -obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_hynix.o nand_micron.o nand_samsung.o nand_toshiba.o +obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_amd.o nand_hynix.o nand_micron.o \ + nand_samsung.o nand_toshiba.o obj-$(CONFIG_SPL_NAND_IDENT) += nand_ids.o nand_timings.o obj-$(CONFIG_SPL_NAND_INIT) += nand.o ifeq ($(CONFIG_SPL_ENV_SUPPORT),y) @@ -31,6 +32,7 @@ obj-y += nand_ids.o obj-y += nand_util.o obj-y += nand_ecc.o obj-y += nand_base.o +obj-y += nand_amd.o obj-y += nand_hynix.o obj-y += nand_micron.o obj-y += nand_samsung.o diff --git a/drivers/mtd/nand/raw/nand_amd.c b/drivers/mtd/nand/raw/nand_amd.c new file mode 100644 index 0000000000..f11166f361 --- /dev/null +++ b/drivers/mtd/nand/raw/nand_amd.c @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2017 Free Electrons + * Copyright (C) 2017 NextThing Co + * + * Author: Boris Brezillon + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +static void amd_nand_decode_id(struct nand_chip *chip) +{ + struct mtd_info *mtd = nand_to_mtd(chip); + + nand_decode_ext_id(chip); + + /* + * Check for Spansion/AMD ID + repeating 5th, 6th byte since + * some Spansion chips have erasesize that conflicts with size + * listed in nand_ids table. + * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) + */ + if (chip->id.data[4] != 0x00 && chip->id.data[5] == 0x00 && + chip->id.data[6] == 0x00 && chip->id.data[7] == 0x00 && + mtd->writesize == 512) { + mtd->erasesize = 128 * 1024; + mtd->erasesize <<= ((chip->id.data[3] & 0x03) << 1); + } +} + +static int amd_nand_init(struct nand_chip *chip) +{ + if (nand_is_slc(chip)) + chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; + + return 0; +} + +const struct nand_manufacturer_ops amd_nand_manuf_ops = { + .detect = amd_nand_decode_id, + .init = amd_nand_init, +}; diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 9024948ded..baa7618923 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4193,7 +4193,6 @@ static void nand_decode_id(struct nand_chip *chip, struct nand_flash_dev *type) { struct mtd_info *mtd = &chip->mtd; - int maf_id = chip->id.data[0]; mtd->erasesize = type->erasesize; mtd->writesize = type->pagesize; @@ -4201,19 +4200,6 @@ static void nand_decode_id(struct nand_chip *chip, /* All legacy ID NAND are small-page, SLC */ chip->bits_per_cell = 1; - - /* - * Check for Spansion/AMD ID + repeating 5th, 6th byte since - * some Spansion chips have erasesize that conflicts with size - * listed in nand_ids table. - * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) - */ - if (maf_id == NAND_MFR_AMD && chip->id.data[4] != 0x00 && chip->id.data[5] == 0x00 - && chip->id.data[6] == 0x00 && chip->id.data[7] == 0x00 - && mtd->writesize == 512) { - mtd->erasesize = 128 * 1024; - mtd->erasesize <<= ((chip->id.data[3] & 0x03) << 1); - } } /* @@ -4238,8 +4224,7 @@ static void nand_decode_bbm_options(struct mtd_info *mtd, * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba, * AMD/Spansion, and Macronix. All others scan only the first page. */ - if (nand_is_slc(chip) && - (maf_id == NAND_MFR_AMD || maf_id == NAND_MFR_MACRONIX)) + if (nand_is_slc(chip) && maf_id == NAND_MFR_MACRONIX) chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; } diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c index bb5ac8337f..c78f2e0880 100644 --- a/drivers/mtd/nand/raw/nand_ids.c +++ b/drivers/mtd/nand/raw/nand_ids.c @@ -196,7 +196,7 @@ struct nand_manufacturers nand_manuf_ids[] = { {NAND_MFR_STMICRO, "ST Micro"}, {NAND_MFR_HYNIX, "Hynix", &hynix_nand_manuf_ops}, {NAND_MFR_MICRON, "Micron", µn_nand_manuf_ops}, - {NAND_MFR_AMD, "AMD/Spansion"}, + {NAND_MFR_AMD, "AMD/Spansion", &amd_nand_manuf_ops}, {NAND_MFR_MACRONIX, "Macronix"}, {NAND_MFR_EON, "Eon"}, {NAND_MFR_SANDISK, "SanDisk"}, diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index ec0f77b24b..bb1a359a9c 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -1142,6 +1142,7 @@ extern const struct nand_manufacturer_ops toshiba_nand_manuf_ops; extern const struct nand_manufacturer_ops samsung_nand_manuf_ops; extern const struct nand_manufacturer_ops hynix_nand_manuf_ops; extern const struct nand_manufacturer_ops micron_nand_manuf_ops; +extern const struct nand_manufacturer_ops amd_nand_manuf_ops; int nand_default_bbt(struct mtd_info *mtd); int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); From patchwork Thu Jul 14 07:51:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Nazzareno Trimarchi X-Patchwork-Id: 2153 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ej1-f72.google.com (mail-ej1-f72.google.com [209.85.218.72]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 576B13F013 for ; Thu, 14 Jul 2022 09:52:00 +0200 (CEST) Received: by mail-ej1-f72.google.com with SMTP id gr1-20020a170906e2c100b006fefea3ec0asf424060ejb.14 for ; Thu, 14 Jul 2022 00:52:00 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1657785120; cv=pass; d=google.com; s=arc-20160816; b=puXHPzrqbtAvEkJBCv0Ui131I7WeyLpwWtquBhu93nYg2I68kvtSbOwLfdgLlKbaGk gORJDQ2sQ+67lt4ePjoe5DBylFydSzcXpckpXl3i8f4wjCDn0gUkdonBvTDIElo0s4w6 TvWh/UuAOBx+noUyzGMIBwbwF0JcK7vF0Xt2OfkpMmCcfvwdUvJaREzU0lB3vEUDhFSi 00I2q0udQGM5heAe/TEC6CCdeTL86MhsR+EQH8BSjgiu7/1UBT/t0cCI4MRP1q3+RnY6 pQ2UmS3OwvByvY+xBXA9XVCm3YdL4NUFgvbGt3oa3V4N16eMhNMTem0NtVCnFvtnbDda WhTg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=FwJKfOkiRL7xGXLx1b0m6O7PEnZxzovlpeWPhsE5gII=; b=MEDCKbwJTuVMDUl1NCmf9qihQhbkkGjUsHp+I3VKU3A+rkS0DNn2sAl+30G8l8BoTN PFeJ5F9XZxEAPR5m/LLEd4d8EIAawELhhB8WtN2roygI2UAI3ZWe0UubOwNa4r9UQGHk sjwia+A084FaQAv45HFnmSGFC4LHU7SbtrP4Tsu+xS89gSFoX4d9Gw/FSdAWnH5jI60+ SfJDPLc19Vl0qb5jQAv03e4XptSbdmfYHTiftf/VTVFldlUbN91Kdju83AZiLO7Sn4HJ e6vZVI85H9X1SWv1zDegFWWsVE9bQ3ak2ag/d1aPAEvuq/hIrr4lV1SnBEy7wZJYzqq4 u7gw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=lqvgGs5H; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :x-original-sender:x-original-authentication-results:precedence :mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=FwJKfOkiRL7xGXLx1b0m6O7PEnZxzovlpeWPhsE5gII=; b=FQ3fv6z8BMkmzCllcW9HNf611o2jMYkMuxcmnd3SPcyyaZ8gmRSHkVg0i0cazEw5Pb NqgvCB5x7K87U13H9Qknsb7wd1Zgp42hzSrQI9sLAFmVnkcPB7oXeUx2bvB0C5bEcq0l hnx4B8fZ19RSOyVV0a3leMV5BHtl+6pHZc9TY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=FwJKfOkiRL7xGXLx1b0m6O7PEnZxzovlpeWPhsE5gII=; b=CLgbCl8cmTmYGn3Lm1OPXcDwEvBPd4Opo/f8EwPFC0Gk+cvvLG1ZngpVx14MMCLx2V 7JYNT3g3DCujfb+eYNPjUsZiSrkVSAM7EcC7kWNyBHhPpXE/bBfFmxPDx9YUMTGUeAq8 wjJi+ItxniXilWdJspQLaUr0zW2HeTonE+7AgVzpBZJCswRIcM/wH1KyqHGsqRe/+D6d p6p5rwG46EQHZLSBxQzNyRwkHcZYHoQiZxTYQt6fOmkpOqpa76dS13N+gHRJAtFWPE5P 3mmcRDdnmh0ByqJ/tnOdIjNRAUrVLwjIptDqdL8LClhh9idZxfAnKrSbHIP7t+rz9cmt bTXw== X-Gm-Message-State: AJIora9F+pwm2JD6VIHqXf24k2eJz42z9jzpYQKFBMFvfpqZ3sHS4P8L IT+DlzsMFeatZ6Xajej4l+qEZBNp X-Google-Smtp-Source: AGRyM1vhRUgwZSCMs5XoW1TGkIf7GGW0V4BfTjw4aHOWWlGK5NTGYt533/tGxjA73zumWT4qp7wOUw== X-Received: by 2002:a17:907:2bcc:b0:72b:3391:59fd with SMTP id gv12-20020a1709072bcc00b0072b339159fdmr7569395ejc.509.1657785120184; Thu, 14 Jul 2022 00:52:00 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:906:70cf:b0:6fe:d027:3c1f with SMTP id g15-20020a17090670cf00b006fed0273c1fls4177018ejk.2.gmail; Thu, 14 Jul 2022 00:51:59 -0700 (PDT) X-Received: by 2002:a17:906:7304:b0:6ff:a76:5b09 with SMTP id di4-20020a170906730400b006ff0a765b09mr7310287ejc.193.1657785118825; Thu, 14 Jul 2022 00:51:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657785118; cv=none; d=google.com; s=arc-20160816; b=YNMo7ZYuQyAsyNV5vLjG1/dNCs2mwe4y9jTnetMcxF3VpGRJDS38WGMLTMUy9xisb5 QOL2yV0apLhUq3f3zLl0GzuPYvZD9MinyXnkZWsYVCJYb18tRBUYIAhPTMlaKDVKW8sL X+45Xn2BAFWFAExMzf45R0tSwDpWPqw7IK3UVBr+5B2mTRNk3Ololjt/2d300yPJ/Tr0 UhGUkP6TsXHYI4Nt+5ptzTQzM4zhOEK7kLAoA1XX/Dsmapd+7tkBo/VbZW2EykxZWQTD ihrXmsOa6dgILitLBxG5apnOc6dtGvwA8TBItAaStbCNgXVP8jh9OB529QQEcHfizDzJ Fi9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=IlWkK+BuUZfXUw6/qJJsivj+j+ojfyd53fXmVlibE+4=; b=ezZXewOJnX31ly9+LtaGMm4Wmxtn0you3+JSoUrTuKh+4UTqxLLcqK88i8cxomvB9p c8oaJWf197gPOfTyBU23akWXdzruvuSP7hYzh3szkRB3AzIHZ4rRQpyFwxFkgwFn1xjN imll+El9hTld8UGiMwFlF2U5XeKQJPsM/TQuId6GitV5P9J56gW6QYTuYuiD40EMqWH0 oBwlc2pVEfFBkDDH7NoRefVqlOSJvbTlzX1FHR0p6qubilO0v6jcrEvugaQxc4o6DI5H TSvoE/Ri3COy6AsDJl3y0aB0k1xQQnMd6qz9Wthf9qjoFXgPETEQRpKKBNVsHy8wKyML 8LKQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=lqvgGs5H; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id dv3-20020a170906b80300b0072b5f614ddcsor306557ejb.41.2022.07.14.00.51.58 for (Google Transport Security); Thu, 14 Jul 2022 00:51:58 -0700 (PDT) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:906:6989:b0:726:f129:1748 with SMTP id i9-20020a170906698900b00726f1291748mr7318783ejr.495.1657785118147; Thu, 14 Jul 2022 00:51:58 -0700 (PDT) Received: from panicking.amarulasolutions.com ([2.198.242.86]) by smtp.gmail.com with ESMTPSA id r23-20020a170906a21700b0072b616ade26sm369252ejy.216.2022.07.14.00.51.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jul 2022 00:51:57 -0700 (PDT) From: Michael Trimarchi To: linux-amarula@amarulasolutions.com, Dario Binacchi , Tommaso Merciai Subject: [PATCH 11/11] mtd: nand: Move Macronix specific initialization in nand_macronix.c Date: Thu, 14 Jul 2022 09:51:31 +0200 Message-Id: <20220714075131.411548-11-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220714075131.411548-1-michael@amarulasolutions.com> References: <20220714075131.411548-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=lqvgGs5H; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Upstream commit 3b5206f4be9b65d2f0f85b3239cf117a1d0de7ce Move Macronix specific initialization logic into nand_macronix.c. This is part of the "separate vendor specific code from core" cleanup process. Signed-off-by: Boris Brezillon Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/Makefile | 4 +++- drivers/mtd/nand/raw/nand_base.c | 11 ---------- drivers/mtd/nand/raw/nand_ids.c | 2 +- drivers/mtd/nand/raw/nand_macronix.c | 32 ++++++++++++++++++++++++++++ include/linux/mtd/rawnand.h | 1 + 5 files changed, 37 insertions(+), 13 deletions(-) create mode 100644 drivers/mtd/nand/raw/nand_macronix.c diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 090bb413f7..d888eb2be5 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -14,7 +14,8 @@ obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o obj-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o -obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_amd.o nand_hynix.o nand_micron.o \ +obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_amd.o nand_hynix.o \ + nand_macronix.o nand_micron.o \ nand_samsung.o nand_toshiba.o obj-$(CONFIG_SPL_NAND_IDENT) += nand_ids.o nand_timings.o obj-$(CONFIG_SPL_NAND_INIT) += nand.o @@ -34,6 +35,7 @@ obj-y += nand_ecc.o obj-y += nand_base.o obj-y += nand_amd.o obj-y += nand_hynix.o +obj-y += nand_macronix.o obj-y += nand_micron.o obj-y += nand_samsung.o obj-y += nand_toshiba.o diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index baa7618923..b16300c304 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4210,22 +4210,11 @@ static void nand_decode_id(struct nand_chip *chip, static void nand_decode_bbm_options(struct mtd_info *mtd, struct nand_chip *chip) { - int maf_id = chip->id.data[0]; - /* Set the bad block position */ if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16)) chip->badblockpos = NAND_LARGE_BADBLOCK_POS; else chip->badblockpos = NAND_SMALL_BADBLOCK_POS; - - /* - * Bad block marker is stored in the last page of each block on Samsung - * and Hynix MLC devices; stored in first two pages of each block on - * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba, - * AMD/Spansion, and Macronix. All others scan only the first page. - */ - if (nand_is_slc(chip) && maf_id == NAND_MFR_MACRONIX) - chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; } static inline bool is_full_id_nand(struct nand_flash_dev *type) diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c index c78f2e0880..7602dd30f1 100644 --- a/drivers/mtd/nand/raw/nand_ids.c +++ b/drivers/mtd/nand/raw/nand_ids.c @@ -197,7 +197,7 @@ struct nand_manufacturers nand_manuf_ids[] = { {NAND_MFR_HYNIX, "Hynix", &hynix_nand_manuf_ops}, {NAND_MFR_MICRON, "Micron", µn_nand_manuf_ops}, {NAND_MFR_AMD, "AMD/Spansion", &amd_nand_manuf_ops}, - {NAND_MFR_MACRONIX, "Macronix"}, + {NAND_MFR_MACRONIX, "Macronix", ¯onix_nand_manuf_ops}, {NAND_MFR_EON, "Eon"}, {NAND_MFR_SANDISK, "SanDisk"}, {NAND_MFR_INTEL, "Intel"}, diff --git a/drivers/mtd/nand/raw/nand_macronix.c b/drivers/mtd/nand/raw/nand_macronix.c new file mode 100644 index 0000000000..3cccb5869a --- /dev/null +++ b/drivers/mtd/nand/raw/nand_macronix.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2017 Free Electrons + * Copyright (C) 2017 NextThing Co + * + * Author: Boris Brezillon + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +static int macronix_nand_init(struct nand_chip *chip) +{ + if (nand_is_slc(chip)) + chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; + + return 0; +} + +const struct nand_manufacturer_ops macronix_nand_manuf_ops = { + .init = macronix_nand_init, +}; diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index bb1a359a9c..aa45558b3d 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -1143,6 +1143,7 @@ extern const struct nand_manufacturer_ops samsung_nand_manuf_ops; extern const struct nand_manufacturer_ops hynix_nand_manuf_ops; extern const struct nand_manufacturer_ops micron_nand_manuf_ops; extern const struct nand_manufacturer_ops amd_nand_manuf_ops; +extern const struct nand_manufacturer_ops macronix_nand_manuf_ops; int nand_default_bbt(struct mtd_info *mtd); int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);