From patchwork Fri Jul 22 16:09:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2230 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f70.google.com (mail-ed1-f70.google.com [209.85.208.70]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id A2DF73F047 for ; Fri, 22 Jul 2022 18:11:09 +0200 (CEST) Received: by mail-ed1-f70.google.com with SMTP id w15-20020a056402268f00b0043ac600a6bcsf3113108edd.6 for ; Fri, 22 Jul 2022 09:11:09 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1658506269; cv=pass; d=google.com; s=arc-20160816; b=r/7M0rU5E9Cr3guZq15TRj7rttaOr+e5kiWZYH8t9TG2uZj4zkNmIhnJ3blXmzFtWi fjg6doTXDhQuerbbjGxQ9qujnrEJ0IZeOM+WVuur/L400K/verKO1mupQkNeUa1WE+Ov tBbdhJLcuqUgvpxdGvHNICwYcI22SM4U69+8oyv9mZ/0mPypC9FfHkS4LKRRlVcpnsDK 23ojvFxvRz9I+1IS2LCIQjyH3N7fP+mB76vuHaAl7nqD2FR8AtC4g6BrLvdCv1ky3ZVH MzRhtR5o7ggfTOdn4V8XYfqNS8tvI20hDlGZEp1yqRA9+znuaGppjQO6nNc0gtmnrLDm +pKA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=NvDKTqSpMiZK09DpgobAKvYfVWZ4vJSSyEY7EknLV2g=; b=CGpZuaWJpaixC74o+m2zGmm6ou1d2noZVtnDd/4AaiKwLO/Tfyd9KcIPbbp/II4Xdo iXlAFk3v3qkShsdqlLkAGMF+2oiUit0iP1zdkW8lfUwwusOKxE6hYWqXTUPQJYTbSutN FMRnzH4OY+AfuTnMiiNzDZbi816bx8BIfeVcFzZIoTwaZLKBrV6OMoyxxMSw4yTVPqQs kbRh2KsiARpcpqMu4W8mo4I98HasJKI1ZrG4t4JE9N5zJoGX8d4pWZApaayENosNP4wP VDVC+/1mqq61cOrSc74N45IeeXBXHitM5l81zaLNh1cJMzftJ+cduQhAz1XKuRUmxhC6 bJnA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=I7jHdhGU; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=NvDKTqSpMiZK09DpgobAKvYfVWZ4vJSSyEY7EknLV2g=; b=p1NPPdA1ebSsDigzEwuFLP6mDYr4Eji0IKvM5R08GH6BWKoYj6AFxihJT2+PPKlNG2 f3B+HtaDfFafSxGpGruVzdA4Osvl0lDx/fHm6P5SDJ7x1wXqcsYdA7XNltIoijRRkgMF sBeWcRFQidMCMvbcKpRWIX0clNjcXyjOuJ2Ik= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=NvDKTqSpMiZK09DpgobAKvYfVWZ4vJSSyEY7EknLV2g=; b=q7SKA3DFaaKv+ZLZyjPGJYogyKKvFvnKtbAqQx2fmlNsgHcUm5hAvt9/bjJV0XUcUh gaPbhMuX1EKEND/r8NC7ga2Muh07nAQag/wmrzvu+X2qbgaMgACf7vtujUYKbWX6jgNX aY9hVbALd3gRoNQAE1npDbgFeRSRpJNmVTqCcIpXz4CPFIAI1tSpjVZCTbtRe7hjQY1e irlM6YGHJ6D2UcTSnDp9tt59EsGY//x+FnHEtbR4pzeaB9Sydkp11xgQj2EVWRRhlQ6o k/8/BIsQLZXiXGNlagP+R+HE+uC/MjjK3wKkj/DFCziI+MR0PRztkkEGFGG5H6jg3XmT njNw== X-Gm-Message-State: AJIora8vI5uQYMfNai8REQVb5NJ7bY2rhE4IDWYsHsi74baqyZhKizwf 8XFNi9Cs9B3cHJLCELt0Jj4wdssD X-Google-Smtp-Source: AGRyM1u6KiugAiIdR/BnAwxYDcFxqMGzkN+vIotN4o/txFmYr+fTdvElBn3FZZO7QH1KTGPizt8f7Q== X-Received: by 2002:a05:6402:1d4a:b0:43a:ca49:abc6 with SMTP id dz10-20020a0564021d4a00b0043aca49abc6mr591268edb.376.1658506269301; Fri, 22 Jul 2022 09:11:09 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:906:3691:b0:72b:564b:c25b with SMTP id a17-20020a170906369100b0072b564bc25bls3081862ejc.7.-pod-prod-gmail; Fri, 22 Jul 2022 09:11:08 -0700 (PDT) X-Received: by 2002:a17:907:6ea7:b0:72f:2cf2:9aef with SMTP id sh39-20020a1709076ea700b0072f2cf29aefmr484114ejc.215.1658506268100; Fri, 22 Jul 2022 09:11:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1658506268; cv=none; d=google.com; s=arc-20160816; b=c4rxb/vvi1tUDnYoS9HpQAb3/FrCvcdBbwffvsQs8OdeKK4qZuI5O5rLM2/WxuSSHx 7sHXeOfXKHZR+zIPvz4wyGUn4FDn57zI+YqufmKUSik/ReqGKkI3TJHKi2seKAdwJI73 BP/FaQSYWU4AXQVzlATq7/cnXcaf8mGX1inGBx2fPdifoFEKpwjM1KvWRWUDTI99y+TQ 3AbAACCoVC6JPqNHhmel9cjdaFXh5zIEZzMbmJBywSVt7fA63wOloDJmkYT/KrZIM3PC ucu/2XBn17RSfhVnFBFiTm9zHSE2H9l5Z9qPjBi7J0TAts9nQ1MFld/mTMdY3Qrqe6sS yL+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=MIMeEQi2VWuSW6sjH1otL/u4J2uLB6sK3BK7CTYNm7w=; b=TsOvqGNfUcBRR0L+tt9xvDHG8Rmx37MU97f1oZUrqYUBWWqZAvPTChRHkYxrDvoNAO LVOyN7CX7B7TqoDpw3Se2RVu0FcOYY7uZUHJXAKMYhxAdtPBU7dPHpLuRooQFyI9GQ3c fP0nIxf0gmuNgupeQCbihUrmBDdAFdZ5EV+3hlS4Osa1U71TVLMWOau9/uZuS7va5ybu AzezO+wnwVTYCwAgaYk+WUUm9XO0kUhjTEUh2ASmKX6sTFz8nsww4FDwlRV8NkNGD9G+ 1RVzwhN8QcZHmcmm0XgUHGuW1CobLUiX+EG+ZFRRbTPSzKtfmjrhlzVy7dNc3EjGdzsE cEtQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=I7jHdhGU; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id f2-20020a17090660c200b0072f8a4320e8sor2194773ejk.47.2022.07.22.09.11.08 for (Google Transport Security); Fri, 22 Jul 2022 09:11:08 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:907:94ce:b0:72f:2cfa:b7b7 with SMTP id dn14-20020a17090794ce00b0072f2cfab7b7mr475467ejc.630.1658506267653; Fri, 22 Jul 2022 09:11:07 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.pdxnet.pdxeng.ch (host-87-14-98-67.retail.telecomitalia.it. [87.14.98.67]) by smtp.gmail.com with ESMTPSA id d19-20020a170906305300b006fe8ac6bc69sm2174025ejd.140.2022.07.22.09.11.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Jul 2022 09:11:07 -0700 (PDT) From: Dario Binacchi To: u-boot@lists.denx.de Cc: Amarula patchwork , michael@amarulasolutions.com, Dario Binacchi Subject: [PATCH v4 01/14] mtd: nand: Get rid of busw parameter Date: Fri, 22 Jul 2022 18:09:55 +0200 Message-Id: <20220722161009.2686504-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220722161009.2686504-1-dario.binacchi@amarulasolutions.com> References: <20220722161009.2686504-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=I7jHdhGU; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Michael Trimarchi Upstream linux commit 29a198a1592d83. Auto-detection functions are passed a busw parameter to retrieve the actual NAND bus width and eventually set the correct value in chip->options. Rework the nand_get_flash_type() function to get rid of this extra parameter and let detection code directly set the NAND_BUSWIDTH_16 flag in chip->options if needed. Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi --- (no changes since v3) Changes in v3: - Use commit sha1 with 13 digits. Changes in v2: - Use short-commit form. - Remove linux info. Uboot seems that backport without add this extra information. drivers/mtd/nand/raw/nand_base.c | 59 +++++++++++++++++--------------- 1 file changed, 32 insertions(+), 27 deletions(-) diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index e8ece0a4a0dd..9a2194ebd3f8 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -3898,8 +3898,7 @@ static void nand_onfi_detect_micron(struct nand_chip *chip, /* * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise. */ -static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, - int *busw) +static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip) { struct nand_onfi_params *p = &chip->onfi_params; char id[4]; @@ -3971,9 +3970,7 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, chip->bits_per_cell = p->bits_per_cell; if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS) - *busw = NAND_BUSWIDTH_16; - else - *busw = 0; + chip->options |= NAND_BUSWIDTH_16; if (p->ecc_bits != 0xff) { chip->ecc_strength_ds = p->ecc_bits; @@ -4003,8 +4000,7 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, return 1; } #else -static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, - int *busw) +static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip) { return 0; } @@ -4013,8 +4009,7 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, /* * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise. */ -static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip, - int *busw) +static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip) { struct nand_jedec_params *p = &chip->jedec_params; struct jedec_ecc_info *ecc; @@ -4076,9 +4071,7 @@ static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip, chip->bits_per_cell = p->bits_per_cell; if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS) - *busw = NAND_BUSWIDTH_16; - else - *busw = 0; + chip->options |= NAND_BUSWIDTH_16; /* ECC info */ ecc = &p->ecc_info[0]; @@ -4168,7 +4161,7 @@ static int nand_get_bits_per_cell(u8 cellinfo) * manufacturer-specific "extended ID" decoding patterns. */ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, - u8 id_data[8], int *busw) + u8 id_data[8]) { int extid, id_len; /* The 3rd id byte holds MLC / multichip data */ @@ -4221,7 +4214,6 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, /* Calc blocksize */ mtd->erasesize = (128 * 1024) << (((extid >> 1) & 0x04) | (extid & 0x03)); - *busw = 0; } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX && !nand_is_slc(chip)) { unsigned int tmp; @@ -4262,7 +4254,6 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, mtd->erasesize = 768 * 1024; else mtd->erasesize = (64 * 1024) << tmp; - *busw = 0; } else { /* Calc pagesize */ mtd->writesize = 1024 << (extid & 0x03); @@ -4275,7 +4266,9 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, mtd->erasesize = (64 * 1024) << (extid & 0x03); extid >>= 2; /* Get buswidth information */ - *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; + /* Get buswidth information */ + if (extid & 0x1) + chip->options |= NAND_BUSWIDTH_16; /* * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per @@ -4301,15 +4294,13 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, * the chip. */ static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, - struct nand_flash_dev *type, u8 id_data[8], - int *busw) + struct nand_flash_dev *type, u8 id_data[8]) { int maf_id = id_data[0]; mtd->erasesize = type->erasesize; mtd->writesize = type->pagesize; mtd->oobsize = mtd->writesize / 32; - *busw = type->options & NAND_BUSWIDTH_16; /* All legacy ID NAND are small-page, SLC */ chip->bits_per_cell = 1; @@ -4371,7 +4362,7 @@ static inline bool is_full_id_nand(struct nand_flash_dev *type) } static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, - struct nand_flash_dev *type, u8 *id_data, int *busw) + struct nand_flash_dev *type, u8 *id_data) { if (!strncmp((char *)type->id, (char *)id_data, type->id_len)) { mtd->writesize = type->pagesize; @@ -4386,8 +4377,6 @@ static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, chip->onfi_timing_mode_default = type->onfi_timing_mode_default; - *busw = type->options & NAND_BUSWIDTH_16; - if (!mtd->name) mtd->name = type->name; @@ -4449,9 +4438,24 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, if (!type) type = nand_flash_ids; + /* + * Save the NAND_BUSWIDTH_16 flag before letting auto-detection logic + * override it. + * This is required to make sure initial NAND bus width set by the + * NAND controller driver is coherent with the real NAND bus width + * (extracted by auto-detection code). + */ + busw = chip->options & NAND_BUSWIDTH_16; + + /* + * The flag is only set (never cleared), reset it to its default value + * before starting auto-detection. + */ + chip->options &= ~NAND_BUSWIDTH_16; + for (; type->name != NULL; type++) { if (is_full_id_nand(type)) { - if (find_full_id_nand(mtd, chip, type, id_data, &busw)) + if (find_full_id_nand(mtd, chip, type, id_data)) goto ident_done; } else if (*dev_id == type->dev_id) { break; @@ -4461,11 +4465,11 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, chip->onfi_version = 0; if (!type->name || !type->pagesize) { /* Check if the chip is ONFI compliant */ - if (nand_flash_detect_onfi(mtd, chip, &busw)) + if (nand_flash_detect_onfi(mtd, chip)) goto ident_done; /* Check if the chip is JEDEC compliant */ - if (nand_flash_detect_jedec(mtd, chip, &busw)) + if (nand_flash_detect_jedec(mtd, chip)) goto ident_done; } @@ -4479,10 +4483,11 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, if (!type->pagesize) { /* Decode parameters from extended ID */ - nand_decode_ext_id(mtd, chip, id_data, &busw); + nand_decode_ext_id(mtd, chip, id_data); } else { - nand_decode_id(mtd, chip, type, id_data, &busw); + nand_decode_id(mtd, chip, type, id_data); } + /* Get chip options */ chip->options |= type->options; From patchwork Fri Jul 22 16:09:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2231 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f69.google.com (mail-ed1-f69.google.com [209.85.208.69]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 9EBD63F047 for ; Fri, 22 Jul 2022 18:11:10 +0200 (CEST) Received: by mail-ed1-f69.google.com with SMTP id s17-20020a056402521100b0043ade613038sf3149876edd.17 for ; Fri, 22 Jul 2022 09:11:10 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1658506270; cv=pass; d=google.com; s=arc-20160816; b=FTjMFn4eP+4JJeZmuTcrOa41jlJIeIcLnPTm/N+0uwU6lgX8zoJXokJH43W6wOQZzZ 5imQO6X+h1FTN/GRtiLPGwIAEK+UidPUfnumt96NWNPjQwfz+ALH4iVIVKMHnhFV8vHZ fzad7i42gRMSM1ZEnmWl6FHrFYy+8b9nHbOpBAYZysPssdWbg10UD7/zojxgqHHmqEG/ 4uTpFKD11noj9MZ6Z/6fZjm5tX8GRBIKk7QunXX3qTE6Ybsu8etWf6MnTyk0jmHJRl7X wplASj+NcEtXh+mTcx/9/xjJtbIMYJjvusAz+3LIU54oLCD81CVTLz2lpZHP7/xMtnJr ujFg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=LVW335RbWk5xAKyfiuoV8s1q/MvuSYUQLtcUBQKIrpI=; b=vMd6sQg5DRBCcjfDwTuVc3GH2l2kqXK0yqen9FWvDGDtRRlAN5sZ40k+Epl6QXcStz nkVX8iqO6QmmN44EuElWAtpMkfM9oorHHNsqwdU9VTjSaO9toC2tJGnUOKc67RjGaFks GBzeGEhh4hPhv1aw1rUgMlaxPehYUVIKHlnhvNzUNUvtT9w13TvsR5Q3CwTYL1vrknxx BtI5zO6U7XNL0r+4Q53qvY8leziJPF8iI3md6Dde2Pi4e6E0sYriwC4znkhG38VzxaFe njz11K6k7Tg0z2BxVZVkjREKffhPm4+13ySXoi965R6jPSOhY5Wj5syj17CeRxUre1H3 deEg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=kh1E7ak5; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=LVW335RbWk5xAKyfiuoV8s1q/MvuSYUQLtcUBQKIrpI=; b=RTXuCFG0iI4ezFelHxrTsRFwWYJFyqAH+Jar129raU3gC4PVqbBFD55MbZpStly4u3 eDb78qRty7TneVyfdDDtC8+G0rdk4fdIVGj4AryokXSBKaJ6Ko8IvjPDKPbSp5rChqg5 nLXq3XUh/zwm9BfihgGe3LZ/mj6Tq2eiH3qWc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=LVW335RbWk5xAKyfiuoV8s1q/MvuSYUQLtcUBQKIrpI=; b=k/e6sQ5isgnULq42GGpqC1/9PAHy2bWnEpOMPlPmFISjOioXfJoqtVPeJzrYHqvN9E Mf2FQShsLSZhWQGKhq5/P20jPMggMX/EU/Iuan4NXxO3kgq3wusu4hygvb1JqEd2hsdU IA7gZc5OYZ13lGm4GsaX65gICSxww651KZ/FmRm7YjIaodEsS/S+QEuEnZ5geIh8w3OY uDt9bbU/Nr4ANLc84F9q1ui7HlepymlEcHVjI4KAINCSYow0VRnFAccGN2B7WKDLeRoT JZMjFjwA9ihBpFe7v9SvrniJ2UjTrcn8bkCyYswNY6kXpRiCj1yoLXPMsj7Kh0jxf5dh XdcA== X-Gm-Message-State: AJIora+c4dWHrsHXNuollMnkMynvGA30vywMY4PlvF/RjOacf3R131Ns IxmlgL0mXotGpSBQ7Ml0MKpBbyJv X-Google-Smtp-Source: AGRyM1uyIOT+ZxAYklUrMVY/Ys31y1yLhAleNY6fx1tWRqP6FDZUJhSQsHVOhPQWwppmoykdUaC/6g== X-Received: by 2002:a05:6402:4442:b0:43b:c866:21be with SMTP id o2-20020a056402444200b0043bc86621bemr645900edb.28.1658506270474; Fri, 22 Jul 2022 09:11:10 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:906:3e57:b0:6fe:b664:4b5f with SMTP id t23-20020a1709063e5700b006feb6644b5fls3069941eji.2.-pod-prod-gmail; Fri, 22 Jul 2022 09:11:09 -0700 (PDT) X-Received: by 2002:a17:906:2086:b0:717:4e91:f1db with SMTP id 6-20020a170906208600b007174e91f1dbmr461232ejq.345.1658506269318; Fri, 22 Jul 2022 09:11:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1658506269; cv=none; d=google.com; s=arc-20160816; b=LG54VJFPt3G7kzWySllYuq2vpnFAK6g5/Z6yivqxVc9t/CR6LoowYn7jrAeuvRwNt8 6JzsZOIUqg2GFZAvr4LZr5Va5yAjbVOItBN6kJw4jkM2NWcP+wHac+BuaV3GCjNpaSDF t4k2oGy+YCjXqrda7jqUBrdlTI7is99uCo5s0MQPhMW2D2fGxO4jXYwcvSybKhi8caE7 22SlHAkWUdcoyLBu+QAsebAECkZd+aOg6+ZPloxPaHzRWPXQOCC8jGlr5COa0ZbkG+Xv iqrhZxRjeZgC+//Z40GbYK6sog4nyHRfrfKVzMy+hkUjkdKg1ATK25muRqwT8Pj1mYJ+ sRyQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=DpblvzNlrwZCrtN/r1WNBm40ia9uEmGxnusYMfCR8bI=; b=aSrhiSTkOAdA+LgDdXl4oBPOmYDgCzc68GK1FpbZoPtoRIYiIb1ZeJ4p+qE3uzXrQd VdI+cKQYDzYIZQ/ac4G7AB8b9MxSmDiy8LZdfEB/KAJHECKFbJ5lQTnX/yVk1m86/Kvr Hn2NZ7MpGiuIo4RB5f693V0Qrw3ahRcoO2pgA1VeoyZ9MaMJMeJIriWmEUlJnlNgDk1c +ABIjq8D3PrnMoZ6R3XrKKmqsGqClk61y/NaYYnWQVU1Zf0IFyCzeuZ1PENrHSRivX+m X91fmtOg8znY7Up4XM8ylcBbydzG6kTmkDbhCOoLJfiHXydzXU8PbQKSFB5xRWgP6LD+ jANg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=kh1E7ak5; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id j5-20020a170906430500b0072a6696313asor2332123ejm.76.2022.07.22.09.11.09 for (Google Transport Security); Fri, 22 Jul 2022 09:11:09 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:907:2c61:b0:72b:3a12:5121 with SMTP id ib1-20020a1709072c6100b0072b3a125121mr506944ejc.52.1658506268914; Fri, 22 Jul 2022 09:11:08 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.pdxnet.pdxeng.ch (host-87-14-98-67.retail.telecomitalia.it. [87.14.98.67]) by smtp.gmail.com with ESMTPSA id d19-20020a170906305300b006fe8ac6bc69sm2174025ejd.140.2022.07.22.09.11.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Jul 2022 09:11:08 -0700 (PDT) From: Dario Binacchi To: u-boot@lists.denx.de Cc: Amarula patchwork , michael@amarulasolutions.com, Dario Binacchi , Patrice Chotard , Simon Glass , Wolfgang Denk Subject: [PATCH v4 02/14] mtd: nand: Store nand ID in struct nand_chip Date: Fri, 22 Jul 2022 18:09:56 +0200 Message-Id: <20220722161009.2686504-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220722161009.2686504-1-dario.binacchi@amarulasolutions.com> References: <20220722161009.2686504-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=kh1E7ak5; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Michael Trimarchi Upstream linux commit 7f501f0a72036d. Store the NAND ID in struct nand_chip to avoid passing id_data and id_len as function parameters. Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi --- (no changes since v3) Changes in v3: - Use commit sha1 with 13 digits. - Fix code style warnings raised by patman. Changes in v2: - Use short-commit form. - Remove linux info. Uboot seems that backport without add this extra information. drivers/mtd/nand/raw/nand_base.c | 58 ++++++++++++++++---------------- include/linux/mtd/rawnand.h | 15 +++++++++ 2 files changed, 44 insertions(+), 29 deletions(-) diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 9a2194ebd3f8..220804c75c87 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4160,16 +4160,14 @@ static int nand_get_bits_per_cell(u8 cellinfo) * chip. The rest of the parameters must be decoded according to generic or * manufacturer-specific "extended ID" decoding patterns. */ -static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, - u8 id_data[8]) +static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip) { int extid, id_len; /* The 3rd id byte holds MLC / multichip data */ - chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); + chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]); /* The 4th id byte is the important one */ - extid = id_data[3]; - - id_len = nand_id_len(id_data, 8); + extid = chip->id.data[3]; + id_len = chip->id.len; /* * Field definitions are in the following datasheets: @@ -4180,8 +4178,8 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung * ID to decide what to do. */ - if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG && - !nand_is_slc(chip) && id_data[5] != 0x00) { + if (id_len == 6 && chip->id.data[0] == NAND_MFR_SAMSUNG && + !nand_is_slc(chip) && chip->id.data[5] != 0x00) { /* Calc pagesize */ mtd->writesize = 2048 << (extid & 0x03); extid >>= 2; @@ -4214,7 +4212,7 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, /* Calc blocksize */ mtd->erasesize = (128 * 1024) << (((extid >> 1) & 0x04) | (extid & 0x03)); - } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX && + } else if (id_len == 6 && chip->id.data[0] == NAND_MFR_HYNIX && !nand_is_slc(chip)) { unsigned int tmp; @@ -4278,10 +4276,10 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, * 110b -> 24nm * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC */ - if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA && - nand_is_slc(chip) && - (id_data[5] & 0x7) == 0x6 /* 24nm */ && - !(id_data[4] & 0x80) /* !BENAND */) { + if (id_len >= 6 && chip->id.data[0] == NAND_MFR_TOSHIBA && + nand_is_slc(chip) && + (chip->id.data[5] & 0x7) == 0x6 /* 24nm */ && + !(chip->id.data[4] & 0x80) /* !BENAND */) { mtd->oobsize = 32 * mtd->writesize >> 9; } @@ -4294,9 +4292,9 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, * the chip. */ static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, - struct nand_flash_dev *type, u8 id_data[8]) + struct nand_flash_dev *type) { - int maf_id = id_data[0]; + int maf_id = chip->id.data[0]; mtd->erasesize = type->erasesize; mtd->writesize = type->pagesize; @@ -4311,11 +4309,11 @@ static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, * listed in nand_ids table. * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) */ - if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00 - && id_data[6] == 0x00 && id_data[7] == 0x00 - && mtd->writesize == 512) { + if (maf_id == NAND_MFR_AMD && chip->id.data[4] != 0x00 && + chip->id.data[5] == 0x00 && chip->id.data[6] == 0x00 && + chip->id.data[7] == 0x00 && mtd->writesize == 512) { mtd->erasesize = 128 * 1024; - mtd->erasesize <<= ((id_data[3] & 0x03) << 1); + mtd->erasesize <<= ((chip->id.data[3] & 0x03) << 1); } } @@ -4325,9 +4323,9 @@ static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, * page size, cell-type information). */ static void nand_decode_bbm_options(struct mtd_info *mtd, - struct nand_chip *chip, u8 id_data[8]) + struct nand_chip *chip) { - int maf_id = id_data[0]; + int maf_id = chip->id.data[0]; /* Set the bad block position */ if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16)) @@ -4362,14 +4360,14 @@ static inline bool is_full_id_nand(struct nand_flash_dev *type) } static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, - struct nand_flash_dev *type, u8 *id_data) + struct nand_flash_dev *type) { - if (!strncmp((char *)type->id, (char *)id_data, type->id_len)) { + if (!strncmp((char *)type->id, (char *)chip->id.data, type->id_len)) { mtd->writesize = type->pagesize; mtd->erasesize = type->erasesize; mtd->oobsize = type->oobsize; - chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); + chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]); chip->chipsize = (uint64_t)type->chipsize << 20; chip->options |= type->options; chip->ecc_strength_ds = NAND_ECC_STRENGTH(type); @@ -4395,7 +4393,7 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, { int busw, ret; int maf_idx; - u8 id_data[8]; + u8 *id_data = chip->id.data; /* * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) @@ -4453,9 +4451,11 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, */ chip->options &= ~NAND_BUSWIDTH_16; + chip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data)); + for (; type->name != NULL; type++) { if (is_full_id_nand(type)) { - if (find_full_id_nand(mtd, chip, type, id_data)) + if (find_full_id_nand(mtd, chip, type)) goto ident_done; } else if (*dev_id == type->dev_id) { break; @@ -4483,9 +4483,9 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, if (!type->pagesize) { /* Decode parameters from extended ID */ - nand_decode_ext_id(mtd, chip, id_data); + nand_decode_ext_id(mtd, chip); } else { - nand_decode_id(mtd, chip, type, id_data); + nand_decode_id(mtd, chip, type); } /* Get chip options */ @@ -4523,7 +4523,7 @@ ident_done: return ERR_PTR(-EINVAL); } - nand_decode_bbm_options(mtd, chip, id_data); + nand_decode_bbm_options(mtd, chip); /* Calculate the address shift from the page size */ chip->page_shift = ffs(mtd->writesize) - 1; diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 3417ca2a0d2e..f2c6a978cbf8 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -507,6 +507,19 @@ static inline void nand_hw_control_init(struct nand_hw_control *nfc) init_waitqueue_head(&nfc->wq); } +/* The maximum expected count of bytes in the NAND ID sequence */ +#define NAND_MAX_ID_LEN 8 + +/** + * struct nand_id - NAND id structure + * @data: buffer containing the id bytes. + * @len: ID length. + */ +struct nand_id { + u8 data[NAND_MAX_ID_LEN]; + int len; +}; + /** * struct nand_ecc_step_info - ECC step information of ECC engine * @stepsize: data bytes per ECC step @@ -888,6 +901,8 @@ nand_get_sdr_timings(const struct nand_data_interface *conf) struct nand_chip { struct mtd_info mtd; + struct nand_id id; + void __iomem *IO_ADDR_R; void __iomem *IO_ADDR_W; From patchwork Fri Jul 22 16:09:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2232 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f69.google.com (mail-ed1-f69.google.com [209.85.208.69]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 4F0363F047 for ; Fri, 22 Jul 2022 18:11:12 +0200 (CEST) Received: by mail-ed1-f69.google.com with SMTP id y8-20020a056402358800b0043bcb538b85sf1876694edc.10 for ; Fri, 22 Jul 2022 09:11:12 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1658506272; cv=pass; d=google.com; s=arc-20160816; b=LdYc0ZqtvyFAG71c4DlSQgz/IvlMxEkIXed2oxWeEqpHn7lA/xdh/Hy6n6omcPNBIJ kRdCW4ynzvUhKPYGRqlLxpzZIx/weLbsi1rimNnsRm/pnhjkydtpYc+u/ZPTUJeWAWHs RJf67ToF3zcJ439Wi/vaSXYJV+Z4C8Loa0Hp1hG+zAKZ0kesm5lZ3SLhjlgX5n0AoJTU 1/8bXVT4k6FadmnIyMcXvZbio7CwO3d3DDVGco7RQOhVSIrrsnQHVedQea3B/0xtF2+i /gI4H1UcRl8WT1AtYCUp41nq9CBTncIzmpPbQgJycrIcG8Xdnnqhbbd78eTiRlOa0/X6 h+mg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=m6D7wlV86Y4Eq1a1C1wH1C9fxPM+Xo3qaLWyerbMuX0=; b=HtV7hMSOcG8NXkSzCMdyKS0l4GLtdOzLYr2UY97pWUAPwhl/ZREmnbRpK8RzB2schz //0S3fcQFGHaBfTO11WHiAx/nWif0IhmsoortqQSC7YDD0Kt55wbE5DZ31vrteAf604k IFEJ8jOhPca3gIBxZaX3oTx83l9Thui9Mqu2RPRbMyi38x1drBjO7bv+eoS2nY2Gzn+U wn586t9Sh4Qj/FO1vZLQAlkX7xsrLbXQVsyCw+dbHilPUTA8Y7vDZ03UINwP3uYyokLX H+7hJbfqBU1y5RZrqH1M9lG1hiO/lzSjJnBLRSfKDNjR+kpu9vFW+ZFayyZEHDdacKtN QNqQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=hFljHZBD; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=m6D7wlV86Y4Eq1a1C1wH1C9fxPM+Xo3qaLWyerbMuX0=; b=qU8M/hz6mA4aaJRzsGv7jD6RTgnmPMYC7qCnPv+I0yItdt03yjEfNvxHuli5ZQ2xup ZPs9BpaCB/45qsvjS5JkPeTGgrD6Vtjtvqp+M88IqBIAGtZivlHUmGnenjHVZ6+V8KUu qaBqxOl+s6yatiYFZxm1L2+5nDP2pLnyjaT4E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=m6D7wlV86Y4Eq1a1C1wH1C9fxPM+Xo3qaLWyerbMuX0=; b=1MplmoJ7/f0Bf3AvDMNBwI20QGTDWLFWa0HKpwv9hBPAApxyEf+edAgNej5XL3qf+h mSuyiu8StJ2pUGGjzsB554iIKjkfs0HxE1RzfG0OPRlSR5cCaRvyo1Ezq/d3fBUr0Kpl +HzEUE/FJNqw9b6sGLnm7liF1uEt0rfnuuU46JUTWbAPU9QU0vmRnGv0fuVkvC/Yl5n0 nC/QXht/gP1jyOI3etVbOa34VEITisTHxbygW4oEmAE+RmgKfzyCf5pMX7RctNp2BzO2 ysODCKfMK3PzwzYFP0bG8Y83Ni0WM32i6RctcKqwuN44hhAOWqgbXL3chLfihsq5MRSc RGIA== X-Gm-Message-State: AJIora9uUB10pX4VAxdDUHsCajQFf7zzt9rtVZN+YB/c7n5gEcOeOfXh G60n/OI5/SWs7jMYFcXT6/5R9XX5 X-Google-Smtp-Source: AGRyM1s4Yrn8BbU5ARk4O2mF60+P1hL//T6tQHg9EhaV6z/S3jof9vdD5QyMAETTFw6xmvoe5XUKLQ== X-Received: by 2002:a17:906:ef90:b0:72b:9ce5:f016 with SMTP id ze16-20020a170906ef9000b0072b9ce5f016mr452287ejb.697.1658506271986; Fri, 22 Jul 2022 09:11:11 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a05:6402:11cb:b0:43a:7c1c:8981 with SMTP id j11-20020a05640211cb00b0043a7c1c8981ls2106758edw.0.-pod-prod-gmail; Fri, 22 Jul 2022 09:11:11 -0700 (PDT) X-Received: by 2002:a50:cdc2:0:b0:43b:bb93:3a5f with SMTP id h2-20020a50cdc2000000b0043bbb933a5fmr632046edj.122.1658506270856; Fri, 22 Jul 2022 09:11:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1658506270; cv=none; d=google.com; s=arc-20160816; b=QbW1cZZaFO83douq5S17zXFCiWi0sQTHsfrxR+/MCWeU4sQPDsvj+7kpj7yTGFOgLx JtSDYydYK46vUSDS8bPXGtFPrYHsBGJlLwi3+FrL6qPM2RFaGDTgGBSIcBqQLx/RIITb 2wftCUIVbaLV+dNyZKUGMphSSLxDgqVyKlenkpauG4Qm8ZJ388Z9squXIeg2yUtzddXC nKgLM9eXCfaQD0llDg0H2rb+1A/8e4wTAkRLTV//E/+uJ6fnjN1UbFewDZjxRxWd5bod PkQ8A0ebUh+3e2o4r7w5+syUMUj6Jqk56mjiy3xWHisgx36mgAdqY7ETjOJAdse16zIK 6j6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=aNS64cmA9ulz6/dS+EH0hp8jY3RUzbjM0jzsDFdJ4xs=; b=WPyW9/H7W/vHVvEFMLjHak4hlr31EAw73Cvj1Iw72DW5f+qg/TdwPswdURy8FIH7yr iE46aYk1Gc8gk7bMsPuLpuIGpeeWBmVfgjmGkrsIyC5fGwpCR3C3m4UWmZi0dZKnHMpt P7qiye0uc3Y1NQA1m3F6Oxzr7aAbXQG4pP7AHRiCsmovG3x1eoXEfYE54Ck3pqam4nWQ kwwbUvk0GknAfzos+bkpSpYITe/ScZeH1cYtmZA9sTvK9JeslaYjBYM4Seonqj+dWhRt QHdLavy46YFx9/ujzR+TSQ99VcNt5IE8+ea5hiInm4nXv85oMcEKr+RluvNaXNexIG9c 4UEA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=hFljHZBD; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id os20-20020a170906af7400b006fe8bef9830sor2095776ejb.108.2022.07.22.09.11.10 for (Google Transport Security); Fri, 22 Jul 2022 09:11:10 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:907:94d0:b0:72f:269c:3aa3 with SMTP id dn16-20020a17090794d000b0072f269c3aa3mr443029ejc.695.1658506270456; Fri, 22 Jul 2022 09:11:10 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.pdxnet.pdxeng.ch (host-87-14-98-67.retail.telecomitalia.it. [87.14.98.67]) by smtp.gmail.com with ESMTPSA id d19-20020a170906305300b006fe8ac6bc69sm2174025ejd.140.2022.07.22.09.11.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Jul 2022 09:11:09 -0700 (PDT) From: Dario Binacchi To: u-boot@lists.denx.de Cc: Amarula patchwork , michael@amarulasolutions.com, Dario Binacchi , Patrice Chotard , Simon Glass , Wolfgang Denk Subject: [PATCH v4 03/14] mtd: nand: Add manufacturer specific initialization/detection steps Date: Fri, 22 Jul 2022 18:09:57 +0200 Message-Id: <20220722161009.2686504-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220722161009.2686504-1-dario.binacchi@amarulasolutions.com> References: <20220722161009.2686504-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=hFljHZBD; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Michael Trimarchi Upstream linux commit abbe26d144ec22. A lot of NANDs are implementing generic features in a non-generic way, or are providing advanced auto-detection logic where the NAND ID bytes meaning changes with the NAND generation. Providing this vendor specific initialization step will allow us to get rid of full-id entries in the nand_ids table or all the vendor specific cases added over the time in the generic NAND ID decoding logic. Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi --- (no changes since v3) Changes in v3: - Use commit sha1 with 13 digits. - Fix code style warnings raised by patman. Changes in v2: - Use short-commit form. - Remove linux info. Uboot seems that backport without add this extra information. drivers/mtd/nand/raw/nand_base.c | 98 ++++++++++++++++++++++++-------- include/linux/mtd/rawnand.h | 30 ++++++++++ 2 files changed, 105 insertions(+), 23 deletions(-) diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 220804c75c87..0900e6dbf9a6 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4286,6 +4286,39 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip) } } +/* + * Manufacturer detection. Only used when the NAND is not ONFI or JEDEC + * compliant and does not have a full-id or legacy-id entry in the nand_ids + * table. + */ +static void nand_manufacturer_detect(struct mtd_info *mtd, struct nand_chip *chip) +{ + /* + * Try manufacturer detection if available and use + * nand_decode_ext_id() otherwise. + */ + if (chip->manufacturer.desc && chip->manufacturer.desc->ops && + chip->manufacturer.desc->ops->detect) + chip->manufacturer.desc->ops->detect(chip); + else + nand_decode_ext_id(mtd, chip); +} + +/* + * Manufacturer initialization. This function is called for all NANDs including + * ONFI and JEDEC compliant ones. + * Manufacturer drivers should put all their specific initialization code in + * their ->init() hook. + */ +static int nand_manufacturer_init(struct nand_chip *chip) +{ + if (!chip->manufacturer.desc || !chip->manufacturer.desc->ops || + !chip->manufacturer.desc->ops->init) + return 0; + + return chip->manufacturer.desc->ops->init(chip); +} + /* * Old devices have chip data hardcoded in the device ID table. nand_decode_id * decodes a matching ID table entry and assigns the MTD size parameters for @@ -4383,6 +4416,26 @@ static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, return false; } +/** + * nand_get_manufacturer_desc - Get manufacturer information from the + * manufacturer ID + * @id: manufacturer ID + * + * Returns a nand_manufacturer_desc object if the manufacturer is defined + * in the NAND manufacturers database, NULL otherwise. + */ +static const struct nand_manufacturers *nand_get_manufacturer_desc(u8 id) +{ + int i; + + for (i = 0; nand_manuf_ids[i].id != 0x0; i++) { + if (nand_manuf_ids[i].id == id) + return &nand_manuf_ids[i]; + } + + return NULL; +} + /* * Get the flash and manufacturer id and lookup if the type is supported. */ @@ -4391,8 +4444,8 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, int *maf_id, int *dev_id, struct nand_flash_dev *type) { + const struct nand_manufacturers *manufacturer_desc; int busw, ret; - int maf_idx; u8 *id_data = chip->id.data; /* @@ -4433,6 +4486,12 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, return ERR_PTR(-ENODEV); } + chip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data)); + + /* Try to identify manufacturer */ + manufacturer_desc = nand_get_manufacturer_desc(*maf_id); + chip->manufacturer.desc = manufacturer_desc; + if (!type) type = nand_flash_ids; @@ -4451,8 +4510,6 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, */ chip->options &= ~NAND_BUSWIDTH_16; - chip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data)); - for (; type->name != NULL; type++) { if (is_full_id_nand(type)) { if (find_full_id_nand(mtd, chip, type)) @@ -4482,8 +4539,7 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, chip->chipsize = (uint64_t)type->chipsize << 20; if (!type->pagesize) { - /* Decode parameters from extended ID */ - nand_decode_ext_id(mtd, chip); + nand_manufacturer_detect(mtd, chip); } else { nand_decode_id(mtd, chip, type); } @@ -4499,12 +4555,6 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, chip->options &= ~NAND_SAMSUNG_LP_OPTIONS; ident_done: - /* Try to identify manufacturer */ - for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) { - if (nand_manuf_ids[maf_idx].id == *maf_id) - break; - } - if (chip->options & NAND_BUSWIDTH_AUTO) { WARN_ON(chip->options & NAND_BUSWIDTH_16); chip->options |= busw; @@ -4516,7 +4566,7 @@ ident_done: */ pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", *maf_id, *dev_id); - pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name); + pr_info("%s %s\n", manufacturer_desc->name, mtd->name); pr_warn("bus width %d instead %d bit\n", (chip->options & NAND_BUSWIDTH_16) ? 16 : 8, busw ? 16 : 8); @@ -4549,28 +4599,30 @@ ident_done: if (mtd->writesize > 512 && chip->cmdfunc == nand_command) chip->cmdfunc = nand_command_lp; + ret = nand_manufacturer_init(chip); + if (ret) + return ERR_PTR(ret); + pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", *maf_id, *dev_id); #ifdef CONFIG_SYS_NAND_ONFI_DETECTION if (chip->onfi_version) - pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, - chip->onfi_params.model); + pr_info("%s %s\n", manufacturer_desc->name, + chip->onfi_params.model); else if (chip->jedec_version) - pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, - chip->jedec_params.model); + pr_info("%s %s\n", manufacturer_desc->name, + chip->jedec_params.model); else - pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, - type->name); + pr_info("%s %s\n", manufacturer_desc->name, type->name); #else if (chip->jedec_version) - pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, - chip->jedec_params.model); + pr_info("%s %s\n", manufacturer_desc->name, + chip->jedec_params.model); else - pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, - type->name); + pr_info("%s %s\n", manufacturer_desc->name, type->name); - pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, + pr_info("%s %s\n", manufacturer_desc->name, type->name); #endif diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index f2c6a978cbf8..57fe7fb47bd8 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -796,6 +796,17 @@ nand_get_sdr_timings(const struct nand_data_interface *conf) return &conf->timings.sdr; } +/** + * struct nand_manufacturer_ops - NAND Manufacturer operations + * @detect: detect the NAND memory organization and capabilities + * @init: initialize all vendor specific fields (like the ->read_retry() + * implementation) if any. + */ +struct nand_manufacturer_ops { + void (*detect)(struct nand_chip *chip); + int (*init)(struct nand_chip *chip); +}; + /** * struct nand_chip - NAND Private Flash Chip Data * @mtd: MTD device registered to the MTD framework @@ -897,6 +908,7 @@ nand_get_sdr_timings(const struct nand_data_interface *conf) * devices. * @priv: [OPTIONAL] pointer to private chip data * @write_page: [REPLACEABLE] High-level page write function + * @manufacturer: [INTERN] Contains manufacturer information */ struct nand_chip { @@ -983,6 +995,11 @@ struct nand_chip { struct nand_bbt_descr *badblock_pattern; void *priv; + + struct { + const struct nand_manufacturers *desc; + void *priv; + } manufacturer; }; static inline void nand_set_flash_node(struct nand_chip *chip, @@ -1016,6 +1033,17 @@ static inline void nand_set_controller_data(struct nand_chip *chip, void *priv) chip->priv = priv; } +static inline void nand_set_manufacturer_data(struct nand_chip *chip, + void *priv) +{ + chip->manufacturer.priv = priv; +} + +static inline void *nand_get_manufacturer_data(struct nand_chip *chip) +{ + return chip->manufacturer.priv; +} + /* * NAND Flash Manufacturer ID Codes */ @@ -1120,10 +1148,12 @@ struct nand_flash_dev { * struct nand_manufacturers - NAND Flash Manufacturer ID Structure * @name: Manufacturer name * @id: manufacturer ID code of device. + * @ops: manufacturer operations */ struct nand_manufacturers { int id; char *name; + const struct nand_manufacturer_ops *ops; }; extern struct nand_flash_dev nand_flash_ids[]; From patchwork Fri Jul 22 16:09:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2233 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f71.google.com (mail-ed1-f71.google.com [209.85.208.71]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 636EA3F047 for ; Fri, 22 Jul 2022 18:11:13 +0200 (CEST) Received: by mail-ed1-f71.google.com with SMTP id g7-20020a056402424700b0043ac55ccf15sf3117593edb.4 for ; Fri, 22 Jul 2022 09:11:13 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1658506273; cv=pass; d=google.com; s=arc-20160816; b=0mzrRDyxP5E7MfCl1wn3sfSnVBb/Iws03a8Aj/fcjtsjZEpS1h/B9Q63pDX0nReodR xp+VP++4NmPVA4YDnLNkQ5HkRqh01RVf3PNmTZLAaEPAE1SXrsehaT53zz9P9CS2iLZ1 h8uxP64kKZBgT3HRZWVm9dYhXDc/mEdxp2oLX1Irl+R7MPjCOZg9bmo/BAH+wTOu7s66 tya4eOGTLvQ8xLu3Q3Piald9ELJmRWxXIzTCFuCUlRf0FDZTvSq+195rZ43y/UPwCX7W L1oWkfqXttvW/8MMpDhult+Gqmna6zxgdzSeuSPmIxLP49OyFZbnK54NgTPzcWv2ZFyD sVOQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=qqn5TwzDTjpb7SSrGiArlPPhjdSCq1sbLToKhMgACKs=; b=LGXA+ES12P4b2G+mcIBxZRUpy2u+ERsUlwKR/frueCKaOvAjBmbUFfs/SVNapcbV9g nQvx5RDKazaRt/cEJ8osR9uq+c0uF9G9M3K9k6MVN+WdxkFyM3G4R7+DApebRY0GdLp7 UjWp1f8RzQXI5xb/RdBLguPEcY5lNsqULHqAU5X9npHDsZ1jH9bQA3Q2pAZZvitgM6mO 24ByTYtWxbjnlV6zSpkY1KAm0b1wRO8haaqrGf+QYSbhJCltkMMqVTz08TOn5EI1eOGj 1+2IuKSM991sllmhBsuJ4I18woXdIG62QqRNi6hEvvopm4V7DUBIcNjfOtG05m3Fo6LV wM+Q== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=NjuBctze; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=qqn5TwzDTjpb7SSrGiArlPPhjdSCq1sbLToKhMgACKs=; b=PD4lXujOXs2utR499bBk0xlM4v+WraUmIbBBqmKEffkQy2D47cRLNr1JY+Lg2NXk1q bZ7AN5gJv2AtnMjROinuC3SklHPiusTj8shlEBeidcbVW5UghmcTFQZPHF5DJ3EFq7Mq MditD5OZmTnOcmkeCYubL5qvM3qSYGhwp1x7s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=qqn5TwzDTjpb7SSrGiArlPPhjdSCq1sbLToKhMgACKs=; b=T/ZCG1nc7JhqGFWiNAJhdkIaVeCCnyU1gHhb5U4QOoXcX/eTpOf0x5+6ppZjK9vKQy 4vBMgiv/vSPQhPcU/eRBDmwx3d76yXuyKjO2U4VN8ksAH2jI5m8FwbAn8tJmNA1GScZY dScGWiNoIinhrUJr0ZSznTy/Db59/DIEVtQ1x0up+huLR85Hb7F6zDEznV0HaWY3K8dF WRi5UzsTUk5PvMFCYsAoe+SxNQc4H7bcIzLv/d9M58zThc6dC15PCe9uvEmfCPosHJRY 8jw7fQOiY65MgmXUw+UPrFxAM2fDdBe4/fVWWfNWr9dLfRXcKqrBFz74MqB3nhl5ZTv0 Gqhg== X-Gm-Message-State: AJIora/VvDifCiHP1h7Kge2w9R8oSqxtSyZGw9W1LGuUZG7ORpONPiA7 hYLfxvPwqd3gPbSYKOZIwyFS4KS1 X-Google-Smtp-Source: AGRyM1uSY8BFqPt8HZDchBHqXlgplWsDyxPPuXKNDiZjVd9/yKa56Yl57tTqzI/MGXLA9+FFZVKIvA== X-Received: by 2002:a17:907:3da0:b0:72b:47df:c1d7 with SMTP id he32-20020a1709073da000b0072b47dfc1d7mr495005ejc.214.1658506273221; Fri, 22 Jul 2022 09:11:13 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a50:d0c9:0:b0:43a:6e16:5059 with SMTP id g9-20020a50d0c9000000b0043a6e165059ls2107193edf.2.-pod-prod-gmail; Fri, 22 Jul 2022 09:11:12 -0700 (PDT) X-Received: by 2002:a05:6402:5192:b0:43b:d728:d2aa with SMTP id q18-20020a056402519200b0043bd728d2aamr582211edd.185.1658506272000; Fri, 22 Jul 2022 09:11:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1658506271; cv=none; d=google.com; s=arc-20160816; b=WOzXWd18eoj3qzsbnZn5S4QjOU1wg4IgQ4uCDPiHuvFk7wpGfS/TWDWim6pC431KSF OEne4UUIzxqB2DnyUpBgKK49xIFm1zSnwwBxdaU3a9Mw3P+TeJZyHaB5QHtGFo83YwMo zYgK6v2oHWAQ5x1ukxM4Kqcb+CevZ6Rz4InJpzXrxS5OTRFhypky9c8G32xCqbFIE/lB tW26tWKx6/x1Vl3M1wRfyatgYfz5h4ohm118piGZPMPPrGGNk22fDowJBB2g2efV6Jty kioB7t+IlGLkdw0fdfJYOvn7Glpvwwh83Eif3s+gYAiHDAPMWDHqoYxlGp6dD4ZnPtHY 2R1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=g1evLi2ic43/8RVgZGntz7H3u7Oa+xL7kn1fzGahP18=; b=yFwGquAWe1bfqLHwuC9w6oDwy5toQ5PpIF1Dse4Y02KDkg9c6AwS25hA83zICfPiLc 8VIX7qHOh/NJUQN0dztLG7nPE6EGaZPAjzyZieQ20hKkzdirXhMHqOit5oA6HHj8Q8LL 4JtuVDvIdWZYmZZ7tbXcn9vDk4X9avkwm0Rll1nh66OKhYZ/7OSL2ZoEKfaajIM1YjZk 9958t4Ir3UMoHKp8/iy9qPiWAg7Kq105vnG/nAGHzujV+ybAbQUKNu7y7+uEyrK0qpqL dGtM6yJiFikmNsaldanz/J846RIwZAFJR/D5+vcz/6n3qyti/ejlGiwMLGSWD0jJfGof TpBg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=NjuBctze; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id kv23-20020a17090778d700b00722e1ac3ee8sor2115699ejc.110.2022.07.22.09.11.11 for (Google Transport Security); Fri, 22 Jul 2022 09:11:11 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:907:60c7:b0:72b:5651:e1f8 with SMTP id hv7-20020a17090760c700b0072b5651e1f8mr464639ejc.375.1658506271719; Fri, 22 Jul 2022 09:11:11 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.pdxnet.pdxeng.ch (host-87-14-98-67.retail.telecomitalia.it. [87.14.98.67]) by smtp.gmail.com with ESMTPSA id d19-20020a170906305300b006fe8ac6bc69sm2174025ejd.140.2022.07.22.09.11.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Jul 2022 09:11:11 -0700 (PDT) From: Dario Binacchi To: u-boot@lists.denx.de Cc: Amarula patchwork , michael@amarulasolutions.com, Dario Binacchi , Patrice Chotard , Simon Glass , Wolfgang Denk Subject: [PATCH v4 04/14] mtd: nand: Get rid of mtd variable in function calls Date: Fri, 22 Jul 2022 18:09:58 +0200 Message-Id: <20220722161009.2686504-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220722161009.2686504-1-dario.binacchi@amarulasolutions.com> References: <20220722161009.2686504-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=NjuBctze; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Michael Trimarchi chip points to mtd. Passing chip is enough to have a reference to mtd when is necessary Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi --- (no changes since v3) Changes in v3: - Fix code style warnings raised by patman. drivers/mtd/nand/raw/nand_base.c | 25 +++++++++++++------------ include/linux/mtd/rawnand.h | 3 +-- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 0900e6dbf9a6..145de22be852 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4160,8 +4160,9 @@ static int nand_get_bits_per_cell(u8 cellinfo) * chip. The rest of the parameters must be decoded according to generic or * manufacturer-specific "extended ID" decoding patterns. */ -static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip) +static void nand_decode_ext_id(struct nand_chip *chip) { + struct mtd_info *mtd = &chip->mtd; int extid, id_len; /* The 3rd id byte holds MLC / multichip data */ chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]); @@ -4291,7 +4292,7 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip) * compliant and does not have a full-id or legacy-id entry in the nand_ids * table. */ -static void nand_manufacturer_detect(struct mtd_info *mtd, struct nand_chip *chip) +static void nand_manufacturer_detect(struct nand_chip *chip) { /* * Try manufacturer detection if available and use @@ -4301,7 +4302,7 @@ static void nand_manufacturer_detect(struct mtd_info *mtd, struct nand_chip *chi chip->manufacturer.desc->ops->detect) chip->manufacturer.desc->ops->detect(chip); else - nand_decode_ext_id(mtd, chip); + nand_decode_ext_id(chip); } /* @@ -4324,9 +4325,9 @@ static int nand_manufacturer_init(struct nand_chip *chip) * decodes a matching ID table entry and assigns the MTD size parameters for * the chip. */ -static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, - struct nand_flash_dev *type) +static void nand_decode_id(struct nand_chip *chip, struct nand_flash_dev *type) { + struct mtd_info *mtd = &chip->mtd; int maf_id = chip->id.data[0]; mtd->erasesize = type->erasesize; @@ -4439,11 +4440,11 @@ static const struct nand_manufacturers *nand_get_manufacturer_desc(u8 id) /* * Get the flash and manufacturer id and lookup if the type is supported. */ -struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, - struct nand_chip *chip, - int *maf_id, int *dev_id, - struct nand_flash_dev *type) +struct nand_flash_dev *nand_get_flash_type(struct nand_chip *chip, int *maf_id, + int *dev_id, + struct nand_flash_dev *type) { + struct mtd_info *mtd = &chip->mtd; const struct nand_manufacturers *manufacturer_desc; int busw, ret; u8 *id_data = chip->id.data; @@ -4539,9 +4540,9 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, chip->chipsize = (uint64_t)type->chipsize << 20; if (!type->pagesize) { - nand_manufacturer_detect(mtd, chip); + nand_manufacturer_detect(chip); } else { - nand_decode_id(mtd, chip, type); + nand_decode_id(chip, type); } /* Get chip options */ @@ -4729,7 +4730,7 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips, nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16); /* Read the flash type */ - type = nand_get_flash_type(mtd, chip, &nand_maf_id, + type = nand_get_flash_type(chip, &nand_maf_id, &nand_dev_id, table); if (IS_ERR(type)) { diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 57fe7fb47bd8..d8141cb4d114 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -29,8 +29,7 @@ struct nand_flash_dev; struct device_node; /* Get the flash and manufacturer id and lookup if the type is supported. */ -struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, - struct nand_chip *chip, +struct nand_flash_dev *nand_get_flash_type(struct nand_chip *chip, int *maf_id, int *dev_id, struct nand_flash_dev *type); From patchwork Fri Jul 22 16:09:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2234 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f69.google.com (mail-ed1-f69.google.com [209.85.208.69]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 67F603F047 for ; Fri, 22 Jul 2022 18:11:14 +0200 (CEST) Received: by mail-ed1-f69.google.com with SMTP id y8-20020a056402358800b0043bcb538b85sf1876732edc.10 for ; Fri, 22 Jul 2022 09:11:14 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1658506274; cv=pass; d=google.com; s=arc-20160816; b=xJf59WWAa7orX7WK6CCJJIPgG7oSj/wS+eUzs9AQ3gwu7+cHu47Z/OSnoJt1KmeHFa 5EXu9+zFFI6RTAkvKFNzWJHwJtl+M4GN1/Biv6Bc4ToaH/pMk/idI5CPmesEZ71kA0ku NbWVOiuAhrMlR+1BqiNz9A7cng7M/5V9zo8AoCRAMDgNgKYYm/kUdRU7LR3+AUZBS3RX eRJHDrbRBaDV7tt7+qU9oJOKWDxvMdvaZKBazfI4lwdnXvEbszGwYA5qYsZO1+cvqvu7 ys0I5onlY0wZYfm2jEM9fiDA3pvA5LwmUPfiSvc2Ac5L4D1j9Wz4Z2JnKTcMs9VOzddK PnYA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=WdcYbpvc3Joc6Nr4Sk2cwsecjAtxdl0NTX1y430B5bY=; b=cq0r7Yx2oUREmtEE1+t2QWfMU9ZD/1xpANaXVZ9IfPFl262zQdxGoD+aBB/4/ZrUQH QvKr6cwmQCnbIAGzdQ40F4yNqqvqi4D69lcpwukdQAgWY2PT6zo1PaEvKG2Wwlh+BNCA bSXlFpX3AcUE+6Bw0AvVrwgdjd38aOGDiMujlY6Ro55CjN9JeeGC7n4IN1e+3VdYzaGd MyQkoj7dCqlMvX4bWMW3I/2qkV8bH9aTdM1BlQ/0BCooEnOfT6g2JgeMandaaTTRjYWe ZPhWFR/cwiA8Dr4A+RjQcyulBEX6nBINtfq6zSMrc1am+izSwYfOKpW158tSI1lOiLY6 km7w== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=TTl468oM; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=WdcYbpvc3Joc6Nr4Sk2cwsecjAtxdl0NTX1y430B5bY=; b=VUZf4XBxIs7BmfMcv+A9x1P4V0dK12f9Oih3TO9v/RdmSb3kZs3w5OLMgYy+BD13RX +L64m4DImZOAg40q8k2t087kDncFYQM3t8mlQW52zXmhH6WIGALCZ/H7ER4c/Jc73epF ajLxyxnt/oeqKa4CNAVNZY9YcZzoO56Z/Vvug= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=WdcYbpvc3Joc6Nr4Sk2cwsecjAtxdl0NTX1y430B5bY=; b=HNQW4UmG8L2AX3Wg/rpOANZFyolrQFZ0TaK4PX4M0/FVdgxPLoXkHADGOptvNe+3NR 9xgl+d1zmjgBZusuvA7wRxUSOb+pjdPGCf99rRzIFPpugVBykngP5e9UIw22isJgnG5z hlCrurL3b+S93+rx7V0jWqWWlGXtNolVcxWM8ir48Ti5S0xQth2gdxMyfEhFeYnLQ1aK RQiRk6PSCjfhfOOJFgWfK2Y5iEEKtZUQREqFCAgcBmMDqWhhgmIwZzZnw1r0hzoHklON sxPEWvK0Ymiz8IS5KOoMgtQH/TQY5y8hv0vEOR3M+kac22jKlbcIEStv0sqsew90Rf89 oahA== X-Gm-Message-State: AJIora8eUtVK4wvc66wVtnf52aeHXtheqo42rD74braNJDBLqI0lev1h G+Q13kmTVpZfwWBjikAKiP1WCrpb X-Google-Smtp-Source: AGRyM1v0lJ+ddfDdobB1H2hXlgJuPMm8mt46r4uXEb3NWATgDEm2GN64NyRKnLcmBCAcySxrzCiR/g== X-Received: by 2002:a05:6402:270d:b0:43a:d1e8:460b with SMTP id y13-20020a056402270d00b0043ad1e8460bmr652075edd.40.1658506274311; Fri, 22 Jul 2022 09:11:14 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a05:6402:11cb:b0:43a:7c1c:8981 with SMTP id j11-20020a05640211cb00b0043a7c1c8981ls2106828edw.0.-pod-prod-gmail; Fri, 22 Jul 2022 09:11:13 -0700 (PDT) X-Received: by 2002:a05:6402:e93:b0:43b:6a49:7e88 with SMTP id h19-20020a0564020e9300b0043b6a497e88mr644098eda.132.1658506273293; Fri, 22 Jul 2022 09:11:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1658506273; cv=none; d=google.com; s=arc-20160816; b=YSMydVbIIYjo1sSQy+g0/Fc5vK2IciYdIkPaCEqeeD2JERUiei7LoFrbFNub2x2LeT 3oRCEnxwEPCD6ozs3/szx1TAaHWaWjYW31ZTCsnO3k7C7bPLG218wqE6GeqKaDG+gDm1 77yNGwEbMogW8WQ6KYEsgWxGno3AlIpJkWwiYvQjwcQNrsDAndnWGDramUlxL1UVs6cv mGoIIaA/Iq1N1GVaj8CngWbCKTrE4a+eC8UDsedeuE7yoam8isgWMp3HHuRBHV1B9V6Q 359F9Rsi/ZUUcI441ZL6iTi3OyyGtyS+LF/lo85bJz63OQTGncBC2JnG4tiqoMSTSs5k BP6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=HG7NUDdxnSS97U4P5z2f21LFtdOJS/jfnwSZbkpZ31A=; b=MdD/o2t14/+YDGLvZPdJUaKc0kjOvYGlgJ8UpnmUfYZ2iSbnnY1WuLYlRCOo4h4E26 EUYWTUE2dEr6HRRNjzOsyiisKSJm0pVmps/ddTr59B32j9Ze6UJ+rqOyZmyximKfiNOc aMZlvai6vn4Hm/Z0+al7cgeNrbh3wMj7w7u/w5sjsJE+cStnOiZplmXfVKY75nojVrtI IyNiPAoRsX26rKXMVurKTT/6zQR1O2Of27KCJsU0he6atn3nogWGaK8qHmk2T3KpTaMd Sf2C96+8w3K92AduBh1AlAKmmiMLb5Sac4gXOopn2Fy5TSMmgJo+7Y3bIHl3jM772Oy7 REUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=TTl468oM; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id f10-20020a170906138a00b0072b1491d92bsor2096357ejc.3.2022.07.22.09.11.13 for (Google Transport Security); Fri, 22 Jul 2022 09:11:13 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:907:9608:b0:72f:4b13:c66c with SMTP id gb8-20020a170907960800b0072f4b13c66cmr456301ejc.531.1658506272946; Fri, 22 Jul 2022 09:11:12 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.pdxnet.pdxeng.ch (host-87-14-98-67.retail.telecomitalia.it. [87.14.98.67]) by smtp.gmail.com with ESMTPSA id d19-20020a170906305300b006fe8ac6bc69sm2174025ejd.140.2022.07.22.09.11.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Jul 2022 09:11:12 -0700 (PDT) From: Dario Binacchi To: u-boot@lists.denx.de Cc: Amarula patchwork , michael@amarulasolutions.com, Dario Binacchi , GSS_MTK_Uboot_upstream , Weijie Gao Subject: [PATCH v4 05/14] mtd: nand: Fix MediaTek MT7621 SoC build Date: Fri, 22 Jul 2022 18:09:59 +0200 Message-Id: <20220722161009.2686504-6-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220722161009.2686504-1-dario.binacchi@amarulasolutions.com> References: <20220722161009.2686504-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=TTl468oM; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Michael Trimarchi nand_get_flash_type was reworked in commit 1ca6f9483e9ab5. This change break the Mediatek MT721. Fix it adjust the function call parameters +include/linux/mtd/rawnand.h:32:62: note: expected 'struct nand_chip *' but argument is of type 'struct mtd_info *' + 32 | struct nand_flash_dev *nand_get_flash_type(struct nand_chip *chip, + | ~~~~~~~~~~~~~~~~~~^~~~ +drivers/mtd/nand/raw/mt7621_nand.c:1189:48: error: passing argument 2 of 'nand_get_flash_type' from incompatible pointer type [-Werror=incompatible-pointer-types] + | ^~~~ + | | + | struct nand_chip * +include/linux/mtd/rawnand.h:33:49: note: expected 'int *' but argument is of type 'struct nand_chip *' + 33 | int *maf_id, int *dev_id, Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi Reviewed-by: Weijie Gao --- Changes in v4: - Add the patch to the series. drivers/mtd/nand/raw/mt7621_nand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/mt7621_nand.c b/drivers/mtd/nand/raw/mt7621_nand.c index 2fd89349392b..9763ae6dc51a 100644 --- a/drivers/mtd/nand/raw/mt7621_nand.c +++ b/drivers/mtd/nand/raw/mt7621_nand.c @@ -1186,7 +1186,7 @@ int mt7621_nfc_spl_post_init(struct mt7621_nfc *nfc) int nand_maf_id, nand_dev_id; struct nand_flash_dev *type; - type = nand_get_flash_type(&nand->mtd, nand, &nand_maf_id, + type = nand_get_flash_type(nand, &nand_maf_id, &nand_dev_id, NULL); if (IS_ERR(type)) From patchwork Fri Jul 22 16:10:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2235 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f71.google.com (mail-ed1-f71.google.com [209.85.208.71]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id AAE1B3F047 for ; Fri, 22 Jul 2022 18:11:15 +0200 (CEST) Received: by mail-ed1-f71.google.com with SMTP id v9-20020a056402348900b0043bcd680e50sf1689619edc.18 for ; Fri, 22 Jul 2022 09:11:15 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1658506275; cv=pass; d=google.com; s=arc-20160816; b=zllEJ6lqvU5VEbZyNKL40Xm9pc3MsLeMd+FaeDucksZ1nKalb3uRWLfTKyw+DxGwMO Stw5Ef53gnUy5GJFHZnisj7BsmtTSXnV2vwK6EnIP5TPajo0mYLxTbTH8atg1nZbzhdJ MntAXISGJbPa5pLJX2sQ8ro0d6Oc0tLYLrn0FFyap6XjyJ+/534kZvVmgY/SNgMuVsBN bIB+YidnpQAqxBAa0ks6EjmfNmVHTysOzVAJ2O8zOCfTgBBIPEP2VSfKOuVFkLp/0q82 T3lDwvbxdc7XBiAHawR0sYuNayOVmvJYTBFYg4i9TDsQ7IsG+bg4dQLoDAWZgVptEep3 Gj/g== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Mx4WhDoVE9eDaatrUeXtmIleNQy27p8J6+NyWVgG2ZE=; b=HihgGNo8orMikanAS1q1yJiAydQ5lswAxxO9BSrRQpSoWRvOs6mb9RIb2ij5przxDf AlaSeDYefETTMz/Z7+L+vKVMLLv25qNHZuf589RgAef8uiwR3LgYNB62HQ9I5uFbaXNB 1DlB0tCqChDDTdaEzA5eO7pxNvMOkq7qwcNZn3furGQn2pbij2rU6YdDG0jtbZQ/RR/R i7dhZzdAgjd2Cu/KjiHVUHDfpYBHeYPNWg/6Jq8fVpFgVQjNNEzFHcz0dfCNXrh8xdjW IryCU+HxZVCUF6wE1D6gWSH43mZudaYR/K67mkyiXnbZa7bobwYQF1eldIkZJg6cmJcj Ev2Q== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=JCpHs0nO; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=Mx4WhDoVE9eDaatrUeXtmIleNQy27p8J6+NyWVgG2ZE=; b=IQGg4aYTJ6vlMJ1eDTtwMZnvEYBm/S4m1bWUyXYiLMCRDcWfAk/CHPg0u55I+wXrs0 YKMWh6HsJG0WY5Jqc4kk4SN2E7mfJa19mXH47Qe/bKNq5Qi/3eHCHozbY51gqdnirq+z DXSRQAKMAl7XRcB3YQE4Pck6bRI9h5rK2NZsE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=Mx4WhDoVE9eDaatrUeXtmIleNQy27p8J6+NyWVgG2ZE=; b=TuGZiCiMb8rnSTDJMSmQ7FJmGCQAsepsitDtB/+ZQDfORJvqyw3Z/ZsndOiqqIX9qm x0sNoqQYh741kjId0YAabluPodrXbBw8KfluHC5OesNw+J1UeMmhlv3UAb0B1gpf+qSa 9l96720ctUu+upMOMkiib42bswCM6Cp+ofg0+h3cSSiYuWe8YwAvMDEhqfH/0z5Kq5/7 P8hGGeEfniRIsdUsqugzK3Ler1OVvb8K8TTdtrVE/fJI1mXwOv/ZxIaIkC7UuzYlrkL7 oDNLcRt/NmCx78PH0FBRBNk2Q3e5FyA7btJqcHhnTnJpbVuA9YwFQih/1bCZO5QOGvxA OKlQ== X-Gm-Message-State: AJIora//t7ustWiyMMSzwLCs+S+2Ee+G06ObqNSM3SUhRINPDkhTUWmG 6uniIUHpxIca6X8Hapj9cdSdrAuo X-Google-Smtp-Source: AGRyM1vUxIdUEvPROyfPN9t39NE4ggMOyoOrHLkWBK8TKTAnNGrdrWr5XsHabbyFjZoXeLOZJHzXBg== X-Received: by 2002:a17:907:7617:b0:72b:49fe:fdf7 with SMTP id jx23-20020a170907761700b0072b49fefdf7mr499990ejc.25.1658506275476; Fri, 22 Jul 2022 09:11:15 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a05:6402:11cb:b0:43a:7c1c:8981 with SMTP id j11-20020a05640211cb00b0043a7c1c8981ls2106863edw.0.-pod-prod-gmail; Fri, 22 Jul 2022 09:11:14 -0700 (PDT) X-Received: by 2002:a05:6402:3047:b0:43a:9e43:95e5 with SMTP id bs7-20020a056402304700b0043a9e4395e5mr558500edb.385.1658506274534; Fri, 22 Jul 2022 09:11:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1658506274; cv=none; d=google.com; s=arc-20160816; b=GT8KQKTfBM+pLmGuonUj0ZOrFxjS+xN9o2SwcV586ZPDSbHOrcqzDLcxpvBACsvoQk F7jXvQpfxJvSKBXdVbJTdPOKMX3gj04GOda7oAt7w2MDBSzKkFCiej3bcrFy3VZS8U+5 00dNpL1LOzCwCe+xzcCCYOvRDvZMdsxdv6QhMsLjwnX3u2SOrmTCaLITCiFVp8Jk5Pbf VWPWnRfvE/e1vTjzhEGR1LOtb0j5D86TIm91tGLgrBVw+W9TvdEwMyVZ6wPvFwyYq6qK 6tER0HXKEMQRpe+vL0jmHYiwZ+7cPYm0p+PNndyM1xUesWmItJDLrUNNFVZG3xaQl9XO uaPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=PqkGaZHSNiv+wfu/yU2ktE6N+nN1VwOJ0uXBw8IizDw=; b=HM9lLt11/2Jd2LEOjM4eQSj05sJ09eZT7roCdYeF3v3aOFBHym0dnsqrSHb+iTeRLO uok5kS8Z6Ybo1UjMmInRD3o7fBDfiLC73+7I1zE268Y44STjHpVmT9VKuXOI2oixzv32 iMjeU+pRCDhjuqU6gfKLy9X4+AUbbZ7K6QHlTvr9mSA3NF3PCyIwxbtu4iSRKJn/yAXH CO50wA5cxYUIMCFJYqxtvl1ILMV/lOztYvH8/y3IVsEWJvvQCRzcVmZNj6g4h1U0FtJb jjJhaCA3nGMYXPFteSMbg8EAZPzz2GksMGxbdCDTLlxciifR4ByX07CmMmdBPzTMhAWh uilA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=JCpHs0nO; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id j5-20020a170906430500b0072a6696313asor2332211ejm.76.2022.07.22.09.11.14 for (Google Transport Security); Fri, 22 Jul 2022 09:11:14 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:906:9751:b0:72f:1b36:e1de with SMTP id o17-20020a170906975100b0072f1b36e1demr479298ejy.451.1658506274266; Fri, 22 Jul 2022 09:11:14 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.pdxnet.pdxeng.ch (host-87-14-98-67.retail.telecomitalia.it. [87.14.98.67]) by smtp.gmail.com with ESMTPSA id d19-20020a170906305300b006fe8ac6bc69sm2174025ejd.140.2022.07.22.09.11.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Jul 2022 09:11:13 -0700 (PDT) From: Dario Binacchi To: u-boot@lists.denx.de Cc: Amarula patchwork , michael@amarulasolutions.com, Dario Binacchi , Patrice Chotard , Simon Glass , Wolfgang Denk Subject: [PATCH v4 06/14] mtd: nand: Export symbol nand_decode_ext_id Date: Fri, 22 Jul 2022 18:10:00 +0200 Message-Id: <20220722161009.2686504-7-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220722161009.2686504-1-dario.binacchi@amarulasolutions.com> References: <20220722161009.2686504-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=JCpHs0nO; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Michael Trimarchi In preparation of moving specific nand support that are not jedec or onfi Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi --- (no changes since v1) drivers/mtd/nand/raw/nand_base.c | 3 ++- include/linux/mtd/rawnand.h | 3 +++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 145de22be852..174c760f3416 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4160,7 +4160,7 @@ static int nand_get_bits_per_cell(u8 cellinfo) * chip. The rest of the parameters must be decoded according to generic or * manufacturer-specific "extended ID" decoding patterns. */ -static void nand_decode_ext_id(struct nand_chip *chip) +void nand_decode_ext_id(struct nand_chip *chip) { struct mtd_info *mtd = &chip->mtd; int extid, id_len; @@ -4286,6 +4286,7 @@ static void nand_decode_ext_id(struct nand_chip *chip) } } +EXPORT_SYMBOL_GPL(nand_decode_ext_id); /* * Manufacturer detection. Only used when the NAND is not ONFI or JEDEC diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index d8141cb4d114..8fb2a43296f5 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -1374,4 +1374,7 @@ int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len, int nand_write_data_op(struct nand_chip *chip, const void *buf, unsigned int len, bool force_8bit); +/* Default extended ID decoding function */ +void nand_decode_ext_id(struct nand_chip *chip); + #endif /* __LINUX_MTD_RAWNAND_H */ From patchwork Fri Jul 22 16:10:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2236 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ej1-f70.google.com (mail-ej1-f70.google.com [209.85.218.70]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 1DBFE3F047 for ; Fri, 22 Jul 2022 18:11:17 +0200 (CEST) Received: by mail-ej1-f70.google.com with SMTP id x2-20020a1709065ac200b006d9b316257fsf2090738ejs.12 for ; Fri, 22 Jul 2022 09:11:17 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1658506277; cv=pass; d=google.com; s=arc-20160816; b=lddP8F+5de8VnGZayOufe3Y9JoOApV8e9boOD0l47/eDVljifaqqU5zYI0H5MxAbr/ XiHhg5zj9MKxRb8dkwH2rwQjJe88611vO2POB+wal6/88pc+vNlxxcQyxgZsKttw0o32 ZbPD/v7rW2fbu4oqVzqk/J1eoiiW1BXTovXyPu0jBnltCLnPn5hbftukBCwbNvslPcrz eRPQBWCTf7t80HCIK5ftkTsXsB8UxOqVQBqyHOEbLqK0AN2b0Punbw+f519cGSO3AacW Cxgb8SiQLftqI5LsVBCHlbSWzA4fFkhAUGuSwMNg5H9hUbIE6dux/WsB/QxGobGP0A+q lyFw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=uuuq6xNIJTC2HxAdBml+msujaQDZLuuTPgkPDc6BuIE=; b=YuNSJmh+y/Ea+d8JuirkAFWW8aOS6iENo72OtFITBHnP0/MFLPvRLmiw3lrGivYpUR lnaU/XJ6NItCM1eBrg6mUaRVFpfESt1w+DJmqehN/kJknictxU4LpHliQv73c5RzVGPk r2aivVAkw57Fmi1gz7BPMNms6BsMEWTg6zKMxbKKPd9RyJaZ7y8mxK1lR+luV3TgfWQO jJpQKH9wvSSDwQhVo5CrQEyED+Io4d9RvIrbK8Q3uU6JBBCoPymoWY1XLVZU30mVcCxd NOyBSJ4dmPAQCJGK9JZBcn7mvLzRjiwYRXwNhHtq2vF+1htHIdrf4YUwtai/cHRrI1wu gUAw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="Jy++8L/M"; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=uuuq6xNIJTC2HxAdBml+msujaQDZLuuTPgkPDc6BuIE=; b=ruSOSdULg542c4bbiyHqOjY1Ew2H7wpbSE9JpagrE1y4l1T1gQ4tWwI2rQIZJ4oQld NaB1b7n/F0HT9qHM3bfJS6aTOawYutdQi1YW/zY++dKkjmx/uaY3doBfuTnOOFc08Ndk UIUuaZIlmkkcX4qQtQS1O7eNEAhtK0/RW6lCs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=uuuq6xNIJTC2HxAdBml+msujaQDZLuuTPgkPDc6BuIE=; b=nkTZG38CTWYkol+rYSZ+rnQXjCR6w3zl8GmhNNs1MRdzw22xdpPdJeW8eHRAofqoIm kkx6rKkNiRJjZFzpsVgZNFYEcYAjdCHXZy5+vv8GYcT7S8OnlSBRtOzE+AaaM7HDMter 4okUqrrfHKmY2l4kcR26ySvNrCmVrkOaASIG/lgtlQILZCNRhLTGvMGiQPSpoA/ckleH 8MyYqKJSD7zj9h0axpNpc/NiF1sor0CvTjsXDhiyZ4o8B8Ruwa+xwDLDsdKreElTH80R 2wVErfYp7mcGDAjJ9U1n7Zgv/eCvTOXT1gWHsYDzR44F/JEiiKUuUXbq/lpDT/8kNUM5 yQYA== X-Gm-Message-State: AJIora+Eb8GPZWV9CtRt0EvVuMBNC1xv0LcCYEofLIzHxN7nvCohePIb EtVrdoZhO7tCp2YQLeskyaljOo22 X-Google-Smtp-Source: AGRyM1t7zW5Aty4TG4Ci/GKoBH6GRPn8C2Ci14GnmrzVTgx4+v2PWNCQH+iaP6ebB0FZqcaJbNc7+A== X-Received: by 2002:a17:907:2d88:b0:72f:5bb:1ee0 with SMTP id gt8-20020a1709072d8800b0072f05bb1ee0mr462331ejc.641.1658506276927; Fri, 22 Jul 2022 09:11:16 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a05:6402:34ce:b0:425:ff69:1a2d with SMTP id w14-20020a05640234ce00b00425ff691a2dls2107307edc.1.-pod-prod-gmail; Fri, 22 Jul 2022 09:11:16 -0700 (PDT) X-Received: by 2002:aa7:c2d1:0:b0:43a:997:c6d8 with SMTP id m17-20020aa7c2d1000000b0043a0997c6d8mr557883edp.161.1658506275896; Fri, 22 Jul 2022 09:11:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1658506275; cv=none; d=google.com; s=arc-20160816; b=il71QrOSpJarnqh0/xja/nEN34/ffkNKJEb5qVwIrlZJlfdwkDQe5SfhX8d4Zn0+IA g9IkJShNDlo8n4Q3OziQHxxp114f+5H+//Nd6XwNZfGduIxoymnY5zIndFQuIIkksYCT zF9duT5gnNyC2xtOo0Ky1M4dvt/QY2mH0etsnrGnS+E+aMggoWAgQau6hJEvNKcH1yF9 PBWqUmNni25gZSqC9EPQyvh8BD73VhPUgDn2WwzFaHiZYY0RSnaBDn7smVMTGUMClbFG UDi0ZMioxdozzl9oxal+2HRHEhf7NP95SSvQX64gCejCcthTkL3Oli5QNjSQmo7mu/EN I6wA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=HB+bOo7QXWBgqSZhIUaTF5Mv/Mrtbb6+knE3GldLnng=; b=EfPwgLhGxhSpV9C2EuzLwJqBxYbRwaQLhiCIktEWqND3cD6XWw7KLGO5bjkBigDET1 fMtpEPX6OvrXBO+rU8GzPrlO17ldbuxRvFf6Foiwd/QJ6d2205e1y0xa0UWa7olZUvW4 5o4RlzKqYVHyit9KumGpUTqAHUjeQBnCAFC+rimcA3/AhV9gNiCekl9povwbEeKGQPeW pXiTEJ3v3b2okfwYkD0olduiVxHrGF76XhM49xHR3I6ypHuu5rJpizTOMty023zMNe4L sau/oSQuuVEecbgXEXrkuX6nAw/h+N/mnskcXxT0G3RIDj7XK9jty0wyPZhVCqdYuvaS VPmw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="Jy++8L/M"; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id vz21-20020a17090704d500b0070f34760164sor2136804ejb.14.2022.07.22.09.11.15 for (Google Transport Security); Fri, 22 Jul 2022 09:11:15 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:906:5a67:b0:72b:610d:4aa4 with SMTP id my39-20020a1709065a6700b0072b610d4aa4mr516098ejc.294.1658506275560; Fri, 22 Jul 2022 09:11:15 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.pdxnet.pdxeng.ch (host-87-14-98-67.retail.telecomitalia.it. [87.14.98.67]) by smtp.gmail.com with ESMTPSA id d19-20020a170906305300b006fe8ac6bc69sm2174025ejd.140.2022.07.22.09.11.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Jul 2022 09:11:15 -0700 (PDT) From: Dario Binacchi To: u-boot@lists.denx.de Cc: Amarula patchwork , michael@amarulasolutions.com, Dario Binacchi , Patrice Chotard , Simon Glass , Wolfgang Denk Subject: [PATCH v4 07/14] mtd: nand: Move Samsung specific init/detection logic in nand_samsung.c Date: Fri, 22 Jul 2022 18:10:01 +0200 Message-Id: <20220722161009.2686504-8-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220722161009.2686504-1-dario.binacchi@amarulasolutions.com> References: <20220722161009.2686504-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="Jy++8L/M"; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Michael Trimarchi Upstream linux commit c51d0ac59f2420. Move Samsung specific initialization and detection logic into nand_samsung.c. This is part of the "separate vendor specific code from core" cleanup process. Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi --- (no changes since v3) Changes in v3: - Use commit sha1 with 13 digits. - Fix code style warnings raised by patman. - Add the SPDX-License-Identifier tag. Changes in v2: - Use short-commit form. - Remove linux info. Uboot seems that backport without add this extra information. - Adjust the include file in nand_samsung. drivers/mtd/nand/raw/Makefile | 3 +- drivers/mtd/nand/raw/nand_base.c | 52 ++--------------- drivers/mtd/nand/raw/nand_ids.c | 4 +- drivers/mtd/nand/raw/nand_samsung.c | 90 +++++++++++++++++++++++++++++ include/linux/mtd/rawnand.h | 2 + 5 files changed, 100 insertions(+), 51 deletions(-) create mode 100644 drivers/mtd/nand/raw/nand_samsung.c diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index f278f31f5cd5..440290bed0fe 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -14,7 +14,7 @@ obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o obj-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o -obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o +obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_samsung.o obj-$(CONFIG_SPL_NAND_IDENT) += nand_ids.o nand_timings.o obj-$(CONFIG_TPL_NAND_INIT) += nand.o ifeq ($(CONFIG_SPL_ENV_SUPPORT),y) @@ -31,6 +31,7 @@ obj-y += nand_ids.o obj-y += nand_util.o obj-y += nand_ecc.o obj-y += nand_base.o +obj-y += nand_samsung.o obj-y += nand_timings.o endif # not spl diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 174c760f3416..fe59157bc3c4 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4173,48 +4173,13 @@ void nand_decode_ext_id(struct nand_chip *chip) /* * Field definitions are in the following datasheets: * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32) - * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44) * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22) * * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung * ID to decide what to do. */ - if (id_len == 6 && chip->id.data[0] == NAND_MFR_SAMSUNG && - !nand_is_slc(chip) && chip->id.data[5] != 0x00) { - /* Calc pagesize */ - mtd->writesize = 2048 << (extid & 0x03); - extid >>= 2; - /* Calc oobsize */ - switch (((extid >> 2) & 0x04) | (extid & 0x03)) { - case 1: - mtd->oobsize = 128; - break; - case 2: - mtd->oobsize = 218; - break; - case 3: - mtd->oobsize = 400; - break; - case 4: - mtd->oobsize = 436; - break; - case 5: - mtd->oobsize = 512; - break; - case 6: - mtd->oobsize = 640; - break; - case 7: - default: /* Other cases are "reserved" (unknown) */ - mtd->oobsize = 1024; - break; - } - extid >>= 2; - /* Calc blocksize */ - mtd->erasesize = (128 * 1024) << - (((extid >> 1) & 0x04) | (extid & 0x03)); - } else if (id_len == 6 && chip->id.data[0] == NAND_MFR_HYNIX && - !nand_is_slc(chip)) { + if (id_len == 6 && chip->id.data[0] == NAND_MFR_HYNIX && + !nand_is_slc(chip)) { unsigned int tmp; /* Calc pagesize */ @@ -4374,13 +4339,10 @@ static void nand_decode_bbm_options(struct mtd_info *mtd, * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba, * AMD/Spansion, and Macronix. All others scan only the first page. */ - if (!nand_is_slc(chip) && - (maf_id == NAND_MFR_SAMSUNG || - maf_id == NAND_MFR_HYNIX)) + if (!nand_is_slc(chip) && maf_id == NAND_MFR_HYNIX) chip->bbt_options |= NAND_BBT_SCANLASTPAGE; else if ((nand_is_slc(chip) && - (maf_id == NAND_MFR_SAMSUNG || - maf_id == NAND_MFR_HYNIX || + (maf_id == NAND_MFR_HYNIX || maf_id == NAND_MFR_TOSHIBA || maf_id == NAND_MFR_AMD || maf_id == NAND_MFR_MACRONIX)) || @@ -4549,12 +4511,6 @@ struct nand_flash_dev *nand_get_flash_type(struct nand_chip *chip, int *maf_id, /* Get chip options */ chip->options |= type->options; - /* - * Check if chip is not a Samsung device. Do not clear the - * options for chips which do not have an extended id. - */ - if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize) - chip->options &= ~NAND_SAMSUNG_LP_OPTIONS; ident_done: if (chip->options & NAND_BUSWIDTH_AUTO) { diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c index 2a50f0b2144c..f4126c3a5a13 100644 --- a/drivers/mtd/nand/raw/nand_ids.c +++ b/drivers/mtd/nand/raw/nand_ids.c @@ -10,7 +10,7 @@ #include #include -#define LP_OPTIONS NAND_SAMSUNG_LP_OPTIONS +#define LP_OPTIONS 0 #define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16) #define SP_OPTIONS NAND_NEED_READRDY @@ -189,7 +189,7 @@ struct nand_flash_dev nand_flash_ids[] = { /* Manufacturer IDs */ struct nand_manufacturers nand_manuf_ids[] = { {NAND_MFR_TOSHIBA, "Toshiba"}, - {NAND_MFR_SAMSUNG, "Samsung"}, + {NAND_MFR_SAMSUNG, "Samsung", &samsung_nand_manuf_ops}, {NAND_MFR_FUJITSU, "Fujitsu"}, {NAND_MFR_NATIONAL, "National"}, {NAND_MFR_RENESAS, "Renesas"}, diff --git a/drivers/mtd/nand/raw/nand_samsung.c b/drivers/mtd/nand/raw/nand_samsung.c new file mode 100644 index 000000000000..0ab80621936f --- /dev/null +++ b/drivers/mtd/nand/raw/nand_samsung.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Free Electrons + * Copyright (C) 2017 NextThing Co + * + * Author: Boris Brezillon + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +static void samsung_nand_decode_id(struct nand_chip *chip) +{ + struct mtd_info *mtd = nand_to_mtd(chip); + + /* New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44) */ + if (chip->id.len == 6 && !nand_is_slc(chip) && + chip->id.data[5] != 0x00) { + u8 extid = chip->id.data[3]; + + /* Get pagesize */ + mtd->writesize = 2048 << (extid & 0x03); + + extid >>= 2; + + /* Get oobsize */ + switch (((extid >> 2) & 0x4) | (extid & 0x3)) { + case 1: + mtd->oobsize = 128; + break; + case 2: + mtd->oobsize = 218; + break; + case 3: + mtd->oobsize = 400; + break; + case 4: + mtd->oobsize = 436; + break; + case 5: + mtd->oobsize = 512; + break; + case 6: + mtd->oobsize = 640; + break; + case 7: + default: /* Other cases are "reserved" (unknown) */ + WARN(1, "Invalid OOB size value"); + mtd->oobsize = 1024; + break; + } + + /* Get blocksize */ + extid >>= 2; + mtd->erasesize = (128 * 1024) << + (((extid >> 1) & 0x04) | (extid & 0x03)); + } else { + nand_decode_ext_id(chip); + } +} + +static int samsung_nand_init(struct nand_chip *chip) +{ + struct mtd_info *mtd = nand_to_mtd(chip); + + if (mtd->writesize > 512) + chip->options |= NAND_SAMSUNG_LP_OPTIONS; + + if (!nand_is_slc(chip)) + chip->bbt_options |= NAND_BBT_SCANLASTPAGE; + else + chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; + + return 0; +} + +const struct nand_manufacturer_ops samsung_nand_manuf_ops = { + .detect = samsung_nand_decode_id, + .init = samsung_nand_init, +}; diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 8fb2a43296f5..d0312e924b4d 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -1158,6 +1158,8 @@ struct nand_manufacturers { extern struct nand_flash_dev nand_flash_ids[]; extern struct nand_manufacturers nand_manuf_ids[]; +extern const struct nand_manufacturer_ops samsung_nand_manuf_ops; + int nand_default_bbt(struct mtd_info *mtd); int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs); From patchwork Fri Jul 22 16:10:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2237 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ej1-f69.google.com (mail-ej1-f69.google.com [209.85.218.69]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 8758A3F047 for ; Fri, 22 Jul 2022 18:11:18 +0200 (CEST) Received: by mail-ej1-f69.google.com with SMTP id gt38-20020a1709072da600b0072f21d7d12dsf2074003ejc.7 for ; Fri, 22 Jul 2022 09:11:18 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1658506278; cv=pass; d=google.com; s=arc-20160816; b=AupC/pb/jFKjgyj+TJcnrUkCYTMH+ZPkFI2+X5yP6VA9ETthQMpgeiwnJkQHZI+J5/ D4yPyhAjuzk+fYYndT5kpMtHsSWLuqS4ZUazhUiVQyvCN0xe4Qwwyelp645f7JfiGGK2 LykYlh/fQLfP3lrS9tW3T6hHkT64O0nL6IutBauUnAN+qf+tJO0Y7dOhyUtCPZx2FEYT 981m7c0NNRZHELhV4IYg06Nw0Dc8BKyRCNDfvnX1D+mQ5baQknIS73y4hDEuZ+FWSaOJ kxZ9Jp9dQPSTeGUU6yXDywB2ln+z/D2bNMbch/aM4WwUlzyV/jpuASKx7zjRiAWc3pUn PvvQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Jvo8FcX5eiF6PEIVD7gM3zj3JGrr+PIDBGvjshzHgos=; b=G5kH3pUyYHuZDzA7s2BOQE+rl9eQk7SkrvujnHK9z4cI5aCn6Xw4xWbgxsGwdePXs9 q/xkEqbfGaKGMJJh/T+FYqaHx7tNMl1w5aFN2h0/rHZn6K97v8jtuUlLtX00iU6EXlBo hWrQ82z25mJD06QaRms2YWP9+8axQXGd7AKBDZuk1kYnfoOFb9pUt3aaXeHBDO04+n8o ICR3r+IaTcNNRiFiz0AV1gUqtnGfbSYjJXFAujPSpDMGI71YC4aeA/VvR6JvDMSGzAa2 LXv3azkQScFXOJKIrS0KMZr485zr7M3KY94naX51GOZtzoXoEC5EPLWsyL4nPbfHHrTp c7+A== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=MA2G+npr; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=Jvo8FcX5eiF6PEIVD7gM3zj3JGrr+PIDBGvjshzHgos=; b=HHWbW+QU2DQAEwr1v5w7cDowXgRX2aLvbeI5Bl5/u8Ipb+ps3SpMLNG5nDtftdSw6T lN4FMN4Rz0uHA0ueDSdm7ZaR1VycnbxIVubG9GZr957NZQGzQBXZOBCib/BQ4Zt3VlV7 eLRUpfBYX9xfGuUWfnJS7/6vwffh//JuXmXDw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=Jvo8FcX5eiF6PEIVD7gM3zj3JGrr+PIDBGvjshzHgos=; b=heklfjqAPPsXob0JP9esM1812YroBEfiloRVD6IwZyG5BbfJjGbQq4oQrxsYWd3YJc rE6d1AnO4Te0fIkBPMEnP1p88r/2IG+cHBbVzxZwR5uW1ZTdHqObAKv7zI1T32g529ox 0v3FQs4ioCOdyoGtVKMmuSCOwbCwgsxYtpydy1xZBnembKyZ5Oa3wYD+OGeJJ+zwR78y ls1wuK76VGeiK+BW7CWVMBO20NQxx2k/cN8KGU9zIo2FIqiB+Y+lzkaiNbj5hb1UYWj6 1JUe2BPqnF4CdpZWwinG5thZd3/Ptl4S+MgkdqvFx4UPFHiECTU6MWGAt7f/JU6F7Xls IwMQ== X-Gm-Message-State: AJIora+hnij1edsZmEAQ17xaUzhL+TrS6GQcTQo4PhslGdxd8OnWqDn4 4M1u3mkmbOC8A/R8/gLoDj1Z2j4u X-Google-Smtp-Source: AGRyM1un0EFIgIegw3kr2/oLtWMiKY8cWPibTLwknsplPNvM3mm87ObXj9ra0nfucS6eQPA5gZT2IA== X-Received: by 2002:a17:906:9b14:b0:72b:7c96:58c9 with SMTP id eo20-20020a1709069b1400b0072b7c9658c9mr496208ejc.648.1658506278167; Fri, 22 Jul 2022 09:11:18 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:906:ece3:b0:72f:6ce5:d858 with SMTP id qt3-20020a170906ece300b0072f6ce5d858ls3081408ejb.4.-pod-prod-gmail; Fri, 22 Jul 2022 09:11:17 -0700 (PDT) X-Received: by 2002:a17:907:e94:b0:72b:700e:21d9 with SMTP id ho20-20020a1709070e9400b0072b700e21d9mr476811ejc.665.1658506277035; Fri, 22 Jul 2022 09:11:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1658506277; cv=none; d=google.com; s=arc-20160816; b=a+wKr9FYqpfcXbceopSU7p2kEIFbioOmh3QGAGbZpQaxcIswGZJX2XyCct2qVVDKet oJO4GJ2O5fzSk9Ip0daX/i8gjGwWgT7ii6v9BmgMv0SsjOGD+5KwwhqD2YeBqyB06GNm 6DKwqnlATDlnSjf70d0edjZxadN9dxgzNIu8f695MJhWmd6fDJ2ui1GQePUi4EqlaNsO q9s9eoBwnzWS4oZ+arJX5m1Dpoap3srdm+gtvNn9wQ6p+Bcp6H1VvjU8dsu4qkvo/COs 4TfhDdPloKjNC3FFCRn9GsO3p7HJyJEAGG+MeENkEG/ymZqGC19gU0GWg2XvmNwMUlA7 W0dg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=y4xGAGlpxcJZI8KRs+76b+i92Av8BxVMTM+CQF6080g=; b=WWuW5i+DkQ5vIsKtfbjfaeGptkHS1D1ARryhOEpfb8z1slCn+rpBV7RFkvVQ4ZsyaR nDw/FJLIYSvBvGkNsSOroGczKqxivocm54p+9k8TNbVNlTGRNJncTYFTlxu9fJYXbe+p Aqm19ogNVm2BKVZb2u5/iQqZKOL4ey0AaENyCjsN219afnvVy2giCfaT5uFgg84YHlMb Dy8X3v6NRYaXHO/jsEswHPyloprNcosfT+tKzeEdclAlRGfby0xMTy51ZyLp0RQaO5Em IeapU9MMbbHug2x2Fu0thqAptMs5G+hla0HfqHq4Nxgo5UDdU6O8AOb4imLWlpzEXznf jZWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=MA2G+npr; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id j23-20020a17090643d700b0072f15f31f0asor2184366ejn.118.2022.07.22.09.11.17 for (Google Transport Security); Fri, 22 Jul 2022 09:11:17 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:906:98c8:b0:72b:41dc:c271 with SMTP id zd8-20020a17090698c800b0072b41dcc271mr527230ejb.36.1658506276759; Fri, 22 Jul 2022 09:11:16 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.pdxnet.pdxeng.ch (host-87-14-98-67.retail.telecomitalia.it. [87.14.98.67]) by smtp.gmail.com with ESMTPSA id d19-20020a170906305300b006fe8ac6bc69sm2174025ejd.140.2022.07.22.09.11.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Jul 2022 09:11:16 -0700 (PDT) From: Dario Binacchi To: u-boot@lists.denx.de Cc: Amarula patchwork , michael@amarulasolutions.com, Dario Binacchi , Patrice Chotard , Simon Glass , Wolfgang Denk Subject: [PATCH v4 08/14] mtd: nand: Move Hynix specific init/detection logic in nand_hynix.c Date: Fri, 22 Jul 2022 18:10:02 +0200 Message-Id: <20220722161009.2686504-9-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220722161009.2686504-1-dario.binacchi@amarulasolutions.com> References: <20220722161009.2686504-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=MA2G+npr; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Michael Trimarchi Upstream linux commit 01389b6bd2f4f7. Move Hynix specific initialization and detection logic into nand_hynix.c. This is part of the "separate vendor specific code from core" cleanup process. Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi --- (no changes since v3) Changes in v3: - Use commit sha1 with 13 digits. - Add the SPDX-License-Identifier tag. - Fix code style warnings raised by patman. Changes in v2: - Use short-commit form - Remove linux info. Uboot seems that backport without add this extra information. - Adjust the include file in nand_hynix. drivers/mtd/nand/raw/Makefile | 3 +- drivers/mtd/nand/raw/nand_base.c | 117 ++++++++---------------------- drivers/mtd/nand/raw/nand_hynix.c | 85 ++++++++++++++++++++++ drivers/mtd/nand/raw/nand_ids.c | 2 +- include/linux/mtd/rawnand.h | 1 + 5 files changed, 120 insertions(+), 88 deletions(-) create mode 100644 drivers/mtd/nand/raw/nand_hynix.c diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 440290bed0fe..86d9b8e8beb8 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -14,7 +14,7 @@ obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o obj-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o -obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_samsung.o +obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_hynix.o nand_samsung.o obj-$(CONFIG_SPL_NAND_IDENT) += nand_ids.o nand_timings.o obj-$(CONFIG_TPL_NAND_INIT) += nand.o ifeq ($(CONFIG_SPL_ENV_SUPPORT),y) @@ -31,6 +31,7 @@ obj-y += nand_ids.o obj-y += nand_util.o obj-y += nand_ecc.o obj-y += nand_base.o +obj-y += nand_hynix.o obj-y += nand_samsung.o obj-y += nand_timings.o diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index fe59157bc3c4..5698c1e6a229 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4170,85 +4170,34 @@ void nand_decode_ext_id(struct nand_chip *chip) extid = chip->id.data[3]; id_len = chip->id.len; + /* Calc pagesize */ + mtd->writesize = 1024 << (extid & 0x03); + extid >>= 2; + /* Calc oobsize */ + mtd->oobsize = (8 << (extid & 0x01)) * + (mtd->writesize >> 9); + extid >>= 2; + /* Calc blocksize. Blocksize is multiples of 64KiB */ + mtd->erasesize = (64 * 1024) << (extid & 0x03); + extid >>= 2; + /* Get buswidth information */ + /* Get buswidth information */ + if (extid & 0x1) + chip->options |= NAND_BUSWIDTH_16; + /* - * Field definitions are in the following datasheets: - * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32) - * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22) - * - * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung - * ID to decide what to do. + * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per + * 512B page. For Toshiba SLC, we decode the 5th/6th byte as + * follows: + * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm, + * 110b -> 24nm + * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC */ - if (id_len == 6 && chip->id.data[0] == NAND_MFR_HYNIX && - !nand_is_slc(chip)) { - unsigned int tmp; - - /* Calc pagesize */ - mtd->writesize = 2048 << (extid & 0x03); - extid >>= 2; - /* Calc oobsize */ - switch (((extid >> 2) & 0x04) | (extid & 0x03)) { - case 0: - mtd->oobsize = 128; - break; - case 1: - mtd->oobsize = 224; - break; - case 2: - mtd->oobsize = 448; - break; - case 3: - mtd->oobsize = 64; - break; - case 4: - mtd->oobsize = 32; - break; - case 5: - mtd->oobsize = 16; - break; - default: - mtd->oobsize = 640; - break; - } - extid >>= 2; - /* Calc blocksize */ - tmp = ((extid >> 1) & 0x04) | (extid & 0x03); - if (tmp < 0x03) - mtd->erasesize = (128 * 1024) << tmp; - else if (tmp == 0x03) - mtd->erasesize = 768 * 1024; - else - mtd->erasesize = (64 * 1024) << tmp; - } else { - /* Calc pagesize */ - mtd->writesize = 1024 << (extid & 0x03); - extid >>= 2; - /* Calc oobsize */ - mtd->oobsize = (8 << (extid & 0x01)) * - (mtd->writesize >> 9); - extid >>= 2; - /* Calc blocksize. Blocksize is multiples of 64KiB */ - mtd->erasesize = (64 * 1024) << (extid & 0x03); - extid >>= 2; - /* Get buswidth information */ - /* Get buswidth information */ - if (extid & 0x1) - chip->options |= NAND_BUSWIDTH_16; - - /* - * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per - * 512B page. For Toshiba SLC, we decode the 5th/6th byte as - * follows: - * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm, - * 110b -> 24nm - * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC - */ - if (id_len >= 6 && chip->id.data[0] == NAND_MFR_TOSHIBA && - nand_is_slc(chip) && - (chip->id.data[5] & 0x7) == 0x6 /* 24nm */ && - !(chip->id.data[4] & 0x80) /* !BENAND */) { - mtd->oobsize = 32 * mtd->writesize >> 9; - } - + if (id_len >= 6 && chip->id.data[0] == NAND_MFR_TOSHIBA && + nand_is_slc(chip) && + (chip->id.data[5] & 0x7) == 0x6 /* 24nm */ && + !(chip->id.data[4] & 0x80) /* !BENAND */) { + mtd->oobsize = 32 * mtd->writesize >> 9; } } EXPORT_SYMBOL_GPL(nand_decode_ext_id); @@ -4339,15 +4288,11 @@ static void nand_decode_bbm_options(struct mtd_info *mtd, * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba, * AMD/Spansion, and Macronix. All others scan only the first page. */ - if (!nand_is_slc(chip) && maf_id == NAND_MFR_HYNIX) - chip->bbt_options |= NAND_BBT_SCANLASTPAGE; - else if ((nand_is_slc(chip) && - (maf_id == NAND_MFR_HYNIX || - maf_id == NAND_MFR_TOSHIBA || - maf_id == NAND_MFR_AMD || - maf_id == NAND_MFR_MACRONIX)) || - (mtd->writesize == 2048 && - maf_id == NAND_MFR_MICRON)) + if ((nand_is_slc(chip) && + (maf_id == NAND_MFR_TOSHIBA || + maf_id == NAND_MFR_AMD || + maf_id == NAND_MFR_MACRONIX)) || + (mtd->writesize == 2048 && maf_id == NAND_MFR_MICRON)) chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; } diff --git a/drivers/mtd/nand/raw/nand_hynix.c b/drivers/mtd/nand/raw/nand_hynix.c new file mode 100644 index 000000000000..547ce7c92031 --- /dev/null +++ b/drivers/mtd/nand/raw/nand_hynix.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Free Electrons + * Copyright (C) 2017 NextThing Co + * + * Author: Boris Brezillon + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +static void hynix_nand_decode_id(struct nand_chip *chip) +{ + struct mtd_info *mtd = nand_to_mtd(chip); + + /* Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22) */ + if (chip->id.len == 6 && !nand_is_slc(chip)) { + u8 tmp, extid = chip->id.data[3]; + + /* Extract pagesize */ + mtd->writesize = 2048 << (extid & 0x03); + extid >>= 2; + + /* Extract oobsize */ + switch (((extid >> 2) & 0x4) | (extid & 0x3)) { + case 0: + mtd->oobsize = 128; + break; + case 1: + mtd->oobsize = 224; + break; + case 2: + mtd->oobsize = 448; + break; + case 3: + mtd->oobsize = 64; + break; + case 4: + mtd->oobsize = 32; + break; + case 5: + mtd->oobsize = 16; + break; + default: + mtd->oobsize = 640; + break; + } + + /* Extract blocksize */ + extid >>= 2; + tmp = ((extid >> 1) & 0x04) | (extid & 0x03); + if (tmp < 0x03) + mtd->erasesize = (128 * 1024) << tmp; + else if (tmp == 0x03) + mtd->erasesize = 768 * 1024; + else + mtd->erasesize = (64 * 1024) << tmp; + } else { + nand_decode_ext_id(chip); + } +} + +static int hynix_nand_init(struct nand_chip *chip) +{ + if (!nand_is_slc(chip)) + chip->bbt_options |= NAND_BBT_SCANLASTPAGE; + else + chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; + + return 0; +} + +const struct nand_manufacturer_ops hynix_nand_manuf_ops = { + .detect = hynix_nand_decode_id, + .init = hynix_nand_init, +}; diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c index f4126c3a5a13..ec263a43279a 100644 --- a/drivers/mtd/nand/raw/nand_ids.c +++ b/drivers/mtd/nand/raw/nand_ids.c @@ -194,7 +194,7 @@ struct nand_manufacturers nand_manuf_ids[] = { {NAND_MFR_NATIONAL, "National"}, {NAND_MFR_RENESAS, "Renesas"}, {NAND_MFR_STMICRO, "ST Micro"}, - {NAND_MFR_HYNIX, "Hynix"}, + {NAND_MFR_HYNIX, "Hynix", &hynix_nand_manuf_ops}, {NAND_MFR_MICRON, "Micron"}, {NAND_MFR_AMD, "AMD/Spansion"}, {NAND_MFR_MACRONIX, "Macronix"}, diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index d0312e924b4d..d35277d18799 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -1159,6 +1159,7 @@ extern struct nand_flash_dev nand_flash_ids[]; extern struct nand_manufacturers nand_manuf_ids[]; extern const struct nand_manufacturer_ops samsung_nand_manuf_ops; +extern const struct nand_manufacturer_ops hynix_nand_manuf_ops; int nand_default_bbt(struct mtd_info *mtd); int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); From patchwork Fri Jul 22 16:10:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2238 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f71.google.com (mail-ed1-f71.google.com [209.85.208.71]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 8B2213F047 for ; Fri, 22 Jul 2022 18:11:19 +0200 (CEST) Received: by mail-ed1-f71.google.com with SMTP id h15-20020a056402280f00b0043bd8412fe0sf286470ede.16 for ; Fri, 22 Jul 2022 09:11:19 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1658506279; cv=pass; d=google.com; s=arc-20160816; b=Fbv35xoJLMib+Uww3KaRiv7wJYiOUkAARYOvIMDT9TR/SVAl8UJTG0jNzYzmur2Fol JIdG78vXP5vwvPhOFGhFQglGVhpI4hvhJmAQ3Og47co1i6AP1bFPXS9tR9OTP5C4CqEV j7F2g4evT0i9VNIPZaFMz/ED6XaBxKOGaOUszAp9SSGoiAJmFgSQv0Jd+3JYsPKlU1Cw WX5hV9TJOxG8oG+ZdeHUIM9l7Kic+G8jvr2CYWSUrqzfiCFykHhIgY0d8NXMIXUk9vfs xlotCvumNiv+xSIBPVG/9RE9gvmy3Nq/4brcd5wlnt7cIKiIq5KTCAdI7ncB00kkAzE4 Va0g== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=ewGf6eOjiLTiCqAcH5LWvGQJpLhWabhte5dm7qE5oV8=; b=ZF5ZVGoMG1a8ndZSTSiHGRRB3rwD7IoXdNTJhuFouCe3WPrm8gFY1P8LTM0EC/JpKx 5/j/FkXV+3ApT+h9ln0TiWMgUL4Jr42mMT3jBSYZ/iY5xxafCLB/lhJnuqRYHYymQcq/ EKpOIUI1S6+UqcecDsOOzWm3lbe5jVhiHbzVwzZh+weIET3+i+2l8o2kLFit13adQr7l /d6FadBuza6SjTT0gH1q7erxSS9T/4GxU9rhaMXrN1spivE6m/QKdPPoCqp+V9H1s6qw 8r9WCJGzkRKDqXX7Krucn/4IRg6KkuZheiVY1knuqvpvPr5T8XzHa/IHrcKvGxeYUbC3 AhWA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=qZFlH+bs; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=ewGf6eOjiLTiCqAcH5LWvGQJpLhWabhte5dm7qE5oV8=; b=mJJ2jGdWNGmK5DGFw7eYW7gy3w8lmbVR/+E+anws3K3ULhNddW4NQu8fdxM1qg1tUJ ZQnhT0VOnSMEULwSTrhr057z0izxOhSTPgFjYceSeLGr00DONT7oW7TQrg97TzqigcuG bpZuGTUHGIPDhgOc8BgXMrlOCy4Ec3qLYLht8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=ewGf6eOjiLTiCqAcH5LWvGQJpLhWabhte5dm7qE5oV8=; b=mj8FuGbxjAy6VOtqocZItyIfgFDVnf+agIPVHCvPCDS6VpKLnaoaST8KWFeKppGDTG 4H5MO/3g4s16JLyluMXRROGXgcd280nAQGd0P1wWQLCCq/xvW5Ljo46q+QWBFweyZyti QPDaCagZxFKe9Uwga/OU0VRoVm0CSr3WtP6HcBlIhE6eGD08iSsLQA2xK/T0u36TVXG/ 32JP2wN5Qs944pbBTZwcREAuHq91yS5MsZGTb5T0pgjtOEOxG6ilkSZxgCXgt53FwDzG 3b1YV688EmUpKrVljnvnZZjryIPbKJ/9VCC3mdKpiJBzSNc5GeVGJMdqUp7NNLXbk89R xlaw== X-Gm-Message-State: AJIora8NORkGapGqfihxg+Z2VJqwZb9CVSy/cKFMkzV5EDGA9ea4aLWO hrXhMY40D1SQUDONp6s3Kso2HFMn X-Google-Smtp-Source: AGRyM1tiIWV0dcxN6sht5wEEzCrb4NAMtfMxINLiVK5CUpIV4Dhjeg/9NjogNNIxsL1uvmyG3tyJWw== X-Received: by 2002:a17:907:94d0:b0:72f:269c:3aa3 with SMTP id dn16-20020a17090794d000b0072f269c3aa3mr443547ejc.695.1658506279365; Fri, 22 Jul 2022 09:11:19 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:906:6cf:b0:72f:5c1f:1852 with SMTP id v15-20020a17090606cf00b0072f5c1f1852ls3071955ejb.0.-pod-prod-gmail; Fri, 22 Jul 2022 09:11:18 -0700 (PDT) X-Received: by 2002:a17:907:9706:b0:72b:4b0d:86a2 with SMTP id jg6-20020a170907970600b0072b4b0d86a2mr484861ejc.242.1658506278176; Fri, 22 Jul 2022 09:11:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1658506278; cv=none; d=google.com; s=arc-20160816; b=zSpLaROpHuxYQNsomHOgw2oso1FzsSSivwJs5e0S4dg4YweTeEvJUjOQ91R2wIQUr+ 4kiBz+jfkVJXUY87FD9TH5WvOcR6f8xML6oUzuWCnDG3Iyqv1JELFnznob/CV5AuU5F8 QTP5LK5Cc3uUgRj1zqIwng53m4WtzRBAkBE2H/Dm4lVSBNN+KHqgXtpMImRHTIKZdrb+ 951c435h5YqYJ9fixWzOGfX2+hRsvIAe/stgMskRimh4Iq6hvDPuLsBlb5iPwhxfcAQI EcQvFmi9L0yfj0A3fIDnTnnNWPXkEtn4W+d6RF/Jyq5oUDSrVe+bI8KM6SZSmAkFI6p/ RdKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=cSB0BpiXJDkvrgFoBXhS8Ii1tPQoOHvkzPEATYktly4=; b=OT+gYIF84nGgLlutjKxJSEbB+zEqc7PfQn3tFJYVIuXR5sby+VKPZBifDGmAm4N01N sjqwah3e3NoXd0C0YuVHVsgl0+NnKuk0dEHxTbsdUrFOGcWECNGU4KSZ8rgipBW7IG/6 L5APST6RpUgP+dZ/OaoNFjNVc73quBwQcOsvrhjmqoHQeKyYDZuosg/aVc6eqUpr/mPS mwwOZ2fUBLAJoPAxKWfYQ+3bjAdrRjEfT2oZVTpyriZONnoC45Q0/9mX0b7v5CdclHzC W69r3rXAuUxCX5fa2l61zig189N2sJHvoHsSNpIyILCefOljI1kJqZdKMj0IDqDLsRGw 4V/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=qZFlH+bs; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id g27-20020a170906199b00b0072ae770fd83sor2233081ejd.38.2022.07.22.09.11.18 for (Google Transport Security); Fri, 22 Jul 2022 09:11:18 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:907:970c:b0:72e:e972:5c73 with SMTP id jg12-20020a170907970c00b0072ee9725c73mr489754ejc.352.1658506277897; Fri, 22 Jul 2022 09:11:17 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.pdxnet.pdxeng.ch (host-87-14-98-67.retail.telecomitalia.it. [87.14.98.67]) by smtp.gmail.com with ESMTPSA id d19-20020a170906305300b006fe8ac6bc69sm2174025ejd.140.2022.07.22.09.11.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Jul 2022 09:11:17 -0700 (PDT) From: Dario Binacchi To: u-boot@lists.denx.de Cc: Amarula patchwork , michael@amarulasolutions.com, Dario Binacchi , Patrice Chotard , Simon Glass , Wolfgang Denk Subject: [PATCH v4 09/14] mtd: nand: Move Toshiba specific init/detection logic in nand_toshiba.c Date: Fri, 22 Jul 2022 18:10:03 +0200 Message-Id: <20220722161009.2686504-10-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220722161009.2686504-1-dario.binacchi@amarulasolutions.com> References: <20220722161009.2686504-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=qZFlH+bs; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Michael Trimarchi Upstream linux commit 9b2d61f80b060c. Move Toshiba specific initialization and detection logic into nand_toshiba.c. This is part of the "separate vendor specific code from core" cleanup process. Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi --- (no changes since v3) Changes in v3: - Use commit sha1 with 13 digits. - Add the SPDX-License-Identifier tag. - Fix code style warnings raised by patman. Changes in v2: - Use short-commit form - Remove linux info. Uboot seems that backport without add this extra information. - Adjust the include file in nand_toshiba. drivers/mtd/nand/raw/Makefile | 3 +- drivers/mtd/nand/raw/nand_base.c | 21 ++---------- drivers/mtd/nand/raw/nand_ids.c | 2 +- drivers/mtd/nand/raw/nand_toshiba.c | 53 +++++++++++++++++++++++++++++ include/linux/mtd/rawnand.h | 1 + 5 files changed, 59 insertions(+), 21 deletions(-) create mode 100644 drivers/mtd/nand/raw/nand_toshiba.c diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 86d9b8e8beb8..16e0775395a2 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -14,7 +14,7 @@ obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o obj-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o -obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_hynix.o nand_samsung.o +obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_hynix.o nand_samsung.o nand_toshiba.o obj-$(CONFIG_SPL_NAND_IDENT) += nand_ids.o nand_timings.o obj-$(CONFIG_TPL_NAND_INIT) += nand.o ifeq ($(CONFIG_SPL_ENV_SUPPORT),y) @@ -33,6 +33,7 @@ obj-y += nand_ecc.o obj-y += nand_base.o obj-y += nand_hynix.o obj-y += nand_samsung.o +obj-y += nand_toshiba.o obj-y += nand_timings.o endif # not spl diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 5698c1e6a229..4ea7f10a06fc 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4163,12 +4163,11 @@ static int nand_get_bits_per_cell(u8 cellinfo) void nand_decode_ext_id(struct nand_chip *chip) { struct mtd_info *mtd = &chip->mtd; - int extid, id_len; + int extid; /* The 3rd id byte holds MLC / multichip data */ chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]); /* The 4th id byte is the important one */ extid = chip->id.data[3]; - id_len = chip->id.len; /* Calc pagesize */ mtd->writesize = 1024 << (extid & 0x03); @@ -4184,21 +4183,6 @@ void nand_decode_ext_id(struct nand_chip *chip) /* Get buswidth information */ if (extid & 0x1) chip->options |= NAND_BUSWIDTH_16; - - /* - * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per - * 512B page. For Toshiba SLC, we decode the 5th/6th byte as - * follows: - * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm, - * 110b -> 24nm - * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC - */ - if (id_len >= 6 && chip->id.data[0] == NAND_MFR_TOSHIBA && - nand_is_slc(chip) && - (chip->id.data[5] & 0x7) == 0x6 /* 24nm */ && - !(chip->id.data[4] & 0x80) /* !BENAND */) { - mtd->oobsize = 32 * mtd->writesize >> 9; - } } EXPORT_SYMBOL_GPL(nand_decode_ext_id); @@ -4289,8 +4273,7 @@ static void nand_decode_bbm_options(struct mtd_info *mtd, * AMD/Spansion, and Macronix. All others scan only the first page. */ if ((nand_is_slc(chip) && - (maf_id == NAND_MFR_TOSHIBA || - maf_id == NAND_MFR_AMD || + (maf_id == NAND_MFR_AMD || maf_id == NAND_MFR_MACRONIX)) || (mtd->writesize == 2048 && maf_id == NAND_MFR_MICRON)) chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c index ec263a43279a..509652c8e26c 100644 --- a/drivers/mtd/nand/raw/nand_ids.c +++ b/drivers/mtd/nand/raw/nand_ids.c @@ -188,7 +188,7 @@ struct nand_flash_dev nand_flash_ids[] = { /* Manufacturer IDs */ struct nand_manufacturers nand_manuf_ids[] = { - {NAND_MFR_TOSHIBA, "Toshiba"}, + {NAND_MFR_TOSHIBA, "Toshiba", &toshiba_nand_manuf_ops}, {NAND_MFR_SAMSUNG, "Samsung", &samsung_nand_manuf_ops}, {NAND_MFR_FUJITSU, "Fujitsu"}, {NAND_MFR_NATIONAL, "National"}, diff --git a/drivers/mtd/nand/raw/nand_toshiba.c b/drivers/mtd/nand/raw/nand_toshiba.c new file mode 100644 index 000000000000..f7426fa59f51 --- /dev/null +++ b/drivers/mtd/nand/raw/nand_toshiba.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Free Electrons + * Copyright (C) 2017 NextThing Co + * + * Author: Boris Brezillon + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +static void toshiba_nand_decode_id(struct nand_chip *chip) +{ + struct mtd_info *mtd = nand_to_mtd(chip); + + nand_decode_ext_id(chip); + + /* + * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per + * 512B page. For Toshiba SLC, we decode the 5th/6th byte as + * follows: + * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm, + * 110b -> 24nm + * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC + */ + if (chip->id.len >= 6 && nand_is_slc(chip) && + (chip->id.data[5] & 0x7) == 0x6 /* 24nm */ && + !(chip->id.data[4] & 0x80) /* !BENAND */) + mtd->oobsize = 32 * mtd->writesize >> 9; +} + +static int toshiba_nand_init(struct nand_chip *chip) +{ + if (nand_is_slc(chip)) + chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; + + return 0; +} + +const struct nand_manufacturer_ops toshiba_nand_manuf_ops = { + .detect = toshiba_nand_decode_id, + .init = toshiba_nand_init, +}; diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index d35277d18799..73abb3401649 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -1158,6 +1158,7 @@ struct nand_manufacturers { extern struct nand_flash_dev nand_flash_ids[]; extern struct nand_manufacturers nand_manuf_ids[]; +extern const struct nand_manufacturer_ops toshiba_nand_manuf_ops; extern const struct nand_manufacturer_ops samsung_nand_manuf_ops; extern const struct nand_manufacturer_ops hynix_nand_manuf_ops; From patchwork Fri Jul 22 16:10:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2239 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ej1-f71.google.com (mail-ej1-f71.google.com [209.85.218.71]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id D468F3F047 for ; Fri, 22 Jul 2022 18:11:20 +0200 (CEST) Received: by mail-ej1-f71.google.com with SMTP id hs16-20020a1709073e9000b0072b73a28465sf2107580ejc.17 for ; Fri, 22 Jul 2022 09:11:20 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1658506280; cv=pass; d=google.com; s=arc-20160816; b=MAXsCJzuFxA6xd5+6d6xMem2j14cOdr6r6ETn0zoww+N1sehwCiaTRzqN588tHR1aE rGwgJSsEDU0ywGaoLR7PohLqF8IhX+/u259a2CM6IiEYq2AnGffLpm1OJXqyrnPlZfOT zII07fjJKIePwQLwd/dWP1Dc1MyPf0qFKTH+jpI4MxbAKPOckEj8F9py3tlPSqLp/UX7 sYbR1agMnNHv68ABPcKIlVDHDw4lCmCTa7+wjNKLBvJNo8wACpqAWjtWQ2r4spuLE/Og rHYOjPxo4JwsS5eHF4pKZWFkK3rpySPMffsY69PJcr6dN5cacrD9Et6oHlSWP887D5h6 G9yQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=FZ5EpgOT5fa8C1uj6OSTP7Vd/v+d/VEHYnyuypm/0Ew=; b=yYrvPaLAm67ErRYq/9pn8I1YPkyam7O/OqG5fB6X6lw+kkInXHdJ3CpWZbNf1cr2Sn A8J9FS+uIkAkrI9Ya98mpCpXM4FuwSTIUAseN2QUXGHuN80e2owAQZ8/Qev6vhYnsQw1 TmQFtJYQh0S2+RGSEx1da19srzSoo8q8U6m+EqnAMLBIKPKMSik5ccdyYNA0koyB8ANX E9/zdq8X1eBqVRbPtyFGW5t57JdXSDzsEAHZm0EPMXdiUbEiSmBqgeGPwRl+r1zpvNwK Svk9q9Zu0E20mX9rn1bjyKxLFGD2w81CEu+NcVbVXQveRS/RHz8n1q3oQb4R0AYvg7S3 dR9Q== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=VUUMzG1C; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=FZ5EpgOT5fa8C1uj6OSTP7Vd/v+d/VEHYnyuypm/0Ew=; b=JxId1s2w7CZR6l+q4nUaylwZLmj9YPa9A9wPYrKu69XTp7KLDDMaTQUHxQIqsCRaWa MaP8Y8JUm+6cvnggqnZ/KkfwXvd3wPxwNjvKREV1wiCa/f6MgpRK2/TXDmFvlJtPN6HX Odum6vYDF8TXsZXn0cDdUa5WE1Fq2dQMGcgjg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=FZ5EpgOT5fa8C1uj6OSTP7Vd/v+d/VEHYnyuypm/0Ew=; b=Sn7keuQcIJ06f5CfguBLii9zQzHn/DgKEkyaQfUN1+zfTLkDCShrmP3oVeFgGICrBh 8dlfSxeXmX2msxuGkLBfudiBP1jJ1LBqd0Aeh1Kn3dy7A9cCZ4QSzC28dh/Gd/szxAIN 5+MWG0C5vQZZ7PGeALdcaP8ic+QFEqIKMAQ1BrNbkjPE9zHsfBf3/4lgI3HSphBUaudm MkyDA/Q1Fxrm5SydOMMTIFY6GGYV/KsuoJbKANHnTYCIvlOqkGL/GzUDN/V7gEGu/fpt fQu9swTRWokAeAJlh2wNNyAGJq8cEHo0HWx1SDyRwkII2K0PNSAonLKCoZfxepD4/fkJ uXBQ== X-Gm-Message-State: AJIora+7pYMUARFS4HAK89VR/yj56RA0sGLiyfZwZo5jf/f+2c2t9E0A mlF/9s/ped8MR36C373CIJp9c8Fs X-Google-Smtp-Source: AGRyM1v+qrjRCSQVXcHZ2M/fYT4kVXf2inNh8Dq7FDOACBlT3tiJe453Z3cQMFGP272SrpxckUcwMw== X-Received: by 2002:a17:907:9493:b0:72f:40ca:fe79 with SMTP id dm19-20020a170907949300b0072f40cafe79mr471046ejc.511.1658506280664; Fri, 22 Jul 2022 09:11:20 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a05:6402:2809:b0:43a:77a6:b0d with SMTP id h9-20020a056402280900b0043a77a60b0dls2108227ede.3.-pod-prod-gmail; Fri, 22 Jul 2022 09:11:19 -0700 (PDT) X-Received: by 2002:a05:6402:48c:b0:43a:8bc7:f440 with SMTP id k12-20020a056402048c00b0043a8bc7f440mr619671edv.8.1658506279460; Fri, 22 Jul 2022 09:11:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1658506279; cv=none; d=google.com; s=arc-20160816; b=LJ9VzWGujCW7tukWOpCDwC0nZHZi9JU+GOKw7v7AsaliaWJpe3CjfmCgoK88B6Jkj0 EtAPEqVIKu9gEyphDRopWyqr+9pmb9wiRVrq46DYvcAs+kokPuZOtj/cyUncMM3ctoKU w4R6zBZtUtPy96fR3GIUXEAIAXtDamoRwG47qGCafp/tkODkF9d9hQ5f3zPU2Hn80TjD GcEk0/eJ3RLWi6ACsh3J6ymPqbabfDfxY/lpf0mAMWsLyzNMlSwHocni3hz30GP6oBJ5 3YzhThCbghmPqIYmIjh7aJQWnspg7n49tsasJT2Epe9nG5Zco/WBuOU3s1jGW1V3Jws/ AfTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=VTfPyW+HXeu/cQyhrJLPIcmJVM7MYEIoxq4LeP00Dkg=; b=kXvniLI9xgMZpIRsCCQSiilg20TkkerNEHcjOh8H5x8PbMRjERCc2Uub6WT1u3d4+P p4i4yfTt29RuXw+Os0q+7+YAv9E/ajm5/9/q4ds/7j2CS3Wcu5wDGFJRtmBgSHCRM+Wr 3QjSmDIT9Dwl2kGCYfo9bK4E1gwAwHORWcm3X4VKhSbjSSfo+V/5auErb5+RZbTt4gcy irj5Dl3cRo3AyJWHeZ73jBupo+032Q+hDIKyPFaqmu7ZuSreb4Qxc91ITCDxEkagW52D fb1/t2OfEbokOWBO1cwOm4gian554HCiL5Z5bn5BzVkX5tf6LTJyMU6h37OsdP54E+bP Dc1g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=VUUMzG1C; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id v5-20020a170906b00500b0072b616ac648sor2151698ejy.85.2022.07.22.09.11.19 for (Google Transport Security); Fri, 22 Jul 2022 09:11:19 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:907:1c95:b0:72b:4e37:7736 with SMTP id nb21-20020a1709071c9500b0072b4e377736mr484247ejc.516.1658506279154; Fri, 22 Jul 2022 09:11:19 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.pdxnet.pdxeng.ch (host-87-14-98-67.retail.telecomitalia.it. [87.14.98.67]) by smtp.gmail.com with ESMTPSA id d19-20020a170906305300b006fe8ac6bc69sm2174025ejd.140.2022.07.22.09.11.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Jul 2022 09:11:18 -0700 (PDT) From: Dario Binacchi To: u-boot@lists.denx.de Cc: Amarula patchwork , michael@amarulasolutions.com, Dario Binacchi , Patrice Chotard , Simon Glass , Wolfgang Denk Subject: [PATCH v4 10/14] mtd: nand: Move Micron specific init logic in nand_micron.c Date: Fri, 22 Jul 2022 18:10:04 +0200 Message-Id: <20220722161009.2686504-11-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220722161009.2686504-1-dario.binacchi@amarulasolutions.com> References: <20220722161009.2686504-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=VUUMzG1C; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Michael Trimarchi Upstream linux commit 10d4e75c36f6c1. Move Micron specific initialization logic into nand_micron.c. This is part of the "separate vendor specific code from core" cleanup process. Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi --- (no changes since v3) Changes in v3: - Use commit sha1 with 13 digits. - Add the SPDX-License-Identifier tag. - Fix code style warnings raised by patman. Changes in v2: - Use short-commit form - Remove linux info. Uboot seems that backport without add this extra information. - Adjust the include file in nand_micron. drivers/mtd/nand/raw/Makefile | 3 +- drivers/mtd/nand/raw/nand_base.c | 33 +----------- drivers/mtd/nand/raw/nand_ids.c | 2 +- drivers/mtd/nand/raw/nand_micron.c | 87 ++++++++++++++++++++++++++++++ include/linux/mtd/rawnand.h | 21 +------- 5 files changed, 93 insertions(+), 53 deletions(-) create mode 100644 drivers/mtd/nand/raw/nand_micron.c diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 16e0775395a2..8ef30b45fd2d 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -14,7 +14,7 @@ obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o obj-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o -obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_hynix.o nand_samsung.o nand_toshiba.o +obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_hynix.o nand_micron.o nand_samsung.o nand_toshiba.o obj-$(CONFIG_SPL_NAND_IDENT) += nand_ids.o nand_timings.o obj-$(CONFIG_TPL_NAND_INIT) += nand.o ifeq ($(CONFIG_SPL_ENV_SUPPORT),y) @@ -32,6 +32,7 @@ obj-y += nand_util.o obj-y += nand_ecc.o obj-y += nand_base.o obj-y += nand_hynix.o +obj-y += nand_micron.o obj-y += nand_samsung.o obj-y += nand_toshiba.o obj-y += nand_timings.o diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 4ea7f10a06fc..fe7e049d4064 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -3871,30 +3871,6 @@ ext_out: return ret; } -static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode}; - - return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY, - feature); -} - -/* - * Configure chip properties from Micron vendor-specific ONFI table - */ -static void nand_onfi_detect_micron(struct nand_chip *chip, - struct nand_onfi_params *p) -{ - struct nand_onfi_vendor_micron *micron = (void *)p->vendor; - - if (le16_to_cpu(p->vendor_revision) < 1) - return; - - chip->read_retries = micron->read_retry_options; - chip->setup_read_retry = nand_setup_read_retry_micron; -} - /* * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise. */ @@ -3994,9 +3970,6 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip) pr_warn("Could not retrieve ONFI ECC requirements\n"); } - if (p->jedec_id == NAND_MFR_MICRON) - nand_onfi_detect_micron(chip, p); - return 1; } #else @@ -4272,10 +4245,8 @@ static void nand_decode_bbm_options(struct mtd_info *mtd, * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba, * AMD/Spansion, and Macronix. All others scan only the first page. */ - if ((nand_is_slc(chip) && - (maf_id == NAND_MFR_AMD || - maf_id == NAND_MFR_MACRONIX)) || - (mtd->writesize == 2048 && maf_id == NAND_MFR_MICRON)) + if (nand_is_slc(chip) && + (maf_id == NAND_MFR_AMD || maf_id == NAND_MFR_MACRONIX)) chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; } diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c index 509652c8e26c..bb5ac8337fde 100644 --- a/drivers/mtd/nand/raw/nand_ids.c +++ b/drivers/mtd/nand/raw/nand_ids.c @@ -195,7 +195,7 @@ struct nand_manufacturers nand_manuf_ids[] = { {NAND_MFR_RENESAS, "Renesas"}, {NAND_MFR_STMICRO, "ST Micro"}, {NAND_MFR_HYNIX, "Hynix", &hynix_nand_manuf_ops}, - {NAND_MFR_MICRON, "Micron"}, + {NAND_MFR_MICRON, "Micron", µn_nand_manuf_ops}, {NAND_MFR_AMD, "AMD/Spansion"}, {NAND_MFR_MACRONIX, "Macronix"}, {NAND_MFR_EON, "Eon"}, diff --git a/drivers/mtd/nand/raw/nand_micron.c b/drivers/mtd/nand/raw/nand_micron.c new file mode 100644 index 000000000000..8b31c6198134 --- /dev/null +++ b/drivers/mtd/nand/raw/nand_micron.c @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Free Electrons + * Copyright (C) 2017 NextThing Co + * + * Author: Boris Brezillon + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +struct nand_onfi_vendor_micron { + u8 two_plane_read; + u8 read_cache; + u8 read_unique_id; + u8 dq_imped; + u8 dq_imped_num_settings; + u8 dq_imped_feat_addr; + u8 rb_pulldown_strength; + u8 rb_pulldown_strength_feat_addr; + u8 rb_pulldown_strength_num_settings; + u8 otp_mode; + u8 otp_page_start; + u8 otp_data_prot_addr; + u8 otp_num_pages; + u8 otp_feat_addr; + u8 read_retry_options; + u8 reserved[72]; + u8 param_revision; +} __packed; + +static int micron_nand_setup_read_retry(struct mtd_info *mtd, int retry_mode) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + u8 feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode}; + + return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY, + feature); +} + +/* + * Configure chip properties from Micron vendor-specific ONFI table + */ +static int micron_nand_onfi_init(struct nand_chip *chip) +{ + struct nand_onfi_params *p = &chip->onfi_params; + struct nand_onfi_vendor_micron *micron = (void *)p->vendor; + + if (!chip->onfi_version) + return 0; + + if (le16_to_cpu(p->vendor_revision) < 1) + return 0; + + chip->read_retries = micron->read_retry_options; + chip->setup_read_retry = micron_nand_setup_read_retry; + + return 0; +} + +static int micron_nand_init(struct nand_chip *chip) +{ + struct mtd_info *mtd = nand_to_mtd(chip); + int ret; + + ret = micron_nand_onfi_init(chip); + if (ret) + return ret; + + if (mtd->writesize == 2048) + chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; + + return 0; +} + +const struct nand_manufacturer_ops micron_nand_manuf_ops = { + .init = micron_nand_init, +}; diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 73abb3401649..ec0f77b24bd6 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -388,26 +388,6 @@ struct onfi_ext_param_page { */ } __packed; -struct nand_onfi_vendor_micron { - u8 two_plane_read; - u8 read_cache; - u8 read_unique_id; - u8 dq_imped; - u8 dq_imped_num_settings; - u8 dq_imped_feat_addr; - u8 rb_pulldown_strength; - u8 rb_pulldown_strength_feat_addr; - u8 rb_pulldown_strength_num_settings; - u8 otp_mode; - u8 otp_page_start; - u8 otp_data_prot_addr; - u8 otp_num_pages; - u8 otp_feat_addr; - u8 read_retry_options; - u8 reserved[72]; - u8 param_revision; -} __packed; - struct jedec_ecc_info { u8 ecc_bits; u8 codeword_size; @@ -1161,6 +1141,7 @@ extern struct nand_manufacturers nand_manuf_ids[]; extern const struct nand_manufacturer_ops toshiba_nand_manuf_ops; extern const struct nand_manufacturer_ops samsung_nand_manuf_ops; extern const struct nand_manufacturer_ops hynix_nand_manuf_ops; +extern const struct nand_manufacturer_ops micron_nand_manuf_ops; int nand_default_bbt(struct mtd_info *mtd); int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); From patchwork Fri Jul 22 16:10:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2240 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ej1-f70.google.com (mail-ej1-f70.google.com [209.85.218.70]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 02EEB3F047 for ; Fri, 22 Jul 2022 18:11:22 +0200 (CEST) Received: by mail-ej1-f70.google.com with SMTP id sa19-20020a1709076d1300b0072f703aef3asf2088063ejc.14 for ; Fri, 22 Jul 2022 09:11:22 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1658506281; cv=pass; d=google.com; s=arc-20160816; b=XWVy1pe/blk7CM1PelMqHNIw/ZYohCjW5oEer6JkMBvNBH/PI674MrinzM8QcrSkWi wJ3X6/RVbMN4GYQdxzyC4jBgwZCyZ/VT0QfdGL8HVCPnFbYXhUZxH5VwF1awcCSILzZ/ FV1qR3M8JUlVwEL3YBiHbPvFEuaNSn9c9Eigdkaxz2n/Owl1M2vQ3oIdtmQD/Tan2fEf N8V5yHohVFGfNyxwwjWKtpC+anQ4hy6qTEGXfhd5DFsowZMuG9c/r92ckGKbc+xMgYUc jm5Ac5bR7HX/EAPrnfWjMeqEAl57EBvZi+mGEfROB7r0QoLsDrUwTz5S6PztfCwxEs1B wQVg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Qv6Mm57Rzn6Vj7g2r05yIl59P06yLg0yIVlQvyx2GkA=; b=WdgRVmciPo1pPETdayGYnjcwckL6HZaDiujZ/Zr80Ud+0CcLZW2hvtJgDTi/zfD8Qo C1ZgDVw4c6CX2IE61kzwVut2kxPZE2DR8B0T5MRHrKGsjQm+9krml/2L+2+RM0fxpY0o QlDQChfkvCIzC7RE1O8zI/USQ8I5kYYtbUAN3pxStLs6NxU5K9neySh2pzNTw2wt3Bzg i6fxii6HAC8TqtgZwzHYxkNfU2l+ACwvkWiPQ9qt13c+lToJ3teOmFwEf4klJFEkUr6l rIfsKnnMW89wls19IHmNnNvxJLZZi1o77k0Zj4+4f8PYeO9toVaK79HhWp1yeKcRAC8X GIPA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=DrAbXCKd; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=Qv6Mm57Rzn6Vj7g2r05yIl59P06yLg0yIVlQvyx2GkA=; b=JINGJcqpDibJBLj0GcIum9csebfaO78BpZJ3zouQEvhzefvJz06kpDctGlA78p6hEO bDgJpHWgKP11oZCm9KA7C9XpkuI+u4h7rUa7VGpj+3uB0xdRNbyhDQPJl/YTLUA7Rfpm WsfP3kiWPSgoRssKi6iYC3Avq3hVP+T7nk9Gc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=Qv6Mm57Rzn6Vj7g2r05yIl59P06yLg0yIVlQvyx2GkA=; b=WjV2Q4k4GGSbppzT/FsX2Jity8ZB7jJsvUrs3He9RI1d98Z+CtqVxxlRGwFzqDvoeB QD7cKgRkBRWXvMA+hvd3tJo0KQl1B0ebsmdIRHoU0TFM5gVjmwzVxYIbHVPwT5aUlsiO ZuYokYzPuxu7KXuZah3Fx7lF15uW0cPya93NGu9whfldFcER4l9bItT6FtkW9Mi/euoz eWaG9GMspnfKGjespgvplAj9fcnD86hBk2lIpXW6+Np3QbNehWXaiyfgqk91fIlfZyjl efsb/EnAcaUvX0uHMTTb/jc6VLp1ybpDX6JXkEf5n0Dk8kxbdXal0YDoAcP6yX6CA+VR 6ZQA== X-Gm-Message-State: AJIora8fjWWYG1EVpr2R58pPoQ73+4uSTPFGFhj3fDKpzl1s+aTbTs5K PGbSDM88BVWVX49V96oxceEyVl7O X-Google-Smtp-Source: AGRyM1s+hTumWzNGWLYDmukb2YcsfLUsg7vwca35f1/4PGzYH8uDri5M9WPaLxOBKkTlbrpcetunjg== X-Received: by 2002:aa7:cd0a:0:b0:43b:c49d:22b6 with SMTP id b10-20020aa7cd0a000000b0043bc49d22b6mr566565edw.155.1658506281843; Fri, 22 Jul 2022 09:11:21 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:906:f741:b0:726:2c39:8546 with SMTP id jp1-20020a170906f74100b007262c398546ls3077791ejb.8.-pod-prod-gmail; Fri, 22 Jul 2022 09:11:20 -0700 (PDT) X-Received: by 2002:a17:906:5d16:b0:72f:9f40:d1eb with SMTP id g22-20020a1709065d1600b0072f9f40d1ebmr470120ejt.403.1658506280733; Fri, 22 Jul 2022 09:11:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1658506280; cv=none; d=google.com; s=arc-20160816; b=Fz5hc7k+ywgDMRZZuIvQe3FPrBVYHgdzzC/JwzYLA3me+xpn1XCAmVQhb5uvdahUBR hUBXTiQPzQt0PDHflDyFwghJI047mTep2vuKH2TE0uESEPFTcEynrQvLafCXz9+rqos9 0D77HaP29zNzljopRSY4UcYrx8Uzd4yVspOuw+S6paNH8iRqtvOm6MD2V00RC2rYMn/P FAmReO68oU3CWAEXdR1zDjCyM2VuuXc7EQ7UlRCjzLWhP4qO8fk3W4xEvOQT875r4M1c n1h3juGYnWt9gsMNEkBOOVblRP1Q2eQADUMpQmwmVghR0lJumdOQg4zEzuJb0Q1ces39 UHEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=AGMOz1nf65DdLdw6QFGuWgesKp0anQ6glN4wf5lFcaQ=; b=LK9tFYXBAqs1jm60KmPXkZgywEjJWrHrsCVahaPtnMdzW78YdNxmQtANU/R8N25ai3 trJTMOS9/4d4oUhwN+ZmOIMPilDDzvGLxRDg7AuTYCzLC2u+wumsLEnXlA1iXN5pCZ54 rrWRQ56sApVRjyXFp8wQILkFH7EpBmEWJY7FeuGPt0li9P4vR9vVFyve+WBVPncqOpTB MQS/5ibb2+pISMjmKe9jbesFz4j2sjk3kwhZqWiIEldJ2OIAoUuS0v8RtLzeh4Xmcobx 1+9vUOgyIxxwUAE+uUwykyqacTxhnO44NqRNubOkspuvRnm3sDtOr5H/aZzZw2ZzA6fk bMeQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=DrAbXCKd; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id j23-20020a17090643d700b0072f15f31f0asor2184430ejn.118.2022.07.22.09.11.20 for (Google Transport Security); Fri, 22 Jul 2022 09:11:20 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:907:7394:b0:72b:3e52:6262 with SMTP id er20-20020a170907739400b0072b3e526262mr493865ejc.756.1658506280456; Fri, 22 Jul 2022 09:11:20 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.pdxnet.pdxeng.ch (host-87-14-98-67.retail.telecomitalia.it. [87.14.98.67]) by smtp.gmail.com with ESMTPSA id d19-20020a170906305300b006fe8ac6bc69sm2174025ejd.140.2022.07.22.09.11.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Jul 2022 09:11:19 -0700 (PDT) From: Dario Binacchi To: u-boot@lists.denx.de Cc: Amarula patchwork , michael@amarulasolutions.com, Dario Binacchi , Patrice Chotard , Simon Glass , Wolfgang Denk Subject: [PATCH v4 11/14] mtd: nand: Move AMD/Spansion specific init/detection logic in nand_amd.c Date: Fri, 22 Jul 2022 18:10:05 +0200 Message-Id: <20220722161009.2686504-12-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220722161009.2686504-1-dario.binacchi@amarulasolutions.com> References: <20220722161009.2686504-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=DrAbXCKd; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Michael Trimarchi Upstream linux commit 229204da53b31d. Move AMD/Spansion specific initialization/detection logic into nand_amd.c. This is part of the "separate vendor specific code from core" cleanup process. Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi --- (no changes since v3) Changes in v3: - Use commit sha1 with 13 digits. - Add the SPDX-License-Identifier tag. - Fix code style warnings raised by patman. Changes in v2: - Use short-commit form - Remove linux info. Uboot seems that backport without add this extra information. - Adjust the include file in nand_amd. drivers/mtd/nand/raw/Makefile | 4 ++- drivers/mtd/nand/raw/nand_amd.c | 52 ++++++++++++++++++++++++++++++++ drivers/mtd/nand/raw/nand_base.c | 17 +---------- drivers/mtd/nand/raw/nand_ids.c | 2 +- include/linux/mtd/rawnand.h | 1 + 5 files changed, 58 insertions(+), 18 deletions(-) create mode 100644 drivers/mtd/nand/raw/nand_amd.c diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 8ef30b45fd2d..9c2ced9925d8 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -14,7 +14,8 @@ obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o obj-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o -obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_hynix.o nand_micron.o nand_samsung.o nand_toshiba.o +obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_amd.o nand_hynix.o nand_micron.o \ + nand_samsung.o nand_toshiba.o obj-$(CONFIG_SPL_NAND_IDENT) += nand_ids.o nand_timings.o obj-$(CONFIG_TPL_NAND_INIT) += nand.o ifeq ($(CONFIG_SPL_ENV_SUPPORT),y) @@ -31,6 +32,7 @@ obj-y += nand_ids.o obj-y += nand_util.o obj-y += nand_ecc.o obj-y += nand_base.o +obj-y += nand_amd.o obj-y += nand_hynix.o obj-y += nand_micron.o obj-y += nand_samsung.o diff --git a/drivers/mtd/nand/raw/nand_amd.c b/drivers/mtd/nand/raw/nand_amd.c new file mode 100644 index 000000000000..e02b8c79dba2 --- /dev/null +++ b/drivers/mtd/nand/raw/nand_amd.c @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Free Electrons + * Copyright (C) 2017 NextThing Co + * + * Author: Boris Brezillon + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +static void amd_nand_decode_id(struct nand_chip *chip) +{ + struct mtd_info *mtd = nand_to_mtd(chip); + + nand_decode_ext_id(chip); + + /* + * Check for Spansion/AMD ID + repeating 5th, 6th byte since + * some Spansion chips have erasesize that conflicts with size + * listed in nand_ids table. + * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) + */ + if (chip->id.data[4] != 0x00 && chip->id.data[5] == 0x00 && + chip->id.data[6] == 0x00 && chip->id.data[7] == 0x00 && + mtd->writesize == 512) { + mtd->erasesize = 128 * 1024; + mtd->erasesize <<= ((chip->id.data[3] & 0x03) << 1); + } +} + +static int amd_nand_init(struct nand_chip *chip) +{ + if (nand_is_slc(chip)) + chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; + + return 0; +} + +const struct nand_manufacturer_ops amd_nand_manuf_ops = { + .detect = amd_nand_decode_id, + .init = amd_nand_init, +}; diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index fe7e049d4064..68e6f4f14347 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4200,7 +4200,6 @@ static int nand_manufacturer_init(struct nand_chip *chip) static void nand_decode_id(struct nand_chip *chip, struct nand_flash_dev *type) { struct mtd_info *mtd = &chip->mtd; - int maf_id = chip->id.data[0]; mtd->erasesize = type->erasesize; mtd->writesize = type->pagesize; @@ -4208,19 +4207,6 @@ static void nand_decode_id(struct nand_chip *chip, struct nand_flash_dev *type) /* All legacy ID NAND are small-page, SLC */ chip->bits_per_cell = 1; - - /* - * Check for Spansion/AMD ID + repeating 5th, 6th byte since - * some Spansion chips have erasesize that conflicts with size - * listed in nand_ids table. - * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) - */ - if (maf_id == NAND_MFR_AMD && chip->id.data[4] != 0x00 && - chip->id.data[5] == 0x00 && chip->id.data[6] == 0x00 && - chip->id.data[7] == 0x00 && mtd->writesize == 512) { - mtd->erasesize = 128 * 1024; - mtd->erasesize <<= ((chip->id.data[3] & 0x03) << 1); - } } /* @@ -4245,8 +4231,7 @@ static void nand_decode_bbm_options(struct mtd_info *mtd, * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba, * AMD/Spansion, and Macronix. All others scan only the first page. */ - if (nand_is_slc(chip) && - (maf_id == NAND_MFR_AMD || maf_id == NAND_MFR_MACRONIX)) + if (nand_is_slc(chip) && maf_id == NAND_MFR_MACRONIX) chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; } diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c index bb5ac8337fde..c78f2e088040 100644 --- a/drivers/mtd/nand/raw/nand_ids.c +++ b/drivers/mtd/nand/raw/nand_ids.c @@ -196,7 +196,7 @@ struct nand_manufacturers nand_manuf_ids[] = { {NAND_MFR_STMICRO, "ST Micro"}, {NAND_MFR_HYNIX, "Hynix", &hynix_nand_manuf_ops}, {NAND_MFR_MICRON, "Micron", µn_nand_manuf_ops}, - {NAND_MFR_AMD, "AMD/Spansion"}, + {NAND_MFR_AMD, "AMD/Spansion", &amd_nand_manuf_ops}, {NAND_MFR_MACRONIX, "Macronix"}, {NAND_MFR_EON, "Eon"}, {NAND_MFR_SANDISK, "SanDisk"}, diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index ec0f77b24bd6..bb1a359a9c14 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -1142,6 +1142,7 @@ extern const struct nand_manufacturer_ops toshiba_nand_manuf_ops; extern const struct nand_manufacturer_ops samsung_nand_manuf_ops; extern const struct nand_manufacturer_ops hynix_nand_manuf_ops; extern const struct nand_manufacturer_ops micron_nand_manuf_ops; +extern const struct nand_manufacturer_ops amd_nand_manuf_ops; int nand_default_bbt(struct mtd_info *mtd); int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); From patchwork Fri Jul 22 16:10:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2241 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f71.google.com (mail-ed1-f71.google.com [209.85.208.71]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id EEA463F047 for ; Fri, 22 Jul 2022 18:11:22 +0200 (CEST) Received: by mail-ed1-f71.google.com with SMTP id q16-20020a056402519000b0043bd73ad1basf570674edd.3 for ; Fri, 22 Jul 2022 09:11:22 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1658506282; cv=pass; d=google.com; s=arc-20160816; b=MsIXV0yS41K2KOczudIR4AnepQC656zNsYF1llEHkedvISspDygxlnNpPCu5CeUO8I rTKMamQeExbBbl2Yehh6k4b1oHb1n+dQ9Kre6JDUyk6W5dyILXZ0GO422c/cflljWKDH rD3TfntqQyKuCntFoCsSHJyUNJ7O4ccibMqAlo2E07GiAqRgVpsAepyR/KLYh9clbbUv rJCeH4BQeFRByg9M3A5qGSK13U+P+bi14YxybOHrK+Yqp8fPV5bn5gm06zKRyEN1KUhu w8ggSO+8IqFwUNqlQZuItPzkEx8ayzET/30zgSLSJzcf+1NTizcVvbvDcfTRsJ1joDWs e4iQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=+nvoBi4Ck3hTBZOmwahF77J02W60BQfsqSgVfcZvnEU=; b=Ef+KyvVWDs4+49Li+PSiIdTcvJ+7BOi/cib8bngC5UNfh1Cv1uXsKpJge30IyjeW3v tkMOpJ1+Cq6uOYaW60SHqi1hCNrpaAlGESXQYCEGLQGTueSfRtmR1F9NQY0DFHXWVJ4C fIEGkB6NgNtM0FzterUOt74tqs4qFf8H8f4qZBakwpBkQCR0gOpHVEJ96at/2CSKeuCF I+AlNXkhdUVmD3coJLfpxYI33jnBr5Jib9XnXN2ri23JGC5eu9C+nYxCFafLHTZxZL+C tvoAKJ1mwiIxhedQF9pNtchQNGOLEeLwqiJvF+CBZw9B3uv4DzfmEsGbVlj5OFs3lTTn vsLQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=kG3r6GTv; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=+nvoBi4Ck3hTBZOmwahF77J02W60BQfsqSgVfcZvnEU=; b=GroQ9MULuxSXgxZGw2Lz/8iDfhMtDRM0VZiA19gtgjd0CNoTKcl6IWoeBQ1ZGlqML6 CS2AQb+fwjLf7GEfTnGH9B7DoJY3o6og3ZG3rWH1XHm3MKYprRhB1/fgseUdaFibXiDi Tb/KUdExnRbDaa1ysZ8RBGlontrGxLaXWhdj0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=+nvoBi4Ck3hTBZOmwahF77J02W60BQfsqSgVfcZvnEU=; b=JoYJXhRficiatt56Ru2ZDFTBcGIKSF4aoE2VuvBbUrOexcWMY/6Wq5XkimxeZmU4IC H04jCkZBqeT3Zw2Ow8vvxWe+OoIEL4WJkjFT79UB6/s7D15rgWGJrPUX+Yx6glWfLsDK z+WwxIV5SBWmFmJ19p8loCiY501ghQguew4Jo0HiuHaegQafY0QtAxGIL10R6x63zJ4q jHzChsKeeXrNu8gifeGrB/5TsOUpApa65b/C8l07P3fpGhp5m6oIemrwfLgWdRQ0qCkd 2nUg83DjZijZ15vn+DmSKOHmSqVHtbypi486gVr1i/9DQmfuHDaOXpCO85M6jIqxEF0T 4ejg== X-Gm-Message-State: AJIora+by6BWOynFsxWNvx3pqySlC++d4MvMQPDWq134BQ1dMtbm4tWf 78A4uukNjlxl+S18VKuSDliBEAT/ X-Google-Smtp-Source: AGRyM1sSJsajtysNlpDgP503dGQRgqhm54Lx/kwUm/1HS70lt3jasu5iSHeatMhRDQdhRDaQ+vVImg== X-Received: by 2002:a17:907:6e02:b0:72b:9f16:1bc5 with SMTP id sd2-20020a1709076e0200b0072b9f161bc5mr498250ejc.676.1658506282856; Fri, 22 Jul 2022 09:11:22 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a50:d0c9:0:b0:43a:6e16:5059 with SMTP id g9-20020a50d0c9000000b0043a6e165059ls2107502edf.2.-pod-prod-gmail; Fri, 22 Jul 2022 09:11:22 -0700 (PDT) X-Received: by 2002:a05:6402:5193:b0:43a:eaa8:74b2 with SMTP id q19-20020a056402519300b0043aeaa874b2mr592802edd.111.1658506281853; Fri, 22 Jul 2022 09:11:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1658506281; cv=none; d=google.com; s=arc-20160816; b=NpR56WX9wZpVpJgQpkdHTUsQ8il0VvSKygMfJCU9ckfRLpzjzbAYzupABgPjhTofYK /iGPzmqkI1+xpbRnjbUkPSrtzwJNWmGBZlzoL6oKZF7M0Xk1RaL0QveQ7GsGbOxN8DcP t+pY5yQo6/2tyiWaBdCGnRHL6Sk9m4hsQOPd1z7cpump+7OE3zu4jpEPIcvNoHLznlZU dfdzN9nGXjKSxqft95FfFuaiRhJZBAKJ8eRaP3bmMrhzbIT7mus182DS2voe1VgAuuEE /8YKlgLuXj8cqikyQ+FEOuepWPfcfFp76rD6BVCXx0XdqC85rLf7IuyBgCj33ZC4xDIL 2ruA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=pTvdFFgd/7bGiFQ+kUeBl/2HLPoUTLMSal7ljPTITS8=; b=eLQsLUoiIHzNT/7cmZ5EXowLfzRpWmWpvKYZ/ARqL3DiQcotANRZ34ziQIuI5rlOT4 IJr9W+jRZtieXJ8uf42REPAohe2DnUZii3gQTZ1BjSBItOEaQMr76f5nPGmay4HlT5GC bV1TuNYDRib+DJieMvNl1DfF7Nn+QDXfKJheCk8ZDRhkeqa5yeYAFTHKeD6/EqsZZNsB fVkb+i5bPL+vI1fjaxeauno4s4D5ChqvbYpYCmidUO8IDS/n2+UYa9HpsUBNhdePYD/B Qw4c69miwdDNBS1XJoLFsZUDLu2yyjG4ca4GiyDC6xBErIXmFEGjymTThueZ2SdCGn1K +lPQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=kG3r6GTv; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id u14-20020a17090617ce00b0072b17278302sor2190520eje.78.2022.07.22.09.11.21 for (Google Transport Security); Fri, 22 Jul 2022 09:11:21 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:907:7243:b0:72f:21d7:d122 with SMTP id ds3-20020a170907724300b0072f21d7d122mr483090ejc.271.1658506281616; Fri, 22 Jul 2022 09:11:21 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.pdxnet.pdxeng.ch (host-87-14-98-67.retail.telecomitalia.it. [87.14.98.67]) by smtp.gmail.com with ESMTPSA id d19-20020a170906305300b006fe8ac6bc69sm2174025ejd.140.2022.07.22.09.11.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Jul 2022 09:11:21 -0700 (PDT) From: Dario Binacchi To: u-boot@lists.denx.de Cc: Amarula patchwork , michael@amarulasolutions.com, Dario Binacchi , Patrice Chotard , Simon Glass , Wolfgang Denk Subject: [PATCH v4 12/14] mtd: nand: Move Macronix specific initialization in nand_macronix.c Date: Fri, 22 Jul 2022 18:10:06 +0200 Message-Id: <20220722161009.2686504-13-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220722161009.2686504-1-dario.binacchi@amarulasolutions.com> References: <20220722161009.2686504-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=kG3r6GTv; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Michael Trimarchi Upstream linux commit 3b5206f4be9b65. Move Macronix specific initialization logic into nand_macronix.c. This is part of the "separate vendor specific code from core" cleanup process. Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi --- (no changes since v3) Changes in v3: - Use commit sha1 with 13 digits. - Add the SPDX-License-Identifier tag. - Fix code style warnings raised by patman. Changes in v2: - Use short-commit form - Remove linux info. Uboot seems that backport without add this extra information. - Adjust the include file in nand_macronix. drivers/mtd/nand/raw/Makefile | 4 +++- drivers/mtd/nand/raw/nand_base.c | 11 ---------- drivers/mtd/nand/raw/nand_ids.c | 2 +- drivers/mtd/nand/raw/nand_macronix.c | 31 ++++++++++++++++++++++++++++ include/linux/mtd/rawnand.h | 1 + 5 files changed, 36 insertions(+), 13 deletions(-) create mode 100644 drivers/mtd/nand/raw/nand_macronix.c diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 9c2ced9925d8..a398aa9d8864 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -14,7 +14,8 @@ obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o obj-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o -obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_amd.o nand_hynix.o nand_micron.o \ +obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_amd.o nand_hynix.o \ + nand_macronix.o nand_micron.o \ nand_samsung.o nand_toshiba.o obj-$(CONFIG_SPL_NAND_IDENT) += nand_ids.o nand_timings.o obj-$(CONFIG_TPL_NAND_INIT) += nand.o @@ -34,6 +35,7 @@ obj-y += nand_ecc.o obj-y += nand_base.o obj-y += nand_amd.o obj-y += nand_hynix.o +obj-y += nand_macronix.o obj-y += nand_micron.o obj-y += nand_samsung.o obj-y += nand_toshiba.o diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 68e6f4f14347..4b09a1128827 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4217,22 +4217,11 @@ static void nand_decode_id(struct nand_chip *chip, struct nand_flash_dev *type) static void nand_decode_bbm_options(struct mtd_info *mtd, struct nand_chip *chip) { - int maf_id = chip->id.data[0]; - /* Set the bad block position */ if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16)) chip->badblockpos = NAND_LARGE_BADBLOCK_POS; else chip->badblockpos = NAND_SMALL_BADBLOCK_POS; - - /* - * Bad block marker is stored in the last page of each block on Samsung - * and Hynix MLC devices; stored in first two pages of each block on - * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba, - * AMD/Spansion, and Macronix. All others scan only the first page. - */ - if (nand_is_slc(chip) && maf_id == NAND_MFR_MACRONIX) - chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; } static inline bool is_full_id_nand(struct nand_flash_dev *type) diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c index c78f2e088040..7602dd30f169 100644 --- a/drivers/mtd/nand/raw/nand_ids.c +++ b/drivers/mtd/nand/raw/nand_ids.c @@ -197,7 +197,7 @@ struct nand_manufacturers nand_manuf_ids[] = { {NAND_MFR_HYNIX, "Hynix", &hynix_nand_manuf_ops}, {NAND_MFR_MICRON, "Micron", µn_nand_manuf_ops}, {NAND_MFR_AMD, "AMD/Spansion", &amd_nand_manuf_ops}, - {NAND_MFR_MACRONIX, "Macronix"}, + {NAND_MFR_MACRONIX, "Macronix", ¯onix_nand_manuf_ops}, {NAND_MFR_EON, "Eon"}, {NAND_MFR_SANDISK, "SanDisk"}, {NAND_MFR_INTEL, "Intel"}, diff --git a/drivers/mtd/nand/raw/nand_macronix.c b/drivers/mtd/nand/raw/nand_macronix.c new file mode 100644 index 000000000000..dc972e590922 --- /dev/null +++ b/drivers/mtd/nand/raw/nand_macronix.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Free Electrons + * Copyright (C) 2017 NextThing Co + * + * Author: Boris Brezillon + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +static int macronix_nand_init(struct nand_chip *chip) +{ + if (nand_is_slc(chip)) + chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; + + return 0; +} + +const struct nand_manufacturer_ops macronix_nand_manuf_ops = { + .init = macronix_nand_init, +}; diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index bb1a359a9c14..aa45558b3d41 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -1143,6 +1143,7 @@ extern const struct nand_manufacturer_ops samsung_nand_manuf_ops; extern const struct nand_manufacturer_ops hynix_nand_manuf_ops; extern const struct nand_manufacturer_ops micron_nand_manuf_ops; extern const struct nand_manufacturer_ops amd_nand_manuf_ops; +extern const struct nand_manufacturer_ops macronix_nand_manuf_ops; int nand_default_bbt(struct mtd_info *mtd); int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs); From patchwork Fri Jul 22 16:10:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2242 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ej1-f71.google.com (mail-ej1-f71.google.com [209.85.218.71]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id D6B153F047 for ; Fri, 22 Jul 2022 18:11:24 +0200 (CEST) Received: by mail-ej1-f71.google.com with SMTP id hs16-20020a1709073e9000b0072b73a28465sf2107620ejc.17 for ; Fri, 22 Jul 2022 09:11:24 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1658506284; cv=pass; d=google.com; s=arc-20160816; b=S1RjUvF6l1bI6/3LGhEwIDEBLM0UwFd+KDiqT2aaYvNT9uq13h7VDF5n5Qg5673y0/ 0EV7j1YpNRoSk9jeAzJWI3PdWSozEQcH5KgrAs5zPLm5bt0/aCBpwhVldhQXWZ5dIncC j6R1kUQm/Im69whQMrtFKSYoAG9UU14EB/ZzQMFD5HaxiPT9xEmyE0b8LE+lBYcC+Dry GVBPv8DDfETS7vwtg3LcscBE0lW/uCni31ESIb0P8kmxj8I8GVWq2fC4UTZTu2PhWfrc yVyeoaBGbKgs7i3KE/T2KRq4iM3G7CQtxtuiLhVe0BDQ3S+/fFedSGAwy6hw3Zld9exH gElw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=2C1VJm1l3z6r5eKWqbtgvXuNzqZfkGTOfeTpMgLc7cE=; b=q6VWa8eYdWEoLnC7rwtgivKvNlJGv+iY7wqmrPEgZTCdsQ7re//xA3g29OKsg4GS0H SlNVut1e4QXVMnCRwrLQNqI6g9K5+dcEW4gxTJ73s2L78cIeJRTGO/u1wgmbMcZ0Kzjo yD4HliU2huvTAT6/fai2ER41+Gtpf/Lfd+uJmoE48dD3Kr4xk8KhG8xoLTcPOzB3roDq tJB2jXzIyaW068RLA6PgmVeqcFYUShPEyZzBSYf/ZAFxNc7NajVItKE0GMvyQeJaMCR6 mVfg4hiIPD66vwxmeqrRsdN9pRh3yP89HRX6PdlpeEGYJYf+qA9cPL8XpSh/TzsNyDHp Pr6g== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=MKrb+6jm; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=2C1VJm1l3z6r5eKWqbtgvXuNzqZfkGTOfeTpMgLc7cE=; b=aNefI1GwZUGfGrbI0rerLmoXtsk55huzfyYDtOkEGyeZsjJfC0dOG3GXuJXUGw8eRW BCwIzmXwKM3oBDbjSJ2LReeQDXADfY/P62xfATUlFhraR6kRfrp0/Iq7wdNgEMUj/BBE 6bVv+t5faKdCRrSUaJxIFsl0uIiAbjcRQ5p4o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=2C1VJm1l3z6r5eKWqbtgvXuNzqZfkGTOfeTpMgLc7cE=; b=K7J9ZriqdlggSDaHsvGjpEGyDtwEM8dxPyx3zYiwcSTJgQUFsWsFrwGtUMIyNtW/zw 8orXSetgIk4LmF0c1RFDHgja1GR+y6FQ9680qMMPDi9cnsWbFAhzkVrDVsMdXb+2pzK7 ZTXRqWjx2hkEqRhWH1hV+F4qBRe8Nr4856KjkhQ3eFu/HBVrktNUaSqiMSCDbsbphGt2 fUB0ucXqzP/jOPEoku41zKrEdg9ysy3idOMf0DoAvgux7fKQmX3cQsGqwnlTdxDDE7tJ Lr6ZzAYpSfZmYADvESZ/ElEIunZFkRAD0RubvUbnfXxNprE0JrMy9VDDJ1jffOjrD2y7 ZfSw== X-Gm-Message-State: AJIora8lpGQsuzCi5/AOzLdW9mQQdUKZvaY2CxhsGuVve7uaSiRHUGCR hFENxMAfunTfrqnNNhicPhGFL6hx X-Google-Smtp-Source: AGRyM1tfJMerzyd9jiYWSJMFtSWmw8TGmmS1poFoeBKt4Q6j0SidMXLThAN0vJS8C6GZS+vo+C2eXw== X-Received: by 2002:a17:906:9b93:b0:72b:8fad:6cf8 with SMTP id dd19-20020a1709069b9300b0072b8fad6cf8mr470407ejc.415.1658506284713; Fri, 22 Jul 2022 09:11:24 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:906:f9c4:b0:72f:b55a:8f8c with SMTP id lj4-20020a170906f9c400b0072fb55a8f8cls60030ejb.6.-pod-prod-gmail; Fri, 22 Jul 2022 09:11:23 -0700 (PDT) X-Received: by 2002:a17:907:2cef:b0:72b:5b3e:3d7a with SMTP id hz15-20020a1709072cef00b0072b5b3e3d7amr474587ejc.293.1658506283576; Fri, 22 Jul 2022 09:11:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1658506283; cv=none; d=google.com; s=arc-20160816; b=oZjK3cSFkEDjBNEyHN70FhNDf2KU5su2XNNeigtx977E/MayO47QROd0c3dh+H7D8+ +S0L9fPLfg1Xwh81KtDOS9Mu+D0qAWRZ4UX809QVsvSoY0SuNP9Mlsv6Gh1uz4iKWM5g +/CmjGG9G0j+l8wfkddmpMZCxAmUI4j2r0CvoVlZc/zuHaYWNItZXV3qwADzmciOYep/ NwRAIXMJ2EKElqPi9xDElL6d889CLPVFUoFMOisiWwtc/WJP47eAOzCn0xSlxb7xW5M5 B4b/drHfPp1TkdMcHtiv8eiTPZnahxtkgseBxQyGSlhydIZ2vUAf6L74eTAAuF4fP9a3 5/sQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=KXBxjCZi8CVVOTeycIO4txADLeL/+95AM1OP9PR9ktQ=; b=omCncQcJr5yKEGiZUV6x+R1ZYCGb0Ej1tAoclgAw2/NEai7hHHWLbh0RH5HTodrZ95 yNOAD4i0EQO8wBgGsF6kqY7LDJjqlM886dg6c3ZSKgqYPYMIMGwWN8GLts4bI7Fbotys ACPrL8G54xfRcbwrrJnVzLtd5UJoiuyJ0ObyEUblVTHMM5ZpOEneqYbxSdAiRqfgZYEX 7ZdT9ya+yQY/mXh0y118AhycIEwQzZS2cSJkIcxUMCRhtY50tFStlYAT8tiOyQ1eR0pG vSgdtonnpbjWGP+ErQGpSSzqGNOokmWy/ExkdkEREuevAuEL8zAwgw58KcXJwcLKzw/k etTw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=MKrb+6jm; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id n18-20020a17090695d200b0072ae925a14esor2164152ejy.52.2022.07.22.09.11.23 for (Google Transport Security); Fri, 22 Jul 2022 09:11:23 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:906:4fc3:b0:72e:eab4:d9d7 with SMTP id i3-20020a1709064fc300b0072eeab4d9d7mr463302ejw.599.1658506283171; Fri, 22 Jul 2022 09:11:23 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.pdxnet.pdxeng.ch (host-87-14-98-67.retail.telecomitalia.it. [87.14.98.67]) by smtp.gmail.com with ESMTPSA id d19-20020a170906305300b006fe8ac6bc69sm2174025ejd.140.2022.07.22.09.11.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Jul 2022 09:11:22 -0700 (PDT) From: Dario Binacchi To: u-boot@lists.denx.de Cc: Amarula patchwork , michael@amarulasolutions.com, Dario Binacchi Subject: [PATCH v4 13/14] mtd: nand: toshiba: Retrieve ECC requirements from extended ID Date: Fri, 22 Jul 2022 18:10:07 +0200 Message-Id: <20220722161009.2686504-14-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220722161009.2686504-1-dario.binacchi@amarulasolutions.com> References: <20220722161009.2686504-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=MKrb+6jm; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Michael Trimarchi Upstream linux commit fb3bff5b407e58. This patch enables support to read the ECC strength and size from the NAND flash using Toshiba Memory SLC NAND extended-ID. This patch is based on the information of the 6th ID byte of the Toshiba Memory SLC NAND. Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi --- (no changes since v3) Changes in v3: - Use commit sha1 with 13 digits. Changes in v2: - Use short-commit form - Remove linux info. Uboot seems that backport without add this extra information. drivers/mtd/nand/raw/nand_toshiba.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/mtd/nand/raw/nand_toshiba.c b/drivers/mtd/nand/raw/nand_toshiba.c index f7426fa59f51..99dc44df671a 100644 --- a/drivers/mtd/nand/raw/nand_toshiba.c +++ b/drivers/mtd/nand/raw/nand_toshiba.c @@ -37,6 +37,32 @@ static void toshiba_nand_decode_id(struct nand_chip *chip) (chip->id.data[5] & 0x7) == 0x6 /* 24nm */ && !(chip->id.data[4] & 0x80) /* !BENAND */) mtd->oobsize = 32 * mtd->writesize >> 9; + + /* + * Extract ECC requirements from 6th id byte. + * For Toshiba SLC, ecc requrements are as follows: + * - 43nm: 1 bit ECC for each 512Byte is required. + * - 32nm: 4 bit ECC for each 512Byte is required. + * - 24nm: 8 bit ECC for each 512Byte is required. + */ + if (chip->id.len >= 6 && nand_is_slc(chip)) { + chip->ecc_step_ds = 512; + switch (chip->id.data[5] & 0x7) { + case 0x4: + chip->ecc_strength_ds = 1; + break; + case 0x5: + chip->ecc_strength_ds = 4; + break; + case 0x6: + chip->ecc_strength_ds = 8; + break; + default: + WARN(1, "Could not get ECC info"); + chip->ecc_step_ds = 0; + break; + } + } } static int toshiba_nand_init(struct nand_chip *chip) From patchwork Fri Jul 22 16:10:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2243 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f70.google.com (mail-ed1-f70.google.com [209.85.208.70]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 89CBD3F047 for ; Fri, 22 Jul 2022 18:11:25 +0200 (CEST) Received: by mail-ed1-f70.google.com with SMTP id m10-20020a056402510a00b0043a93d807ffsf3128741edd.12 for ; Fri, 22 Jul 2022 09:11:25 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1658506285; cv=pass; d=google.com; s=arc-20160816; b=RWGH9m2yFqwkloPZYeJmCXAqGTYFRIBU6Zxf2ayaFbnRWqC8eX+lllsqf7Z8Kq+1wD EYqaAYIEhyJJlVzPBiU5AFPooc/rXf8yjhiTJcUfJCdrE6BYvj9ceshRjtF+cQH35tJq 6b82FD/vgkglnpXiRChr3m0EKQEO3oHzEg/CLBzr7y1POfgytelUe1h6Lq5HqXZEcLE9 1UO9/rUHlez7rxplc/eejJwrMCULXfVxpa00zJk2KPKoflxiJ7HzMkVyPG5OyLQq69F1 DPV/qp7/uAtmheOf/yP1Pth5Fo7wtncd/HkwZ9TdU0I4LYiF5M8Zn5M6YUYtN9ykWkh/ ELAA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=dbktCdYMDXHWMaVMaALY4MVM8fTNM60gGppAaa+WnzU=; b=iw2/6l6BHiU5+wiyazUMIl892e2lRQzLWhe+lttH+QwilUIXyeLR4f7zOYxxYINLbk 8/UAcfE72SV5zVpevt3rofSa/8/Bei8eWvowTI3Tm/OUwiA41IAuw6U28PHJFDIIzS9j i6C3HW9dAi/euUF9j9Z+8WafSfeIUri4I4TfX5CSoOgiONHscBrM9xE0iQDWwPLYpbsW q1AN4SMHENLGOAtjXciZikxokK+b531xn0cUmge7WhMqapJkkNUSEgXtCvjVQBlcHCpx Oyw5WhtIEWa7gr+MNsI/Ufvy1G8kuOC1jRMLkdysppn6Jkod3UxWqDZ/GVCv5QoubWql BjQg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=R3F8Ihbf; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=dbktCdYMDXHWMaVMaALY4MVM8fTNM60gGppAaa+WnzU=; b=h0HNCUeHPPtvjoeXTWrpLnAFDfW7Xj1gsabajmc6jFciSHB/0bp8JYSgO9KewdN818 O1IzNpAx+P58/4ADx+0UPLQrGF+00sWtG69uibhblt0tYHYlMazGL4h8nVUOQKoZtBru 9Yq9njbYFADQuwPShE+cPArNlObqPo1wR6IF4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=dbktCdYMDXHWMaVMaALY4MVM8fTNM60gGppAaa+WnzU=; b=Bc5rZ1/LuVo5M/XoxEIu64zN5CFqagVkjCpsTfuh/8ECuj4fQ2+sEMY3A8Z5pxnoJg 3Tc3Ntx/6YNYGvD+aPfm4M9r+eJVJYNP7bbnh6H1Mshhb/kgIrEt7Vd7ZWXyF9CVQY7X gmjCdkQ9vG8ueRKcXqsJikRwxono5AMC548AT2uN2GkzjIZ7yyky68+x8ma5nzMUbF3+ yLcbN5q8d0y+tm0zWD9bzIRt4Yki09dWTZLmxOb3+Y+CuOfml2WP4zEUjTHW8DxwDOM4 Qjb6NnJji2c+vOYomU7WEb++0agxFWXF7gS7CKWwWtXlanHyAKUUr+MQYRVOm/ckbXQL RtVA== X-Gm-Message-State: AJIora+YjZwUv9jPXUpCBmh8LmbSu32i5w4Xo3sJIFBg2Z/NVLdgdf1h 5a82HVhNbFiuIhqBX1JG9cHKNC+X X-Google-Smtp-Source: AGRyM1v9zUS/xST2TU8CpipElFMD1Xxr0re6zGi59QAzwN9msmfgG579TIVDb/5koU0kr8G6USiEfQ== X-Received: by 2002:a17:907:7617:b0:72b:49fe:fdf7 with SMTP id jx23-20020a170907761700b0072b49fefdf7mr500597ejc.25.1658506285390; Fri, 22 Jul 2022 09:11:25 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a05:6402:11cb:b0:43a:7c1c:8981 with SMTP id j11-20020a05640211cb00b0043a7c1c8981ls2107158edw.0.-pod-prod-gmail; Fri, 22 Jul 2022 09:11:24 -0700 (PDT) X-Received: by 2002:a05:6402:440f:b0:435:2e63:aca9 with SMTP id y15-20020a056402440f00b004352e63aca9mr605153eda.162.1658506284435; Fri, 22 Jul 2022 09:11:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1658506284; cv=none; d=google.com; s=arc-20160816; b=EZNrS67GMM+AW01X55ccRQMCWA2SxhpjE1zzwg0dRhdMMoLViSfKmULDmOToaSOxuQ MZJj39v9lCsrTUnlaz4LxiW9L4w9+1ByJw5bsrFI1Bx6EFGpxjYovgTqSBS6ECE5QCpU ePDFJlgaQ11vQjZMlaZcRe/60kR+eP9XCENlhOaMoBFfrBTVrtxJFnS6OFu729jl5mRw ZWCqZ1LVSJAaiUf7vM6cEpY6+eSamTOEhi+r7nFVmJxdP7HbOGoinpfHAhQQet9MVdUZ CBsdOx9CFBnSrtMK5EQTgdvEYkC/Xdsst2Et7kxKnWsPYz82yzxcLw6mxSThfWxmwRT7 DgmQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=zaSdFJYhjDJ6EOnBrmlwaLGap+wCVxas9PhmsjykTFw=; b=JKVAf1e7Cj3CKesULa77RjbizBkKvnV8Zl3LySVZLm6xrw6V9grfo5UghiegIyP4g8 eEk1bFrkcuhp6FOJycYW2znqP1iRDV6Jh6KsNe4+cL+FJNhMpytc+HnUNwZM5+SV6Cos SEjHQA49SEXoXY5b8fg9pPCdx3ubUfEzJ8TSh9bCZ65ACfZLD1f/o9gzHikeqhlFUPxY SymcniowBP8solEl13cBRfeR0m7f5ZbyZAhcknecCGglmZDaig/zgvuWsdqKNMxmxb9k w0ayM6GjNhmqZzb4ELhHehH96g25iUW38127hlSORDOLUDvWsgjqa1w0hacNAfnh6QFc YrAw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=R3F8Ihbf; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id i26-20020a1709064eda00b006fe8d2e8599sor2175514ejv.29.2022.07.22.09.11.24 for (Google Transport Security); Fri, 22 Jul 2022 09:11:24 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:907:3e11:b0:72b:49d1:2054 with SMTP id hp17-20020a1709073e1100b0072b49d12054mr526591ejc.78.1658506284142; Fri, 22 Jul 2022 09:11:24 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.pdxnet.pdxeng.ch (host-87-14-98-67.retail.telecomitalia.it. [87.14.98.67]) by smtp.gmail.com with ESMTPSA id d19-20020a170906305300b006fe8ac6bc69sm2174025ejd.140.2022.07.22.09.11.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Jul 2022 09:11:23 -0700 (PDT) From: Dario Binacchi To: u-boot@lists.denx.de Cc: Amarula patchwork , michael@amarulasolutions.com, Dario Binacchi Subject: [PATCH v4 14/14] mtd: decommission the NAND museum Date: Fri, 22 Jul 2022 18:10:08 +0200 Message-Id: <20220722161009.2686504-15-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220722161009.2686504-1-dario.binacchi@amarulasolutions.com> References: <20220722161009.2686504-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=R3F8Ihbf; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Michael Trimarchi Upstream linux commit f7025a43a9da26. The MTD subsystem has its own small museum of ancient NANDs in a form of the CONFIG_MTD_NAND_MUSEUM_IDS configuration option. The museum contains stone age NANDs with 256 bytes pages, as well as iron age NANDs with 512 bytes per page and up to 8MiB page size. It is with great sorrow that I inform you that the museum is being decommissioned. The MTD subsystem is out of budget for Kconfig options and already has too many of them, and there is a general kernel trend to simplify the configuration menu. We remove the stone age exhibits along with closing the museum REMARK Don't apply this part from upstream: Some of the iron age ones are transferred to the regular NAND depot. Namely, only those which have unique device IDs are transferred, and the ones which have conflicting device IDs are removed. Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi --- (no changes since v3) Changes in v3: - Use commit sha1 with 13 digits. - Wrap commit description to a maximum of 75 chars. Changes in v2: - Use short-commit form. - Remove linux info. Uboot seems that backport without add this extra information. drivers/mtd/nand/raw/nand_ids.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c index 7602dd30f169..4dece1b20676 100644 --- a/drivers/mtd/nand/raw/nand_ids.c +++ b/drivers/mtd/nand/raw/nand_ids.c @@ -24,16 +24,6 @@ * extended chip ID. */ struct nand_flash_dev nand_flash_ids[] = { -#ifdef CONFIG_MTD_NAND_MUSEUM_IDS - LEGACY_ID_NAND("NAND 1MiB 5V 8-bit", 0x6e, 1, SZ_4K, SP_OPTIONS), - LEGACY_ID_NAND("NAND 2MiB 5V 8-bit", 0x64, 2, SZ_4K, SP_OPTIONS), - LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xe8, 1, SZ_4K, SP_OPTIONS), - LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xec, 1, SZ_4K, SP_OPTIONS), - LEGACY_ID_NAND("NAND 2MiB 3,3V 8-bit", 0xea, 2, SZ_4K, SP_OPTIONS), - LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xd5, 4, SZ_8K, SP_OPTIONS), - - LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xe6, 8, SZ_8K, SP_OPTIONS), -#endif /* * Some incompatible NAND chips share device ID's and so must be * listed by full ID. We list them first so that we can easily identify