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[37.181.33.55]) by smtp.gmail.com with ESMTPSA id q22-20020a17090676d600b006fece722508sm7317678ejn.135.2022.07.27.02.37.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Jul 2022 02:37:51 -0700 (PDT) From: Michael Trimarchi To: dario.binacchi@amarulasolutions.com, Tommaso Merciai , linux-amarula@amarulasolutions.com Subject: [PATCH 1/7] mtd: nand: Rename the nand_manufacturers struct Date: Wed, 27 Jul 2022 11:37:42 +0200 Message-Id: <20220727093748.1415135-2-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220727093748.1415135-1-michael@amarulasolutions.com> References: <20220727093748.1415135-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=jmeQOnnq; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Upstream linux commit 8cfb9ab68f9070. Drop the 's' at the end of nand_manufacturers since the struct is actually describing a single manufacturer, not a manufacturer table. Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/nand_base.c | 4 ++-- drivers/mtd/nand/raw/nand_ids.c | 2 +- include/linux/mtd/rawnand.h | 8 ++++---- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 4b09a11288..9d8ccfda53 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4261,7 +4261,7 @@ static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, * Returns a nand_manufacturer_desc object if the manufacturer is defined * in the NAND manufacturers database, NULL otherwise. */ -static const struct nand_manufacturers *nand_get_manufacturer_desc(u8 id) +static const struct nand_manufacturer *nand_get_manufacturer_desc(u8 id) { int i; @@ -4281,7 +4281,7 @@ struct nand_flash_dev *nand_get_flash_type(struct nand_chip *chip, int *maf_id, struct nand_flash_dev *type) { struct mtd_info *mtd = &chip->mtd; - const struct nand_manufacturers *manufacturer_desc; + const struct nand_manufacturer *manufacturer_desc; int busw, ret; u8 *id_data = chip->id.data; diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c index 4dece1b206..d0cfacc69b 100644 --- a/drivers/mtd/nand/raw/nand_ids.c +++ b/drivers/mtd/nand/raw/nand_ids.c @@ -177,7 +177,7 @@ struct nand_flash_dev nand_flash_ids[] = { }; /* Manufacturer IDs */ -struct nand_manufacturers nand_manuf_ids[] = { +struct nand_manufacturer nand_manuf_ids[] = { {NAND_MFR_TOSHIBA, "Toshiba", &toshiba_nand_manuf_ops}, {NAND_MFR_SAMSUNG, "Samsung", &samsung_nand_manuf_ops}, {NAND_MFR_FUJITSU, "Fujitsu"}, diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index aa45558b3d..8dc2d81dba 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -976,7 +976,7 @@ struct nand_chip { void *priv; struct { - const struct nand_manufacturers *desc; + const struct nand_manufacturer *desc; void *priv; } manufacturer; }; @@ -1124,19 +1124,19 @@ struct nand_flash_dev { }; /** - * struct nand_manufacturers - NAND Flash Manufacturer ID Structure + * struct nand_manufacturer - NAND Flash Manufacturer ID Structure * @name: Manufacturer name * @id: manufacturer ID code of device. * @ops: manufacturer operations */ -struct nand_manufacturers { +struct nand_manufacturer { int id; char *name; const struct nand_manufacturer_ops *ops; }; extern struct nand_flash_dev nand_flash_ids[]; -extern struct nand_manufacturers nand_manuf_ids[]; +extern struct nand_manufacturer nand_manuf_ids[]; extern const struct nand_manufacturer_ops toshiba_nand_manuf_ops; extern const struct nand_manufacturer_ops samsung_nand_manuf_ops; From patchwork Wed Jul 27 09:37:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Nazzareno Trimarchi X-Patchwork-Id: 2263 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ej1-f69.google.com (mail-ej1-f69.google.com [209.85.218.69]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 282E33F1F7 for ; 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[37.181.33.55]) by smtp.gmail.com with ESMTPSA id q22-20020a17090676d600b006fece722508sm7317678ejn.135.2022.07.27.02.37.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Jul 2022 02:37:52 -0700 (PDT) From: Michael Trimarchi To: dario.binacchi@amarulasolutions.com, Tommaso Merciai , linux-amarula@amarulasolutions.com Subject: [PATCH 2/7] mtd: nand: change return type of nand_get_flash_type() to int Date: Wed, 27 Jul 2022 11:37:43 +0200 Message-Id: <20220727093748.1415135-3-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220727093748.1415135-1-michael@amarulasolutions.com> References: <20220727093748.1415135-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=O2y1jS1V; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Upstream linux commit 4722c0e958e636. The returned "type" is never used in nand_scan_ident() and spl code Make nand_get_flash_type() simply return an integer value in order to avoid unnecessary ERR_PTR/PTR_ERR dance. Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/mt7621_nand.c | 10 +++++----- drivers/mtd/nand/raw/mxs_nand_spl.c | 8 ++++---- drivers/mtd/nand/raw/nand_base.c | 28 +++++++++++++--------------- include/linux/mtd/rawnand.h | 5 ++--- 4 files changed, 24 insertions(+), 27 deletions(-) diff --git a/drivers/mtd/nand/raw/mt7621_nand.c b/drivers/mtd/nand/raw/mt7621_nand.c index 9763ae6dc5..a4a0bce35d 100644 --- a/drivers/mtd/nand/raw/mt7621_nand.c +++ b/drivers/mtd/nand/raw/mt7621_nand.c @@ -1184,13 +1184,13 @@ int mt7621_nfc_spl_post_init(struct mt7621_nfc *nfc) { struct nand_chip *nand = &nfc->nand; int nand_maf_id, nand_dev_id; - struct nand_flash_dev *type; + int ret; - type = nand_get_flash_type(nand, &nand_maf_id, - &nand_dev_id, NULL); + ret = nand_get_flash_type(nand, &nand_maf_id, + &nand_dev_id, NULL); - if (IS_ERR(type)) - return PTR_ERR(type); + if (ret) + return ret; nand->numchips = 1; nand->mtd.size = nand->chipsize; diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c b/drivers/mtd/nand/raw/mxs_nand_spl.c index 3daacbb330..773d375fc2 100644 --- a/drivers/mtd/nand/raw/mxs_nand_spl.c +++ b/drivers/mtd/nand/raw/mxs_nand_spl.c @@ -81,13 +81,13 @@ static int mxs_flash_full_ident(struct mtd_info *mtd) { int nand_maf_id, nand_dev_id; struct nand_chip *chip = mtd_to_nand(mtd); - struct nand_flash_dev *type; + int ret; - type = nand_get_flash_type(mtd, chip, &nand_maf_id, &nand_dev_id, NULL); + ret = nand_get_flash_type(mtd, chip, &nand_maf_id, &nand_dev_id, NULL); - if (IS_ERR(type)) { + if (ret) { chip->select_chip(mtd, -1); - return PTR_ERR(type); + return ret; } return 0; diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 9d8ccfda53..b4fa618dc4 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4276,9 +4276,8 @@ static const struct nand_manufacturer *nand_get_manufacturer_desc(u8 id) /* * Get the flash and manufacturer id and lookup if the type is supported. */ -struct nand_flash_dev *nand_get_flash_type(struct nand_chip *chip, int *maf_id, - int *dev_id, - struct nand_flash_dev *type) +int nand_get_flash_type(struct nand_chip *chip, int *maf_id, + int *dev_id, struct nand_flash_dev *type) { struct mtd_info *mtd = &chip->mtd; const struct nand_manufacturer *manufacturer_desc; @@ -4291,7 +4290,7 @@ struct nand_flash_dev *nand_get_flash_type(struct nand_chip *chip, int *maf_id, */ ret = nand_reset(chip, 0); if (ret) - return ERR_PTR(ret); + return ret; /* Select the device */ chip->select_chip(mtd, 0); @@ -4299,7 +4298,7 @@ struct nand_flash_dev *nand_get_flash_type(struct nand_chip *chip, int *maf_id, /* Send the command for reading device ID */ ret = nand_readid_op(chip, 0, id_data, 2); if (ret) - return ERR_PTR(ret); + return ret; /* Read manufacturer and device IDs */ *maf_id = id_data[0]; @@ -4315,12 +4314,12 @@ struct nand_flash_dev *nand_get_flash_type(struct nand_chip *chip, int *maf_id, /* Read entire ID string */ ret = nand_readid_op(chip, 0, id_data, 8); if (ret) - return ERR_PTR(ret); + return ret; if (id_data[0] != *maf_id || id_data[1] != *dev_id) { pr_info("second ID read did not match %02x,%02x against %02x,%02x\n", *maf_id, *dev_id, id_data[0], id_data[1]); - return ERR_PTR(-ENODEV); + return -ENODEV; } chip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data)); @@ -4368,7 +4367,7 @@ struct nand_flash_dev *nand_get_flash_type(struct nand_chip *chip, int *maf_id, } if (!type->name) - return ERR_PTR(-ENODEV); + return -ENODEV; if (!mtd->name) mtd->name = type->name; @@ -4401,7 +4400,7 @@ ident_done: pr_warn("bus width %d instead %d bit\n", (chip->options & NAND_BUSWIDTH_16) ? 16 : 8, busw ? 16 : 8); - return ERR_PTR(-EINVAL); + return -EINVAL; } nand_decode_bbm_options(mtd, chip); @@ -4432,7 +4431,7 @@ ident_done: ret = nand_manufacturer_init(chip); if (ret) - return ERR_PTR(ret); + return ret; pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", *maf_id, *dev_id); @@ -4460,7 +4459,7 @@ ident_done: pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n", (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC", mtd->erasesize >> 10, mtd->writesize, mtd->oobsize); - return type; + return 0; } EXPORT_SYMBOL(nand_get_flash_type); @@ -4547,7 +4546,6 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips, { int i, nand_maf_id, nand_dev_id; struct nand_chip *chip = mtd_to_nand(mtd); - struct nand_flash_dev *type; int ret; if (ofnode_valid(chip->flash_node)) { @@ -4560,14 +4558,14 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips, nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16); /* Read the flash type */ - type = nand_get_flash_type(chip, &nand_maf_id, + ret = nand_get_flash_type(chip, &nand_maf_id, &nand_dev_id, table); - if (IS_ERR(type)) { + if (ret) { if (!(chip->options & NAND_SCAN_SILENT_NODEV)) pr_warn("No NAND device found\n"); chip->select_chip(mtd, -1); - return PTR_ERR(type); + return ret; } /* Initialize the ->data_interface field. */ diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 8dc2d81dba..8178f36b49 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -29,9 +29,8 @@ struct nand_flash_dev; struct device_node; /* Get the flash and manufacturer id and lookup if the type is supported. */ -struct nand_flash_dev *nand_get_flash_type(struct nand_chip *chip, - int *maf_id, int *dev_id, - struct nand_flash_dev *type); +int nand_get_flash_type(struct nand_chip *chip, int *maf_id, int *dev_id, + struct nand_flash_dev *type); /* Scan and identify a NAND device */ int nand_scan(struct mtd_info *mtd, int max_chips); From patchwork Wed Jul 27 09:37:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Nazzareno Trimarchi X-Patchwork-Id: 2264 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f70.google.com (mail-ed1-f70.google.com [209.85.208.70]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 2FE1B3F1F7 for ; Wed, 27 Jul 2022 11:37:57 +0200 (CEST) Received: by mail-ed1-f70.google.com with SMTP id s17-20020a056402521100b0043ade613038sf10456206edd.17 for ; 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[37.181.33.55]) by smtp.gmail.com with ESMTPSA id q22-20020a17090676d600b006fece722508sm7317678ejn.135.2022.07.27.02.37.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Jul 2022 02:37:53 -0700 (PDT) From: Michael Trimarchi To: dario.binacchi@amarulasolutions.com, Tommaso Merciai , linux-amarula@amarulasolutions.com Subject: [PATCH 3/7] mtd: nand: Rename nand_get_flash_type() into nand_detect() Date: Wed, 27 Jul 2022 11:37:44 +0200 Message-Id: <20220727093748.1415135-4-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220727093748.1415135-1-michael@amarulasolutions.com> References: <20220727093748.1415135-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=HXxuLHfB; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Upstream linux commit 7bb427990ee364. Rename the function to match this new behavior. Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/mt7621_nand.c | 3 +-- drivers/mtd/nand/raw/mxs_nand_spl.c | 2 +- drivers/mtd/nand/raw/nand_base.c | 11 +++++------ include/linux/mtd/rawnand.h | 4 ++-- 4 files changed, 9 insertions(+), 11 deletions(-) diff --git a/drivers/mtd/nand/raw/mt7621_nand.c b/drivers/mtd/nand/raw/mt7621_nand.c index a4a0bce35d..f6eddb84a9 100644 --- a/drivers/mtd/nand/raw/mt7621_nand.c +++ b/drivers/mtd/nand/raw/mt7621_nand.c @@ -1186,8 +1186,7 @@ int mt7621_nfc_spl_post_init(struct mt7621_nfc *nfc) int nand_maf_id, nand_dev_id; int ret; - ret = nand_get_flash_type(nand, &nand_maf_id, - &nand_dev_id, NULL); + ret = nand_detect(nand, &nand_maf_id, &nand_dev_id, NULL); if (ret) return ret; diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c b/drivers/mtd/nand/raw/mxs_nand_spl.c index 773d375fc2..4dffa76eaf 100644 --- a/drivers/mtd/nand/raw/mxs_nand_spl.c +++ b/drivers/mtd/nand/raw/mxs_nand_spl.c @@ -83,7 +83,7 @@ static int mxs_flash_full_ident(struct mtd_info *mtd) struct nand_chip *chip = mtd_to_nand(mtd); int ret; - ret = nand_get_flash_type(mtd, chip, &nand_maf_id, &nand_dev_id, NULL); + ret = nand_detect(mtd, chip, &nand_maf_id, &nand_dev_id, NULL); if (ret) { chip->select_chip(mtd, -1); diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index b4fa618dc4..1a1a757932 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4276,8 +4276,8 @@ static const struct nand_manufacturer *nand_get_manufacturer_desc(u8 id) /* * Get the flash and manufacturer id and lookup if the type is supported. */ -int nand_get_flash_type(struct nand_chip *chip, int *maf_id, - int *dev_id, struct nand_flash_dev *type) +int nand_detect(struct nand_chip *chip, int *maf_id, + int *dev_id, struct nand_flash_dev *type) { struct mtd_info *mtd = &chip->mtd; const struct nand_manufacturer *manufacturer_desc; @@ -4461,7 +4461,7 @@ ident_done: mtd->erasesize >> 10, mtd->writesize, mtd->oobsize); return 0; } -EXPORT_SYMBOL(nand_get_flash_type); +EXPORT_SYMBOL(nand_detect); #if CONFIG_IS_ENABLED(OF_CONTROL) @@ -4558,8 +4558,7 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips, nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16); /* Read the flash type */ - ret = nand_get_flash_type(chip, &nand_maf_id, - &nand_dev_id, table); + ret = nand_detect(chip, &nand_maf_id, &nand_dev_id, table); if (ret) { if (!(chip->options & NAND_SCAN_SILENT_NODEV)) @@ -4591,7 +4590,7 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips, for (i = 1; i < maxchips; i++) { u8 id[2]; - /* See comment in nand_get_flash_type for reset */ + /* See comment in nand_detect for reset */ nand_reset(chip, i); chip->select_chip(mtd, i); diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 8178f36b49..fb002ae641 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -29,8 +29,8 @@ struct nand_flash_dev; struct device_node; /* Get the flash and manufacturer id and lookup if the type is supported. */ -int nand_get_flash_type(struct nand_chip *chip, int *maf_id, int *dev_id, - struct nand_flash_dev *type); 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[37.181.33.55]) by smtp.gmail.com with ESMTPSA id q22-20020a17090676d600b006fece722508sm7317678ejn.135.2022.07.27.02.37.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Jul 2022 02:37:57 -0700 (PDT) From: Michael Trimarchi To: dario.binacchi@amarulasolutions.com, Tommaso Merciai , linux-amarula@amarulasolutions.com Subject: [PATCH 4/7] mtd: nand: samsung: Retrieve ECC requirements from extended Date: Wed, 27 Jul 2022 11:37:45 +0200 Message-Id: <20220727093748.1415135-5-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220727093748.1415135-1-michael@amarulasolutions.com> References: <20220727093748.1415135-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=nMrQ2n5R; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Upstream linux commit 8fc82d456e40a0. On some nand controllers with hw-ecc the controller code wants to know the ecc strength and size and having these as 0, 0 is not accepted. Specifying these in devicetree is possible but undesirable as the nand may be different in different production runs of the same board, so it is better to get this info from the nand id where possible. This commit adds code to read the ecc strength and size from the nand for Samsung extended-id nands. This code is based on the info for the 5th id byte in the datasheets for the following Samsung nands: K9GAG08U0E, K9GAG08U0F, K9GAG08X0D, K9GBG08U0A, K9GBG08U0B. These all use these bits in the exact same way. Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/nand_samsung.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/mtd/nand/raw/nand_samsung.c b/drivers/mtd/nand/raw/nand_samsung.c index 0ab8062193..36ef48e5ec 100644 --- a/drivers/mtd/nand/raw/nand_samsung.c +++ b/drivers/mtd/nand/raw/nand_samsung.c @@ -64,6 +64,26 @@ static void samsung_nand_decode_id(struct nand_chip *chip) extid >>= 2; mtd->erasesize = (128 * 1024) << (((extid >> 1) & 0x04) | (extid & 0x03)); + + /* Extract ECC requirements from 5th id byte*/ + extid = (chip->id.data[4] >> 4) & 0x07; + if (extid < 5) { + chip->ecc_step_ds = 512; + chip->ecc_strength_ds = 1 << extid; + } else { + chip->ecc_step_ds = 1024; + switch (extid) { + case 5: + chip->ecc_strength_ds = 24; + break; + case 6: + chip->ecc_strength_ds = 40; + break; + case 7: + chip->ecc_strength_ds = 60; + break; + } + } } else { nand_decode_ext_id(chip); } From patchwork Wed Jul 27 09:37:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Nazzareno Trimarchi X-Patchwork-Id: 2267 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f72.google.com (mail-ed1-f72.google.com [209.85.208.72]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 4E69F3F1F7 for ; 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[37.181.33.55]) by smtp.gmail.com with ESMTPSA id q22-20020a17090676d600b006fece722508sm7317678ejn.135.2022.07.27.02.37.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Jul 2022 02:37:58 -0700 (PDT) From: Michael Trimarchi To: dario.binacchi@amarulasolutions.com, Tommaso Merciai , linux-amarula@amarulasolutions.com Subject: [PATCH 5/7] mtd: nand: Fix ecc in mxs_nand_spl onfi mode Date: Wed, 27 Jul 2022 11:37:46 +0200 Message-Id: <20220727093748.1415135-6-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220727093748.1415135-1-michael@amarulasolutions.com> References: <20220727093748.1415135-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=gHcl8wBk; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , We need to calculate the ecc parameters in a way that are the same in uboot and spl. The parameters are connected to the onfi computation. We need to assign all the value of chip in order to have same ecc strength parameters before calling mxs_nand_set_geometry that calculate the ecc layout /* use the legacy bch setting by default */ if ((!nand_info->use_minimum_ecc && mtd->oobsize < 1024) || !(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0)) { dev_dbg(mtd->dev, "use legacy bch geometry\n"); err = mxs_nand_legacy_calc_ecc_layout(geo, mtd); if (!err) return 0; } Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/mxs_nand_spl.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c b/drivers/mtd/nand/raw/mxs_nand_spl.c index 4dffa76eaf..6d8ec5b3cb 100644 --- a/drivers/mtd/nand/raw/mxs_nand_spl.c +++ b/drivers/mtd/nand/raw/mxs_nand_spl.c @@ -139,6 +139,10 @@ static int mxs_flash_onfi_ident(struct mtd_info *mtd) mtd->writesize = le32_to_cpu(p->byte_per_page); mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize; mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); + if (p->ecc_bits != 0xff) { + chip->ecc_strength_ds = p->ecc_bits; + chip->ecc_step_ds = 512; + } chip->chipsize = le32_to_cpu(p->blocks_per_lun); chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; /* Calculate the address shift from the page size */ @@ -152,6 +156,8 @@ static int mxs_flash_onfi_ident(struct mtd_info *mtd) debug("writesize=%d (>>%d)\n", mtd->writesize, chip->page_shift); debug("oobsize=%d\n", mtd->oobsize); debug("chipsize=%lld\n", chip->chipsize); + debug("ecc_strength_ds=%d\n", chip->ecc_strength_ds); + debug("ecc_step_ds = %d\n", chip->ecc_step_ds); return 0; } From patchwork Wed Jul 27 09:37:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Nazzareno Trimarchi X-Patchwork-Id: 2266 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ej1-f71.google.com (mail-ej1-f71.google.com [209.85.218.71]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 2CB573F1F7 for ; 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dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , When size is 0 we need to stop the inner loop or we just waste time to load all the block of the eraseblock Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/mxs_nand_spl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c b/drivers/mtd/nand/raw/mxs_nand_spl.c index 6d8ec5b3cb..c7ea09e2f9 100644 --- a/drivers/mtd/nand/raw/mxs_nand_spl.c +++ b/drivers/mtd/nand/raw/mxs_nand_spl.c @@ -260,10 +260,10 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) page_offset = offs % mtd->writesize; nand_page_per_block = mtd->erasesize / mtd->writesize; - while (block <= lastblock && size > 0) { + while (block <= lastblock) { if (!is_badblock(mtd, mtd->erasesize * block, 1)) { /* Skip bad blocks */ - while (page < nand_page_per_block) { + while (page < nand_page_per_block && size > 0) { int curr_page = nand_page_per_block * block + page; if (mxs_read_page_ecc(mtd, page_buf, curr_page) < 0) { From patchwork Wed Jul 27 09:37:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Nazzareno Trimarchi X-Patchwork-Id: 2268 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f71.google.com (mail-ed1-f71.google.com [209.85.208.71]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id A38893F330 for ; Wed, 27 Jul 2022 11:38:03 +0200 (CEST) Received: by mail-ed1-f71.google.com with SMTP id b15-20020a056402278f00b0043acaf76f8dsf10523854ede.21 for ; Wed, 27 Jul 2022 02:38:03 -0700 (PDT) ARC-Seal: i=2; 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[37.181.33.55]) by smtp.gmail.com with ESMTPSA id q22-20020a17090676d600b006fece722508sm7317678ejn.135.2022.07.27.02.38.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Jul 2022 02:38:01 -0700 (PDT) From: Michael Trimarchi To: dario.binacchi@amarulasolutions.com, Tommaso Merciai , linux-amarula@amarulasolutions.com Subject: [PATCH 7/7] mtd: nand: Add a common spl layer for nand subsystem Date: Wed, 27 Jul 2022 11:37:48 +0200 Message-Id: <20220727093748.1415135-8-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220727093748.1415135-1-michael@amarulasolutions.com> References: <20220727093748.1415135-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=KZ8hSNfI; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Avoid code duplication accross drivers but make them use the same implementation. Create nand_common_spl to implement the part that does not depend on nand chipset. Apply to - mxs nand spl driver - mt7621 spl driver The mt7621 now as side effect implement nand_spl_adjust_offset, that implements bad block handle for complex image like fitImage Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/Makefile | 4 +- drivers/mtd/nand/raw/mt7621_nand_spl.c | 188 +------------------ drivers/mtd/nand/raw/mxs_nand_spl.c | 176 +----------------- drivers/mtd/nand/raw/nand_common_spl.c | 245 +++++++++++++++++++++++++ drivers/mtd/nand/raw/nand_common_spl.h | 15 ++ 5 files changed, 269 insertions(+), 359 deletions(-) create mode 100644 drivers/mtd/nand/raw/nand_common_spl.c create mode 100644 drivers/mtd/nand/raw/nand_common_spl.h diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index a398aa9d88..82ddb2b5d8 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -87,8 +87,8 @@ else # minimal SPL drivers obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_spl.o obj-$(CONFIG_NAND_MXC) += mxc_nand_spl.o -obj-$(CONFIG_NAND_MXS) += mxs_nand_spl.o mxs_nand.o +obj-$(CONFIG_NAND_MXS) += mxs_nand_spl.o mxs_nand.o nand_common_spl.o obj-$(CONFIG_NAND_SUNXI) += sunxi_nand_spl.o -obj-$(CONFIG_NAND_MT7621) += mt7621_nand_spl.o mt7621_nand.o +obj-$(CONFIG_NAND_MT7621) += mt7621_nand_spl.o mt7621_nand.o nand_common_spl.o endif # drivers diff --git a/drivers/mtd/nand/raw/mt7621_nand_spl.c b/drivers/mtd/nand/raw/mt7621_nand_spl.c index 114fc8b7ce..254e14a553 100644 --- a/drivers/mtd/nand/raw/mt7621_nand_spl.c +++ b/drivers/mtd/nand/raw/mt7621_nand_spl.c @@ -10,187 +10,13 @@ #include #include #include +#include "nand_common_spl.h" #include "mt7621_nand.h" +#include "nand_common_spl.h" static struct mt7621_nfc nfc_dev; -static u8 *buffer; static int nand_valid; -static void nand_command_lp(struct mtd_info *mtd, unsigned int command, - int column, int page_addr) -{ - register struct nand_chip *chip = mtd_to_nand(mtd); - - /* Command latch cycle */ - chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); - - if (column != -1 || page_addr != -1) { - int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; - - /* Serially input address */ - if (column != -1) { - chip->cmd_ctrl(mtd, column, ctrl); - ctrl &= ~NAND_CTRL_CHANGE; - if (command != NAND_CMD_READID) - chip->cmd_ctrl(mtd, column >> 8, ctrl); - } - if (page_addr != -1) { - chip->cmd_ctrl(mtd, page_addr, ctrl); - chip->cmd_ctrl(mtd, page_addr >> 8, - NAND_NCE | NAND_ALE); - if (chip->options & NAND_ROW_ADDR_3) - chip->cmd_ctrl(mtd, page_addr >> 16, - NAND_NCE | NAND_ALE); - } - } - chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); - - /* - * Program and erase have their own busy handlers status, sequential - * in and status need no delay. - */ - switch (command) { - case NAND_CMD_STATUS: - case NAND_CMD_READID: - case NAND_CMD_SET_FEATURES: - return; - - case NAND_CMD_READ0: - chip->cmd_ctrl(mtd, NAND_CMD_READSTART, - NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); - chip->cmd_ctrl(mtd, NAND_CMD_NONE, - NAND_NCE | NAND_CTRL_CHANGE); - } - - /* - * Apply this short delay always to ensure that we do wait tWB in - * any case on any machine. - */ - ndelay(100); - - nand_wait_ready(mtd); -} - -static int nfc_read_page_hwecc(struct mtd_info *mtd, void *buf, - unsigned int page) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - int ret; - - chip->cmdfunc(mtd, NAND_CMD_READ0, 0x0, page); - - ret = chip->ecc.read_page(mtd, chip, buf, 1, page); - if (ret < 0 || ret > chip->ecc.strength) - return -1; - - return 0; -} - -static int nfc_read_oob_hwecc(struct mtd_info *mtd, void *buf, u32 len, - unsigned int page) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - int ret; - - chip->cmdfunc(mtd, NAND_CMD_READ0, 0x0, page); - - ret = chip->ecc.read_page(mtd, chip, NULL, 1, page); - if (ret < 0) - return -1; - - if (len > mtd->oobsize) - len = mtd->oobsize; - - memcpy(buf, chip->oob_poi, len); - - return 0; -} - -static int nfc_check_bad_block(struct mtd_info *mtd, unsigned int page) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - u32 pages_per_block, i = 0; - int ret; - u8 bad; - - pages_per_block = 1 << (mtd->erasesize_shift - mtd->writesize_shift); - - /* Read from first/last page(s) if necessary */ - if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) { - page += pages_per_block - 1; - if (chip->bbt_options & NAND_BBT_SCAN2NDPAGE) - page--; - } - - do { - ret = nfc_read_oob_hwecc(mtd, &bad, 1, page); - if (ret) - return ret; - - ret = bad != 0xFF; - - i++; - page++; - } while (!ret && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2); - - return ret; -} - -int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest) -{ - struct mt7621_nfc *nfc = &nfc_dev; - struct nand_chip *chip = &nfc->nand; - struct mtd_info *mtd = &chip->mtd; - u32 addr, col, page, chksz; - bool check_bad = true; - - if (!nand_valid) - return -ENODEV; - - while (size) { - if (check_bad || !(offs & mtd->erasesize_mask)) { - addr = offs & (~mtd->erasesize_mask); - page = addr >> mtd->writesize_shift; - if (nfc_check_bad_block(mtd, page)) { - /* Skip bad block */ - if (addr >= mtd->size - mtd->erasesize) - return -1; - - offs += mtd->erasesize; - continue; - } - - check_bad = false; - } - - col = offs & mtd->writesize_mask; - page = offs >> mtd->writesize_shift; - chksz = min(mtd->writesize - col, (uint32_t)size); - - if (unlikely(chksz < mtd->writesize)) { - /* Not reading a full page */ - if (nfc_read_page_hwecc(mtd, buffer, page)) - return -1; - - memcpy(dest, buffer + col, chksz); - } else { - if (nfc_read_page_hwecc(mtd, dest, page)) - return -1; - } - - dest += chksz; - offs += chksz; - size -= chksz; - } - - return 0; -} - -int nand_default_bbt(struct mtd_info *mtd) -{ - return 0; -} - unsigned long nand_size(void) { if (!nand_valid) @@ -203,10 +29,6 @@ unsigned long nand_size(void) return SZ_2G; } -void nand_deselect(void) -{ -} - void nand_init(void) { struct mtd_info *mtd; @@ -219,7 +41,7 @@ void nand_init(void) chip = &nfc_dev.nand; mtd = &chip->mtd; - chip->cmdfunc = nand_command_lp; + chip->cmdfunc = nand_spl_command_lp; if (mt7621_nfc_spl_post_init(&nfc_dev)) return; @@ -229,9 +51,7 @@ void nand_init(void) mtd->erasesize_mask = (1 << mtd->erasesize_shift) - 1; mtd->writesize_mask = (1 << mtd->writesize_shift) - 1; - buffer = malloc(mtd->writesize); - if (!buffer) - return; + nand_spl_init(chip); nand_valid = 1; } diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c b/drivers/mtd/nand/raw/mxs_nand_spl.c index c7ea09e2f9..5cff6020c4 100644 --- a/drivers/mtd/nand/raw/mxs_nand_spl.c +++ b/drivers/mtd/nand/raw/mxs_nand_spl.c @@ -14,66 +14,11 @@ #include #include #include +#include "nand_common_spl.h" static struct mtd_info *mtd; static struct nand_chip nand_chip; -static void mxs_nand_command(struct mtd_info *mtd, unsigned int command, - int column, int page_addr) -{ - register struct nand_chip *chip = mtd_to_nand(mtd); - u32 timeo, time_start; - - /* write out the command to the device */ - chip->cmd_ctrl(mtd, command, NAND_CLE); - - /* Serially input address */ - if (column != -1) { - /* Adjust columns for 16 bit buswidth */ - if (chip->options & NAND_BUSWIDTH_16 && - !nand_opcode_8bits(command)) - column >>= 1; - chip->cmd_ctrl(mtd, column, NAND_ALE); - - /* - * Assume LP NAND here, so use two bytes column address - * but not for CMD_READID and CMD_PARAM, which require - * only one byte column address - */ - if (command != NAND_CMD_READID && - command != NAND_CMD_PARAM) - chip->cmd_ctrl(mtd, column >> 8, NAND_ALE); - } - if (page_addr != -1) { - chip->cmd_ctrl(mtd, page_addr, NAND_ALE); - chip->cmd_ctrl(mtd, page_addr >> 8, NAND_ALE); - /* One more address cycle for devices > 128MiB */ - if (chip->chipsize > (128 << 20)) - chip->cmd_ctrl(mtd, page_addr >> 16, NAND_ALE); - } - chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0); - - if (command == NAND_CMD_READ0) { - chip->cmd_ctrl(mtd, NAND_CMD_READSTART, NAND_CLE); - chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0); - } else if (command == NAND_CMD_RNDOUT) { - /* No ready / busy check necessary */ - chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, - NAND_NCE | NAND_CLE); - chip->cmd_ctrl(mtd, NAND_CMD_NONE, - NAND_NCE); - } - - /* wait for nand ready */ - ndelay(100); - timeo = (CONFIG_SYS_HZ * 20) / 1000; - time_start = get_timer(0); - while (get_timer(time_start) < timeo) { - if (chip->dev_ready(mtd)) - break; - } -} - #if defined (CONFIG_SPL_NAND_IDENT) /* Trying to detect the NAND flash using ONFi, JEDEC, and (extended) IDs */ @@ -175,35 +120,6 @@ static int mxs_flash_ident(struct mtd_info *mtd) return ret; } -static int mxs_read_page_ecc(struct mtd_info *mtd, void *buf, unsigned int page) -{ - register struct nand_chip *chip = mtd_to_nand(mtd); - int ret; - - chip->cmdfunc(mtd, NAND_CMD_READ0, 0x0, page); - ret = nand_chip.ecc.read_page(mtd, chip, buf, 1, page); - if (ret < 0) { - printf("read_page failed %d\n", ret); - return -1; - } - return 0; -} - -static int is_badblock(struct mtd_info *mtd, loff_t offs, int allowbbt) -{ - register struct nand_chip *chip = mtd_to_nand(mtd); - unsigned int block = offs >> chip->phys_erase_shift; - unsigned int page = offs >> chip->page_shift; - - debug("%s offs=0x%08x block:%d page:%d\n", __func__, (int)offs, block, - page); - chip->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page); - memset(chip->oob_poi, 0, mtd->oobsize); - chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); - - return chip->oob_poi[0] != 0xff; -} - /* setup mtd and nand structs and init mxs_nand driver */ void nand_init(void) { @@ -215,7 +131,7 @@ void nand_init(void) mxs_nand_init_spl(&nand_chip); mtd = nand_to_mtd(&nand_chip); /* set mtd functions */ - nand_chip.cmdfunc = mxs_nand_command; + nand_chip.cmdfunc = nand_spl_command_lp; nand_chip.scan_bbt = nand_default_bbt; nand_chip.numchips = 1; @@ -234,92 +150,6 @@ void nand_init(void) mtd->size = nand_chip.chipsize; nand_chip.scan_bbt(mtd); mxs_nand_setup_ecc(mtd); -} - -int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) -{ - unsigned int sz; - unsigned int block, lastblock; - unsigned int page, page_offset; - unsigned int nand_page_per_block; - struct nand_chip *chip; - u8 *page_buf = NULL; - - chip = mtd_to_nand(mtd); - if (!chip->numchips) - return -ENODEV; - - page_buf = malloc(mtd->writesize); - if (!page_buf) - return -ENOMEM; - - /* offs has to be aligned to a page address! */ - block = offs / mtd->erasesize; - lastblock = (offs + size - 1) / mtd->erasesize; - page = (offs % mtd->erasesize) / mtd->writesize; - page_offset = offs % mtd->writesize; - nand_page_per_block = mtd->erasesize / mtd->writesize; - - while (block <= lastblock) { - if (!is_badblock(mtd, mtd->erasesize * block, 1)) { - /* Skip bad blocks */ - while (page < nand_page_per_block && size > 0) { - int curr_page = nand_page_per_block * block + page; - - if (mxs_read_page_ecc(mtd, page_buf, curr_page) < 0) { - free(page_buf); - return -EIO; - } - - if (size > (mtd->writesize - page_offset)) - sz = (mtd->writesize - page_offset); - else - sz = size; - - memcpy(dst, page_buf + page_offset, sz); - dst += sz; - size -= sz; - page_offset = 0; - page++; - } - - page = 0; - } else { - lastblock++; - } - - block++; - } - - free(page_buf); - - return 0; -} - -int nand_default_bbt(struct mtd_info *mtd) -{ - return 0; -} - -void nand_deselect(void) -{ -} - -u32 nand_spl_adjust_offset(u32 sector, u32 offs) -{ - unsigned int block, lastblock; - - block = sector / mtd->erasesize; - lastblock = (sector + offs) / mtd->erasesize; - - while (block <= lastblock) { - if (is_badblock(mtd, block * mtd->erasesize, 1)) { - offs += mtd->erasesize; - lastblock++; - } - - block++; - } - return offs; + nand_spl_init(&nand_chip); } diff --git a/drivers/mtd/nand/raw/nand_common_spl.c b/drivers/mtd/nand/raw/nand_common_spl.c new file mode 100644 index 0000000000..0595fcbc26 --- /dev/null +++ b/drivers/mtd/nand/raw/nand_common_spl.c @@ -0,0 +1,245 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Amarula Solutions B.V. All rights reserved. + * + * Author: Michael Trimarchi + * Author: Weijie Gao + */ + +#include +#include +#include +#include +#include +#include + +static struct nand_chip *nand; +static u8 *buffer; +static int nand_valid; + +int nand_spl_init(struct nand_chip *chip) +{ + struct mtd_info *mtd = nand_to_mtd(chip); + + if (!mtd) + return -EINVAL; + + buffer = malloc(mtd->writesize); + if (!buffer) + return -ENOMEM; + + nand = chip; + nand_valid = 1; + + return 0; +} + +static struct nand_chip *nand_spl_get_chip(void) +{ + return nand; +} + +void nand_spl_command_lp(struct mtd_info *mtd, unsigned int command, + int column, int page_addr) +{ + register struct nand_chip *chip = mtd_to_nand(mtd); + u32 timeo, time_start; + + /* Command latch cycle */ + chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); + + if (column != -1 || page_addr != -1) { + int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; + + /* Serially input address */ + if (column != -1) { + chip->cmd_ctrl(mtd, column, ctrl); + ctrl &= ~NAND_CTRL_CHANGE; + if (command != NAND_CMD_READID) + chip->cmd_ctrl(mtd, column >> 8, ctrl); + } + if (page_addr != -1) { + chip->cmd_ctrl(mtd, page_addr, ctrl); + chip->cmd_ctrl(mtd, page_addr >> 8, + NAND_NCE | NAND_ALE); + if (chip->options & NAND_ROW_ADDR_3) + chip->cmd_ctrl(mtd, page_addr >> 16, + NAND_NCE | NAND_ALE); + } + } + chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + + /* + * Program and erase have their own busy handlers status, sequential + * in and status need no delay. + */ + switch (command) { + case NAND_CMD_STATUS: + case NAND_CMD_READID: + case NAND_CMD_SET_FEATURES: + return; + + case NAND_CMD_READ0: + chip->cmd_ctrl(mtd, NAND_CMD_READSTART, + NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); + chip->cmd_ctrl(mtd, NAND_CMD_NONE, + NAND_NCE | NAND_CTRL_CHANGE); + } + + /* + * Apply this short delay always to ensure that we do wait tWB in + * any case on any machine. + */ + ndelay(100); + + timeo = (CONFIG_SYS_HZ * 20) / 1000; + time_start = get_timer(0); + while (get_timer(time_start) < timeo) { + if (chip->dev_ready(mtd)) + break; + } +} + +static int nand_spl_read_page_hwecc(struct mtd_info *mtd, void *buf, + unsigned int page) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + int ret; + + chip->cmdfunc(mtd, NAND_CMD_READ0, 0x0, page); + + ret = chip->ecc.read_page(mtd, chip, buf, 1, page); + if (ret < 0 || ret > chip->ecc.strength) + return -1; + + return 0; +} + +static int nand_spl_read_oob_hwecc(struct mtd_info *mtd, void *buf, u32 len, + unsigned int page) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + int ret; + + chip->cmdfunc(mtd, NAND_CMD_READ0, 0x0, page); + + ret = chip->ecc.read_page(mtd, chip, NULL, 1, page); + if (ret < 0) + return -1; + + if (len > mtd->oobsize) + len = mtd->oobsize; + + memcpy(buf, chip->oob_poi, len); + + return 0; +} + +static int nand_spl_check_bad_block(struct mtd_info *mtd, unsigned int page) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + u32 pages_per_block, i = 0; + int ret; + u8 bad; + + pages_per_block = 1 << (mtd->erasesize_shift - mtd->writesize_shift); + + /* Read from first/last page(s) if necessary */ + if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) { + page += pages_per_block - 1; + if (chip->bbt_options & NAND_BBT_SCAN2NDPAGE) + page--; + } + + do { + ret = nand_spl_read_oob_hwecc(mtd, &bad, 1, page); + if (ret) + return ret; + + ret = bad != 0xFF; + + i++; + page++; + } while (!ret && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2); + + return ret; +} + +int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest) +{ + struct nand_chip *chip = nand_spl_get_chip(); + struct mtd_info *mtd = &chip->mtd; + u32 addr, col, page, chksz; + bool check_bad = true; + + if (!nand_valid) + return -ENODEV; + + while (size) { + if (check_bad || !(offs & mtd->erasesize_mask)) { + addr = offs & (~mtd->erasesize_mask); + page = addr >> mtd->writesize_shift; + if (nand_spl_check_bad_block(mtd, page)) { + /* Skip bad block */ + if (addr >= mtd->size - mtd->erasesize) + return -ENXIO; + + offs += mtd->erasesize; + continue; + } + + check_bad = false; + } + + col = offs & mtd->writesize_mask; + page = offs >> mtd->writesize_shift; + chksz = min(mtd->writesize - col, (uint32_t)size); + + if (unlikely(chksz < mtd->writesize)) { + /* Not reading a full page */ + if (nand_spl_read_page_hwecc(mtd, buffer, page)) + return -EIO; + + memcpy(dest, buffer + col, chksz); + } else { + if (nand_spl_read_page_hwecc(mtd, dest, page)) + return -EIO; + } + + dest += chksz; + offs += chksz; + size -= chksz; + } + + return 0; +} + +int nand_default_bbt(struct mtd_info *mtd) +{ + return 0; +} + +void nand_deselect(void) +{ +} + +u32 nand_spl_adjust_offset(u32 sector, u32 offs) +{ + struct nand_chip *chip = nand_spl_get_chip(); + struct mtd_info *mtd = nand_to_mtd(chip); + unsigned int block, lastblock; + + block = sector / mtd->erasesize; + lastblock = (sector + offs) / mtd->erasesize; + + while (block <= lastblock) { + if (nand_spl_check_bad_block(mtd, block * mtd->erasesize)) { + offs += mtd->erasesize; + lastblock++; + } + + block++; + } + + return offs; +} diff --git a/drivers/mtd/nand/raw/nand_common_spl.h b/drivers/mtd/nand/raw/nand_common_spl.h new file mode 100644 index 0000000000..36bf63b230 --- /dev/null +++ b/drivers/mtd/nand/raw/nand_common_spl.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022 Amarula Solution B.V. All rights reserved. + * + * Author: Michael Trimarchi + */ + +#ifndef _NAND_COMMON_SPL_H +#define _NAND_COMMON_SPL_H + +void nand_spl_command_lp(struct mtd_info *mtd, unsigned int command, + int column, int page_addr); +int nand_spl_init(struct nand_chip *chip); + +#endif /* _NAND_COMMON_SPL_H_ */