From patchwork Tue Sep 27 10:24:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2387 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-qt1-f199.google.com (mail-qt1-f199.google.com [209.85.160.199]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 9CED13F1C8 for ; Tue, 27 Sep 2022 12:25:11 +0200 (CEST) Received: by mail-qt1-f199.google.com with SMTP id w4-20020a05622a134400b0035cbc5ec9a2sf6513960qtk.14 for ; Tue, 27 Sep 2022 03:25:11 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1664274310; cv=pass; d=google.com; s=arc-20160816; b=m8PibDyNWtT1riKqgufra/vl8egXeoGJK6JrEQ4Dk3BIbUMBK6ycXsH6v4F8VEqJiW pfmYXV2owBKJ/bVtBLadDGFDkir9I96Q+XXODn9JDyyIkJ2j0Fi4ozqnmsCURPk/Rjfe nLJIz/mQ5FyGHrQDD8PTCdY9gtx4qxDl57XlaZTnr4g8v3Vz9Xaf4yuEnIowmBvkUoLe ILgGF4YSHYtUtiS4ul8qFjDP/fwdIAsJsViMYRNXH00yguA0ksV8X0XIeEw0Plk5ZlnM tYTp1dIcmB/CzfCgNkyi9C+vUpCd6qOoeGjlxvzsO5QwVf+jue5kW1LAcityWuA30iQX 4MsQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:message-id:date:subject:cc:to :from:dkim-signature; bh=13rWljxrdyk5fcwwJDX2Eb4XCCFzNx54+JBaiPKX5iQ=; b=VxQS7gyZdgriXZ5N6Rs4UoTpN4w3R1F5YN5IhOE3+lU5CZKvW/uWf6qeP2TTpY82Cz LdDGzR4riuXRppXT4Pu9Ibf5mvKAgMMPK5Ql89/ADMEB/SQrdYL/wAgY9mBhIgsRrtl1 q1ohVZL48FUasdHVx4QSah2NzMfuSWnH+I6GjenJXpD+9vSJQEXcgg0YT9Re78xdLt0V UP8XQxo9obyEeTT8IdSq2YW8JxekZ5Rb/uFbxPlKlnWSkFWXjyQzmi1UIjYFgg37TmvS JZ7A2XhDq5ktS/ABRA79qNjSze7Bos3a4qtYbBAjp+ZUOpfJgTPJgwDmvLsYd1/IQngR iT0Q== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=bBNuS2KD; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:message-id:date:subject:cc:to:from :from:to:cc:subject:date; bh=13rWljxrdyk5fcwwJDX2Eb4XCCFzNx54+JBaiPKX5iQ=; b=eVrAmrW6bgd57h/mke1V33fIL9aWot22KUTrEECyT4kIExqATkXBJ6V8b5X6Ywu7yG k+OInGQmELfkRT6+cE6TBhvJi574hAwb2eRvAU4/dHRrfl/DoX55BmAXUg+PR2yT4/L6 SjAEf6f51DKFzsncbudDweR28zqOXquhANpNg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=13rWljxrdyk5fcwwJDX2Eb4XCCFzNx54+JBaiPKX5iQ=; b=nhAoA7hw5/4rWjYx05l8I/TqIfCfSUxpz8G2mvYzlcJ/To5j9o0i/03GqZ8p8kvCbk b+KFZ5bJyAxjwe2OUPGA+19aGqPebTf6d2i+765NIhGDRjHyXRa8pVP9V2HEy52ItPJl NLqW9xP3ypZ+bI4gbQwk9hTIIBg6KluznyJBbnJj+46+MErh+sxExujGB+2SM4QoX4yZ KMPN6copMsW7Yc8F6+8uTE/jmjTp0SGDmMWpYTlXdD25lUeXYSNyZI60da92/mbuUnhR 9uFL3bnMeep3irLJZA529sMlzuFh9JmG2uMfiQAfYhs8OA6OlNvLEzjYv1PyMSAsaDbF C8Dw== X-Gm-Message-State: ACrzQf3CtZVgE+BwSiRQCDHyUzObSQZWmzTaLfUgMyF27O6y5iRHQ0FT Dx0pQ6x1ztrcvYd7s9zuMisd9Tgh X-Google-Smtp-Source: AMsMyM7iWRLcbiQNk3C1nZPpX7zqo5ISMAxQ6xQXkbi2nDBRsKOevKw193Qf8zzRSY5vbjThN0RiBg== X-Received: by 2002:a05:620a:1103:b0:6ce:a0f6:90da with SMTP id o3-20020a05620a110300b006cea0f690damr17569559qkk.101.1664274310585; Tue, 27 Sep 2022 03:25:10 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a05:620a:1482:b0:6cd:f04a:6014 with SMTP id w2-20020a05620a148200b006cdf04a6014ls1358443qkj.4.-pod-prod-gmail; Tue, 27 Sep 2022 03:25:10 -0700 (PDT) X-Received: by 2002:a05:620a:40c4:b0:6ce:9653:c09a with SMTP id g4-20020a05620a40c400b006ce9653c09amr16948709qko.219.1664274309972; Tue, 27 Sep 2022 03:25:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664274309; cv=none; d=google.com; s=arc-20160816; b=YS357O2oEneH4oSE1TWAGr293QkuyS4bsv6dfpYIfj9XmUQHdgPY+0eXDMojOA87h9 6KZKm2i7zkkjha4lXo8xgm3aSaBXKjCm8hdMSwf4rjeaC0PkV9frnjLcWoERrlV4qUWQ Bq2XLH+YMo/64wAa62/1BjPcxO3Mh/c++CoHqioZl42AS461i7ou3ymylXh6u8+i4Y35 chC7RWrHiDcDe5S4hI3DJWmZO6/HCogc+STJ7LAQRYY1gFV1pAu3/GMxfXNBA3lTEBdc Pow6CUZe92+u3ovSGrIZPfqBtpdaLp4kW6c6yJKh3R8DdLz1w69ATWbXrE/x4hl0DjoH mrcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:dkim-signature; bh=D5mrFg+SkQJ1Q/CNWlJLaGhlsan8B5d2K7mtLoAm4Rg=; b=eXnndILdwgn0MYhSF6STdqZfu6kTF1S7iHealyFRvyZzClYp85qG8lmcN4XtKUPBjp P2K5C1Q6Gn2MAKlik5S4co+GlMmA9vxcBmhFD6/EJtKFJwgbvxRsG6KMFhWImfQRP3Wh /zCw03ObaLAzy0AIELTm0Iz5LrU9dPV6Ntim6PgJJY946tpEbYHnVyYLGazD68ozjH2X zhHycccBzYSq5UbmXxXCY2nxz/K+qwbfAu09d97E+o0nmg2zSvVB6xRrNVqGahAWmzkY G1AkNyqBe5G8h04O3U1hwUx+6zVPKS4hy1+sfZOxFiLhGLljcIIjD9DDSO5Wg9/jBPZd K7QA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=bBNuS2KD; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id b10-20020a05620a0f8a00b006c097741d81sor280116qkn.39.2022.09.27.03.25.09 for (Google Transport Security); Tue, 27 Sep 2022 03:25:09 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a05:620a:2584:b0:6ca:bf8e:5e2a with SMTP id x4-20020a05620a258400b006cabf8e5e2amr17398697qko.390.1664274309415; Tue, 27 Sep 2022 03:25:09 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.pdxnet.pdxeng.ch (host-95-232-92-192.retail.telecomitalia.it. [95.232.92.192]) by smtp.gmail.com with ESMTPSA id d11-20020a05620a240b00b006be8713f742sm752220qkn.38.2022.09.27.03.25.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Sep 2022 03:25:09 -0700 (PDT) From: Dario Binacchi To: linux-amarula@amarulasolutions.com Cc: michael@amarulasolutions.com, Dario Binacchi Subject: [PATCH 1/6] clk: imx: gate2 support shared counter and relative clock functions Date: Tue, 27 Sep 2022 12:24:38 +0200 Message-Id: <20220927102443.1816168-1-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=bBNuS2KD; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Michael Trimarchi Add shared counter in order to avoid to swich off clock that are already used. Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi --- drivers/clk/imx/clk-gate2.c | 15 ++++++++++++++- drivers/clk/imx/clk.h | 24 ++++++++++++++++++++---- 2 files changed, 34 insertions(+), 5 deletions(-) diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c index 40b2d4caab49..da2723023778 100644 --- a/drivers/clk/imx/clk-gate2.c +++ b/drivers/clk/imx/clk-gate2.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include "clk.h" @@ -33,6 +34,7 @@ struct clk_gate2 { u8 bit_idx; u8 cgr_val; u8 flags; + unsigned int *share_count; }; #define to_clk_gate2(_clk) container_of(_clk, struct clk_gate2, clk) @@ -42,6 +44,9 @@ static int clk_gate2_enable(struct clk *clk) struct clk_gate2 *gate = to_clk_gate2(clk); u32 reg; + if (gate->share_count && (*gate->share_count)++ > 0) + return 0; + reg = readl(gate->reg); reg &= ~(3 << gate->bit_idx); reg |= gate->cgr_val << gate->bit_idx; @@ -55,6 +60,13 @@ static int clk_gate2_disable(struct clk *clk) struct clk_gate2 *gate = to_clk_gate2(clk); u32 reg; + if (gate->share_count) { + if (WARN_ON(*gate->share_count == 0)) + return 0; + else if (--(*gate->share_count) > 0) + return 0; + } + reg = readl(gate->reg); reg &= ~(3 << gate->bit_idx); writel(reg, gate->reg); @@ -82,7 +94,7 @@ static const struct clk_ops clk_gate2_ops = { struct clk *clk_register_gate2(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 cgr_val, - u8 clk_gate2_flags) + u8 clk_gate2_flags, unsigned int *share_count) { struct clk_gate2 *gate; struct clk *clk; @@ -96,6 +108,7 @@ struct clk *clk_register_gate2(struct device *dev, const char *name, gate->bit_idx = bit_idx; gate->cgr_val = cgr_val; gate->flags = clk_gate2_flags; + gate->share_count = share_count; clk = &gate->clk; diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 0e1eaf03d419..b02075167f64 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -52,7 +52,7 @@ struct clk *imx_clk_pll14xx(const char *name, const char *parent_name, struct clk *clk_register_gate2(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 cgr_val, - u8 clk_gate_flags); + u8 clk_gate_flags, unsigned int *share_count); struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, const char *parent_name, void __iomem *base, @@ -62,7 +62,23 @@ static inline struct clk *imx_clk_gate2(const char *name, const char *parent, void __iomem *reg, u8 shift) { return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, - shift, 0x3, 0); + shift, 0x3, 0, NULL); +} + +static inline struct clk *imx_clk_gate2_shared(const char *name, + const char *parent, void __iomem *reg, u8 shift, + unsigned int *share_count) +{ + return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, + shift, 0x3, 0, share_count); +} + +static inline struct clk *imx_clk_gate2_shared2(const char *name, + const char *parent, void __iomem *reg, u8 shift, + unsigned int *share_count) +{ + return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT | + CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0, share_count); } static inline struct clk *imx_clk_gate4(const char *name, const char *parent, @@ -70,7 +86,7 @@ static inline struct clk *imx_clk_gate4(const char *name, const char *parent, { return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, - reg, shift, 0x3, 0); + reg, shift, 0x3, 0, NULL); } static inline struct clk *imx_clk_gate4_flags(const char *name, @@ -79,7 +95,7 @@ static inline struct clk *imx_clk_gate4_flags(const char *name, { return clk_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, - reg, shift, 0x3, 0); + reg, shift, 0x3, 0, NULL); } static inline struct clk *imx_clk_fixed_factor(const char *name, From patchwork Tue Sep 27 10:24:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2388 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-qk1-f199.google.com (mail-qk1-f199.google.com [209.85.222.199]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id B678D3F1C8 for ; Tue, 27 Sep 2022 12:25:34 +0200 (CEST) Received: by mail-qk1-f199.google.com with SMTP id w10-20020a05620a444a00b006ce9917ea1fsf6978242qkp.16 for ; Tue, 27 Sep 2022 03:25:34 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1664274333; cv=pass; d=google.com; s=arc-20160816; b=aEl5vYcj6kxzjQ9n78c2yexv+eC66numJy/PyWP4TjWwnli/S5kRe4BvhFibxQeEWv bcEYXLKopRIXoVtOkulQo+QAn5gTfCed/lgpswfO41gXYN3RiYuNhpyCNlcz3rLrhQiP zWFNOoHm/dN99C3icntzfHsstXqZCRU2VLz7aT9TtYiiH50K0dOYGuLPMQVIGdAzMfvO I1BNwCmZPGKl4QSv9eG4i/WlzZnZAHsXLqeuhriTtllOuxtKdvtubv35MdRtDVNMbq0B FE6K3svnO3o2lpnwQCxQCxpJpjYLMB9nUGPLgPZ1A5je7wKMgEtm30Q+3CPTGjL5j1t2 5Dhw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=TCNqw8nDFBZ+9RfaM6MHVaHe/s4S4aL2bMgmQ7kF7rg=; b=QrVtGtzMCHOsXRsCQEWjEnbAhPLcJxsI22b2mMISF5XxlpKLA8f92wu9IBrPVYhsMj cHUqcPNuz6W1aZWPz6DsNIua7sQPf0tLBINS6WAQBrCOP9oZUo3+Jjw3EHk+ChlWxG+W zr9rar8ghiFypmxLgffoRfQ/ickAQ1MdFRs1MC7LPNJGsaRSLCxrsp//fcWiWVczRqDo QAHx6TTULaRjAz5vRZYRs7GWz/Y9woBp5mBuU41ns9bSout0lHrKiZgzdhUF7PTZV+3U XSV69XSFoAQhVi6uAN0MKDq3PsAVzaGcf+ZPy+LYyq3Xckz0gUUsd4e7aHprwdjxtDk5 29TA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=OzZubobJ; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date; bh=TCNqw8nDFBZ+9RfaM6MHVaHe/s4S4aL2bMgmQ7kF7rg=; b=g0w9pw6hRltC5JYXSJkle5t0dCuOFcEJ+f8r6fGD9CQAyzG4uHKYmPgWYyhPVaK5SF vEyvffbHQCXJEKzFaZ9yHXSSZBNn/e2/klFX+1nzMxODj6IXF3V66chvp9FdVVqY/4Ut Mn0NVeUkeDlUzbq3tP6ACPrjq+6vSOAe5jtvs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date; bh=TCNqw8nDFBZ+9RfaM6MHVaHe/s4S4aL2bMgmQ7kF7rg=; b=dSoS2NRug7pq6xreDA+BFkH2ueCvObKlVl6mAbuqOmbRuBmS0ceT0SeO2IUNqC5Mfc luyKUgCT2ytHNvHRaDxzqUaTnGHZOpU6jNrw14uqXo2pYlRE7yl18kKpn3Rv8CUPZ73/ fKi2XIbe5rbgspLlTwxTCKstSqiWlIh7TBA9bL5Sczro+rrJggUzWsdrH1qnz33IoMDK sljWVaMZHkB3D/AspuZabuZds0bMoPtjL3dfMRHzKwQ1ZOpcgIxJJvDStpfaQDp/poJQ 8t0NSwA3mCLLWgj6a5OUS6RuNKIOJoAEptzY8NKHbStu2iUzXKzUBIMkKOT0DRUwux5B v4Lg== X-Gm-Message-State: ACrzQf2up1dXxzp6bNsyOX9yRGCD43IpjhHeO9QVH+AV2LXDxpTynedm XIJWKVG8iDPgo85/9Da+W+m7Qooc X-Google-Smtp-Source: AMsMyM7Ys+Lih0tERjryZj0/ccR/+bh963UvlYwaDo+VQAmZ/BU+dtuNkmEsuE69z/itpGmMs9VZEw== X-Received: by 2002:a05:620a:c55:b0:6a7:9f07:f41 with SMTP id u21-20020a05620a0c5500b006a79f070f41mr17445247qki.430.1664274333764; Tue, 27 Sep 2022 03:25:33 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a0c:a9ce:0:b0:4ad:3c6e:9c05 with SMTP id c14-20020a0ca9ce000000b004ad3c6e9c05ls1070753qvb.11.-pod-prod-gmail; Tue, 27 Sep 2022 03:25:33 -0700 (PDT) X-Received: by 2002:a05:6214:4101:b0:4af:8cdc:20c4 with SMTP id kc1-20020a056214410100b004af8cdc20c4mr1598763qvb.6.1664274333219; Tue, 27 Sep 2022 03:25:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664274333; cv=none; d=google.com; s=arc-20160816; b=Bwopk89cI824LK5sp0/DVj8WdLcp63tNO85IIx4ps8d7tMvuwfnM47I3AknELfDDn7 m1+Nr2KSmg/yMQ3+bw6JFW3fYEbRdxYYmwcrYPyNbSWmP1w7MUVgiQ3KbBvBz1Z5/JAG QOjfuZ9EJ2gzsZAJiNmMT6I1NAfDxUtTtx0ymSarxyti3rQcTHvV4FkDS9xIg6TZtTmI IJgtoQ1CMYM6dllOZrCnLGIL+iu3vQqRk3l/YuqvbvUvNjH2SKWFdWkkAAu3i3sylAsT ZYcSJD/4jvYCT9SOHMAkz8jOZTXDEOwemTVxBlqBm+TJoz8nyNoE4XX+RLWfRBNKlvDI UdkQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=pGDKq+xn18+m6jtoNNUu49y0z2SdD5p2VhRYi00YVHY=; b=RBlr4BvDwli+7V1IShr35JjxvZNzA+1cqip2bQDc61SlPlTUq6I1mKMcxlxkO0x6ag B3U2MrSpZunBormxd1Do8nY5GEgdu1XzXH4oMJc9i6rec2p9IYkqxFcIDHVB204pBV2B S3wywhSwxFtO8dIeQJrEhcQJJ/JVxcpYm436l/zSg8ewCMwkunCTMfJKfws6K7oikTgO Xw3/xnnaX7zJspquCeqkCG7SeG7AIbUl/hCxoMy/yALQd//sn+sA9nMoClmcXrwOic1W s1rgMJDLF2Y16xEbHlS0a/qMj0p+WZ1oV4+yfgA/pTXKjfZrOnCsEDvEEArGWv10FQ0d erIQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=OzZubobJ; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id iy13-20020a0562140f6d00b004a06adbd4c5sor814347qvb.10.2022.09.27.03.25.33 for (Google Transport Security); Tue, 27 Sep 2022 03:25:33 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a0c:dd94:0:b0:4ad:4f0e:d660 with SMTP id v20-20020a0cdd94000000b004ad4f0ed660mr20230334qvk.118.1664274332668; Tue, 27 Sep 2022 03:25:32 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.pdxnet.pdxeng.ch (host-95-232-92-192.retail.telecomitalia.it. [95.232.92.192]) by smtp.gmail.com with ESMTPSA id d11-20020a05620a240b00b006be8713f742sm752220qkn.38.2022.09.27.03.25.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Sep 2022 03:25:32 -0700 (PDT) From: Dario Binacchi To: linux-amarula@amarulasolutions.com Cc: michael@amarulasolutions.com, Dario Binacchi Subject: [PATCH 2/6] clk: imx: clk-imx8mn add gpmi nand clocks Date: Tue, 27 Sep 2022 12:24:39 +0200 Message-Id: <20220927102443.1816168-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220927102443.1816168-1-dario.binacchi@amarulasolutions.com> References: <20220927102443.1816168-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=OzZubobJ; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Michael Trimarchi Add gpmi nand clock. Those clock can be used in mxs nand driver to run nand to EDO mode 5, 4, ... Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi --- drivers/clk/imx/clk-imx8mn.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index 15d7599cfb7d..83e31e37fa49 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -15,6 +15,8 @@ #include "clk.h" +static u32 share_count_nand; + static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", }; static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", }; static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; @@ -90,6 +92,10 @@ static const char *imx8mn_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sy static const char *imx8mn_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", }; +static const char *imx8mn_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out", + "sys_pll1_400m", "audio_pll2_out", "sys_pll3_out", + "sys_pll2_250m", "video_pll1_out", }; + static const char * const imx8mn_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", }; @@ -268,6 +274,8 @@ static int imx8mn_clk_probe(struct udevice *dev) clk_dm(IMX8MN_CLK_USDHC3, imx8m_clk_composite("usdhc3", imx8mn_usdhc3_sels, base + 0xbc80)); + clk_dm(IMX8MN_CLK_NAND, + imx8m_clk_composite("nand", imx8mn_nand_sels, base + 0xab00)); clk_dm(IMX8MN_CLK_QSPI, imx8m_clk_composite("qspi", imx8mn_qspi_sels, base + 0xab80)); clk_dm(IMX8MN_CLK_USB_CORE_REF, @@ -299,6 +307,11 @@ static int imx8mn_clk_probe(struct udevice *dev) imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0)); clk_dm(IMX8MN_CLK_QSPI_ROOT, imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0)); + clk_dm(IMX8MN_CLK_NAND_ROOT, + imx_clk_gate2_shared2("nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand)); + clk_dm(IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK, + imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_bus", base + 0x4300, 0, + &share_count_nand)); clk_dm(IMX8MN_CLK_USB1_CTRL_ROOT, imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0)); From patchwork Tue Sep 27 10:24:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2389 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-qk1-f197.google.com (mail-qk1-f197.google.com [209.85.222.197]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id F2BF63F1C8 for ; Tue, 27 Sep 2022 12:25:40 +0200 (CEST) Received: by mail-qk1-f197.google.com with SMTP id v15-20020a05620a0f0f00b006ceab647023sf6994324qkl.13 for ; Tue, 27 Sep 2022 03:25:40 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1664274340; cv=pass; d=google.com; s=arc-20160816; b=GgOwOj37dV0UjGf9nXMm4KxTho+qdltdSD1ibhlFsmgmNWqsOnTU5/IGIRcwZeESA8 Mii0zec4+QzumnclLsHF1WqmPTf83jy4t2Oqjy6P3/kIimV0IJDFKw1gmo4WdNcGRW+F 1qMh7Ayw6PIi6DCeZgLIx5WDFpzj+4ma8kB+wktkpPbzkuKrdyT9hGOCCxlUlUzi0BYi HV2iPubYwHefIW2t4YK2j6kjADkiPc2HyCYXHyZBGZ3H99jl7DNt1mhFXKtqrJarAr6R n474LAekmgyS1MSVwuhchBPWxL8PQXbLhHx1B/+ETLrW3lxtDhMCvdBVDSf/CPhz6JgF b1lA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=iZTOivsluDXK94Zo1SozORrplAnhuC15m1uXOoghVYA=; b=1GEvVCe95AuhAh9V3ueSsIhXIV3nE5Qn49SfUSqDznmm+qtj3OSQudhbipBaInqJ7A zq6f/mV23VvYf79YwIobhM6D+KKk2nh9gHWNhedtQ+xD0XoeR06t1y++ZHS919oEh5hA 2+B3MnZ7mY+3UXRseVHzxRtgcQDIq8K1jvZVG1imEKdOVjwgtyBIAGN2VS2ieHd1ehoi a/iUUw3Hqib3Fx2YVL6QRRwCtLIbtDeghIsEWgl9r3tA/ubo88U3ir/wat7pXs10YLcK NJd/ygIh/+aydhHhEqzrU6/o/bVXZKJtqiEokR8Xrz/Cy0fqx4ObLvmC6T6XnASBuOJQ P/ag== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="TY+Vk/kl"; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date; bh=iZTOivsluDXK94Zo1SozORrplAnhuC15m1uXOoghVYA=; b=HocAqL85i0T+U5WJgokb0XTS96GtmWXZgUrHu9ViKr+1Hemd0eVcu8QnAGCK6qi80n 0RPi+p7/XJYj/4aMkFqeph+jwVU/M1yYBqUDH9NxVlo26/3/ACsQndZiZnH4+CJpXGi5 tpyS62WxvqoWyAGXEjo9MrjU9u7MhJ6guBSUM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date; bh=iZTOivsluDXK94Zo1SozORrplAnhuC15m1uXOoghVYA=; b=mMadI7Ab9h4k3UvS3iVbiqcslSlGoAdB4bAd3IU1QOecgMVxYuWz+YOFjjkpa/SNPT nyUTwrhseIjA5i4/0I+JeebpAwsXDBkM2j0Jx7TRnWH4AfejH+ZTim6MLj4YWK0aatSe oqpGytInizafHv3ERGGMrZgfzPsb3OBYRk51SxjO9KNIeH/sOGbNztJHzJaGG123Ecvp 81P7gW8mKNRGrglYwYOsg8VeWfuwKlrtIJlX2P1ASKtSoZK3/4nbjfajRSKrC1jPtxlO azlj88BxZespB6/oBk+rMI8qmgUqBO+JN/KTD2mTKhc7ASV5u/l8lcPIjn0MWpQmwC5F sPHg== X-Gm-Message-State: ACrzQf3pU36zMjokIHL1MEnz1VWN8eTPnouPGw+34mwh/sIyfgXwgda+ u/CQ3t7Uw3DeWpJIfSqXGAsXKg1B X-Google-Smtp-Source: AMsMyM5SVO0g/+d0qK+1jF7wTHp9JCPSNznBE/ZM5OwCb9JlsLMFtJ7MAsXSAGcGMrWXmbxNlfhHGg== X-Received: by 2002:a05:620a:2902:b0:6ce:7e0d:c233 with SMTP id m2-20020a05620a290200b006ce7e0dc233mr16811962qkp.205.1664274339998; Tue, 27 Sep 2022 03:25:39 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:ac8:4611:0:b0:342:f631:7f63 with SMTP id p17-20020ac84611000000b00342f6317f63ls1405523qtn.3.-pod-prod-gmail; Tue, 27 Sep 2022 03:25:39 -0700 (PDT) X-Received: by 2002:a05:622a:447:b0:35d:43ae:96a6 with SMTP id o7-20020a05622a044700b0035d43ae96a6mr5906445qtx.71.1664274339358; Tue, 27 Sep 2022 03:25:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664274339; cv=none; d=google.com; s=arc-20160816; b=P5m8FVfRqNHJ4H+GVboOEHzrtJGLIisxn6XSKalE8+awBY634LlLoyvD9naE56/tjm 1Rqqr7D/WxR/1ha+D5W32Ho1ln3mqLH+7Et/m9OhzT0yUNOSZIyCUUJAZJOloyHBjvPF XEJDWZWr0FzFWUUS7CqTffMxCTTkRCAK/V84wYK9kSvc+lwzxFqP7IWd0AJrXu7Xqu1m s0tTi0nmm7qma2wbxLZ3VjhA4oGXouuyqgnn6K4sw/tBxBzStj201EZrz0BzEsQ0Yges pW/9f1zco50bmFrsPFJsSXTVo1fjto/9aHfKwvizZzBvxy9U3Pm2K4I/hJqOxcq0poFl FiPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=/Jg5mwMtMPtJQ0kdBLOzsvaXMuaNDU222h/klHdkT1Q=; b=FMSEkyZG0RsJ0oCnvAqOQUP9BRasxBy+ZzIIBcGaWmXkhHPkHjcKWnS4aoYhdQ9I0T ztUaOiV0hnIs6/y0DZ1rgKCcUDXwIk49fCoyXTNgOXtD01nSmT0MXXDTePcq7UZgx2AA fYOhPBSOfSYFu3mvqWCCCvoMgKCHWOseFosbfFNgZ13rKdUoTwfmaA6xqOsGvaw42z8K Iki6JDeG/edcCuYGXih+27br7sz04ryjFWh97JkTMOTuTnKR9XXCqsMvXAN42SG+rgmm K4EiE/wJOuOl1ZYUJxRjqv4ShXjx/LfaZ+px557ZM5y3Eg8bzGtgoOaWoL6OoFcJwh1F Xqaw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="TY+Vk/kl"; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id br33-20020a05620a462100b006b995c43de8sor279991qkb.151.2022.09.27.03.25.39 for (Google Transport Security); Tue, 27 Sep 2022 03:25:39 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a05:620a:4008:b0:6ce:8725:cb7 with SMTP id h8-20020a05620a400800b006ce87250cb7mr17801330qko.480.1664274338874; Tue, 27 Sep 2022 03:25:38 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.pdxnet.pdxeng.ch (host-95-232-92-192.retail.telecomitalia.it. [95.232.92.192]) by smtp.gmail.com with ESMTPSA id d11-20020a05620a240b00b006be8713f742sm752220qkn.38.2022.09.27.03.25.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Sep 2022 03:25:38 -0700 (PDT) From: Dario Binacchi To: linux-amarula@amarulasolutions.com Cc: michael@amarulasolutions.com, Dario Binacchi Subject: [PATCH 3/6] imx: gpmi: Add register needed to control nand bus timing Date: Tue, 27 Sep 2022 12:24:40 +0200 Message-Id: <20220927102443.1816168-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220927102443.1816168-1-dario.binacchi@amarulasolutions.com> References: <20220927102443.1816168-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="TY+Vk/kl"; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Michael Trimarchi Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi --- arch/arm/include/asm/mach-imx/regs-gpmi.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/include/asm/mach-imx/regs-gpmi.h b/arch/arm/include/asm/mach-imx/regs-gpmi.h index 33daa53c45df..7a1577863195 100644 --- a/arch/arm/include/asm/mach-imx/regs-gpmi.h +++ b/arch/arm/include/asm/mach-imx/regs-gpmi.h @@ -93,6 +93,11 @@ struct mxs_gpmi_regs { #define GPMI_CTRL1_DECOUPLE_CS (1 << 24) #define GPMI_CTRL1_WRN_DLY_SEL_MASK (0x3 << 22) #define GPMI_CTRL1_WRN_DLY_SEL_OFFSET 22 +#define GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS 0x0 +#define GPMI_CTRL1_WRN_DLY_SEL_6_TO_10NS 0x1 +#define GPMI_CTRL1_WRN_DLY_SEL_7_TO_12NS 0x2 +#define GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY 0x3 + #define GPMI_CTRL1_TIMEOUT_IRQ_EN (1 << 20) #define GPMI_CTRL1_GANGED_RDYBUSY (1 << 19) #define GPMI_CTRL1_BCH_MODE (1 << 18) @@ -111,6 +116,10 @@ struct mxs_gpmi_regs { #define GPMI_CTRL1_ATA_IRQRDY_POLARITY (1 << 2) #define GPMI_CTRL1_CAMERA_MODE (1 << 1) #define GPMI_CTRL1_GPMI_MODE (1 << 0) +#define GPMI_CTRL1_CLEAR_MASK (GPMI_CTRL1_WRN_DLY_SEL_MASK | \ + GPMI_CTRL1_DLL_ENABLE | \ + GPMI_CTRL1_RDN_DELAY_MASK | \ + GPMI_CTRL1_HALF_PERIOD) #define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xff << 16) #define GPMI_TIMING0_ADDRESS_SETUP_OFFSET 16 From patchwork Tue Sep 27 10:24:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2390 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-qv1-f69.google.com (mail-qv1-f69.google.com [209.85.219.69]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id B99423F1C8 for ; Tue, 27 Sep 2022 12:25:46 +0200 (CEST) Received: by mail-qv1-f69.google.com with SMTP id mo5-20020a056214330500b004ad711537a6sf5537413qvb.10 for ; Tue, 27 Sep 2022 03:25:46 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1664274345; cv=pass; d=google.com; s=arc-20160816; b=wZhDZAPKFG9p4PPwUdwLTN95TkOqNWWhtw/NjketIB/r1ez78CEh/OveLqyzOS7Gfx EARI+y3YyWRkbeB+o+3HDPO2hQzrI+RBz9LE3+eAYjKrOHqJgfMHg2SIlvjZgJJPQCV2 /xrh6E1hhjNVn1cpts1+VojdsJ4EsufAt/C48wMFo0qqPHCB7ib/6NqahPRl3Mnx/EeK F96X4gI0L1/k24uhWXiGkmvR6+Ekmgqn0m608SYPpj9T/WWKFeXcgKcUiRX8NNMFiAY8 hD4Y3t5uhUVIH3bileKjRAnNb3jF2YGWpfbF3ydnw0au7e+U+Gprh2fNLBc3AKx/cU0I jCjw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=umJscMPrnAoEHbgWf8DzO1lPfLMgCFykwlOJjHCJcgo=; b=jpi0I5GwDNXzvQJJdJnSZXD7ZSRbO53LIxxaaUs2u8OLHZQxUD1MUirXhIUievg/V/ cCUsk6c+2KLh/r1jUDntw3GB0068SlhRNBhfy6qeZoETHwMM8A/Jp8Rbawm1mHExjo4E 0n+DMGV2i8msr0JwuFTEMiAEiCkd3ZC+F1oXykS2M5EPNJcA1AQiq3DqfTxh3iQhi0xL w7kk0xPFUXqsg7m2bFCEcbkDbl1pRoyOCgQedU6zbfVyZYYGuDIZqbDRw2yXEGwcK2Ij i0TwUWwF4OkZvaD7SSoRa3wVxGSDVq3DIu3U45IUdVHZiPx7uwg0OKRcxpEZFAe+5H/t eVUQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=hTnSUMuN; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date; bh=umJscMPrnAoEHbgWf8DzO1lPfLMgCFykwlOJjHCJcgo=; b=hr7TGAuI96Y6QkSeqZ/+lUNHzAPoZl0bn7n0NsayLqzp9h/sNaRsBrhR4yOYU/lzTf xNPtgejWxo3XV5dIAAUxnAFeVQhv22K6WlunOhEJQscCk5XsIg9o4SvpXFderc0Xlcp0 p8AwPgSlqSbDIJlRaUWUYNNV0oY/l4hDTJBjk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date; bh=umJscMPrnAoEHbgWf8DzO1lPfLMgCFykwlOJjHCJcgo=; b=SlpXFufYdk+0Ij476Eiq+UXY2NlzvrS6AiAR19PDPF+ywBkDt9C2BrJ2sKU+Iirtev /Bc3ePpUumDnGObzioB2Yu+nbRgxW4iC3aL51B0sUAxQYnYywDRB8MPgD7rv1uBG9fau BIuRmeFTT+sPoNogPoMEGiBECai3gxxjWejm5a+DEchys4ifXMusN0ZbLqfMLoxO11Hj 7WYUE1eTJm/LE0YofZ6b0EaMuQSR9XoM/Bfc6E+uuFKlZ8KvLenZkIC7Xx5mbHtn4ffu dyVLQURJ8uGIu4pHEXokmFUPQr8e9MvdBqR/A7cZAuf7Drr3KsgN1Nn3kh2iCVoLE89q ph/g== X-Gm-Message-State: ACrzQf3J+Wz5F0X5+0svhFPamvGW/77dviyxoLcZKPu3dSKux+OhFUZQ ZKmYUrSLgboxYkaAXXGdsPMWGGNN X-Google-Smtp-Source: AMsMyM4w6lEMo1tgK+NjSc/i7goKAKkRUFoSGS+jV2cz/kJhh+4xP2mYMvFUgCWtUDOejUr6744F3Q== X-Received: by 2002:a0c:9a0c:0:b0:497:2e1c:98a3 with SMTP id p12-20020a0c9a0c000000b004972e1c98a3mr20844686qvd.91.1664274345662; Tue, 27 Sep 2022 03:25:45 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a05:622a:386:b0:342:fcdc:2d4d with SMTP id j6-20020a05622a038600b00342fcdc2d4dls1366432qtx.10.-pod-prod-gmail; Tue, 27 Sep 2022 03:25:45 -0700 (PDT) X-Received: by 2002:a05:622a:107:b0:35d:4cfe:5b34 with SMTP id u7-20020a05622a010700b0035d4cfe5b34mr1247814qtw.388.1664274345104; Tue, 27 Sep 2022 03:25:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664274345; cv=none; d=google.com; s=arc-20160816; b=u+zne3N4oBy6+5KBgCiwPNQQFbAgBKsAG94s0sN8Fo3RzhHXVNNV8q1z9zoVblpvty Z7mughUWW0/TKEZdJE77ZI/n/BSyGlaH8YXQhj3OycmLxImveoxIHUAIUkAMyz6X28Y0 AP+kQh9PcCaKgUvPC3ZWhSKZ51CJxHZs6HJmnQoe01wPNl69aKlCGNyf8qvCDmA90rOh OufYKcMyE5GyEmATUdJAywMULJwXWTAISzYp9+MjxrRxOrcfqGWzbDIeGiKrNiQX5CBq sQy4eOU1PgYhoqCV49N8HjgWFOPvdGC4EmhGY73+NdeK1a2NyhZuczDlJGGzAQx1Kyqp +zxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=+YD7bF1kO6ZqRwpuHSR62S3PKJz8ye4UiphsI9lYWyY=; b=wPbLH94Zp9yeaC5YmNA7lGYm00jtqC+M/YY13eusRj51IcTjOpfBjnfhyHXdKaADYp M8mZop0LjnmACMZAfeuH8PniVdXvgGK0emOWyKquEvE1ywWQx3//Kf7vmPfeiPFg8Dai RbyufcaIuksGk9X3MM354LcP+pw06ywNkNw3U6vwm5qX6A1zrMNTKCreDQ/x6emxhAk8 aHdkvKxwJbThdl+d94XcbPsSK+M+18Zhq1xcUNp1I7I3f7EFeA00fn/ntl2k15+IxHV7 Vxttz6O4FOCKdexLxq9x4On10/annGX+g+Le6Mgn+UKyIjkR8dRyKpVk9IaK/MxXI6Hd HsvA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=hTnSUMuN; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id h5-20020a05620a400500b006bbcb84b046sor280796qko.189.2022.09.27.03.25.45 for (Google Transport Security); Tue, 27 Sep 2022 03:25:45 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a05:620a:2485:b0:6ce:d439:887 with SMTP id i5-20020a05620a248500b006ced4390887mr17045248qkn.458.1664274344331; Tue, 27 Sep 2022 03:25:44 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.pdxnet.pdxeng.ch (host-95-232-92-192.retail.telecomitalia.it. [95.232.92.192]) by smtp.gmail.com with ESMTPSA id d11-20020a05620a240b00b006be8713f742sm752220qkn.38.2022.09.27.03.25.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Sep 2022 03:25:43 -0700 (PDT) From: Dario Binacchi To: linux-amarula@amarulasolutions.com Cc: michael@amarulasolutions.com, Dario Binacchi Subject: [PATCH 4/6] mtd: mxs_nand: don't get the gpmi_apbh_dma clock Date: Tue, 27 Sep 2022 12:24:41 +0200 Message-Id: <20220927102443.1816168-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220927102443.1816168-1-dario.binacchi@amarulasolutions.com> References: <20220927102443.1816168-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=hTnSUMuN; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This clock name is not present in any U-boot and Linux kernel device tree. Fixes: commit a59691280daca ("MXS_NAND: Add clock support for iMX8") Signed-off-by: Dario Binacchi --- drivers/mtd/nand/raw/mxs_nand_dt.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/drivers/mtd/nand/raw/mxs_nand_dt.c b/drivers/mtd/nand/raw/mxs_nand_dt.c index b9833a646f01..c1e784832f33 100644 --- a/drivers/mtd/nand/raw/mxs_nand_dt.c +++ b/drivers/mtd/nand/raw/mxs_nand_dt.c @@ -143,19 +143,6 @@ static int mxs_nand_dt_probe(struct udevice *dev) debug("Can't enable gpmi_apb_bch clk: %d\n", ret); return ret; } - - /* this clock is used for apbh_dma, since the apbh dma does not support DM, - * we optionally enable it here - */ - ret = clk_get_by_name(dev, "gpmi_apbh_dma", &gpmi_clk); - if (ret < 0) { - debug("Can't get gpmi_apbh_dma clk: %d\n", ret); - } else { - ret = clk_enable(&gpmi_clk); - if (ret < 0) { - debug("Can't enable gpmi_apbh_dma clk: %d\n", ret); - } - } } return mxs_nand_init_ctrl(info); From patchwork Tue Sep 27 10:24:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2391 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-qk1-f199.google.com (mail-qk1-f199.google.com [209.85.222.199]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 46C7A3F1C8 for ; Tue, 27 Sep 2022 12:25:50 +0200 (CEST) Received: by mail-qk1-f199.google.com with SMTP id az15-20020a05620a170f00b006cece4cd0besf7024630qkb.22 for ; Tue, 27 Sep 2022 03:25:50 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1664274349; cv=pass; d=google.com; s=arc-20160816; b=X06rjZHybEGBiSi47EkoZBBysu4LfqQ9I63C/i0c1I90Lg07uFeUBGxo0SOmZOxsr7 /MZ8V/+bT6ukMVf2/nhKbgHANFP70dm1GJrEwg+mfk3rH9GfW2E2j1DE9Rt62zd0wq6e /DIsKT2cFaqkwiaXEIoFpY7fgDCdEoaM93qz5ni2yXj7vhDGFSbyXd1WVdvhN4R5F+W0 l3zfYyC/TY7ozv7uOfInffyCA++DIqAKjl9OSoUGVPRgagk/rthaxJMomqzoF+z4fJsP 5k+ACcRxd4nCkMxrYtvsgpdgQT2XeqUnPk73XaAYwbOmDM6KH5uan0HpzkbpxGx4s7KZ rXSg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=rXxuh7l4QZME07TAwaGBQB5cOyiV0tQSYvw9PmYuZq0=; b=mBZdloyuL3STkSMefS391hMcQreJwWXBb7Yxhrzxp+fx2nIU8eF/66nkYvBPObWrOn u0Vy5KJk7Tn4a+/4SW5h4I0pGw/yfscMsk+sADvmP7pWuNymAsT7Da41CvyOJMgohxQG +xeaKA6YmeQ6x2IQBJCsnP/l+6uPbjHSqe5hlBgfxLvwlio54oxlaIj47GiwJf6kds1q X58jY/Jzb5pcKwpaKiWJNgfkJO/PnVUfBp50V3NUw7oAaD7UmRTtaauo48GGHDAHAMHZ A7Wuzy9qs8376kpkA93BuRKVofsfP97kp4hieVnBENsrq66YqJpgLEOdmBeqy4X3VmeW 00aw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=YnySFrjd; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date; bh=rXxuh7l4QZME07TAwaGBQB5cOyiV0tQSYvw9PmYuZq0=; b=L1fEmsjxeVfgy8dU/pEGggB2a1Xsd5ILSZx5+gSRChfhn62T8r3he1Rz3MNvIehuU6 KTtGHD7ir+QuWcVRFxBRUNs5NHDgos733LwuhX8jTcsFihhSBrZmAyOnj/+0hOs60vFk JVP8/5RjXopZ+qMroDLgyA8nri3LWCnbRUIGk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date; bh=rXxuh7l4QZME07TAwaGBQB5cOyiV0tQSYvw9PmYuZq0=; b=zCzMHpTEhVtTIxXrUjBkGcFL4U4xx7Q0WfJmR+CMxpc/JciEE4xl9ifKAqyjUXA+Zb gEBOlT92MiKi2Bs+oCD5ui282ZfvRETAL1RGi8up2G+NivyN7/HFxBjAjvPFm2nkE8IP 7Z7tHNWmYA6ZVyDoBUKJGt5NQt7k2yb9zypm1we/80o6wSfljOyGcIq5NsMz5utkzaSj ZSZBuCxVMLa9GQvFh1DcUhDcB99dwFY4qvQ6yc8lLhmlK5wFpDsEipamaQ7DKO3pSRsh Leqel9yfhu8NOtXBjRSnoGLXDZz3lFO3ioOD77dWmBwu8C/pEhR9KJ/U+5mpaF8zBVP1 T9BQ== X-Gm-Message-State: ACrzQf2w8XA39JWyFWx8aSgqq8Eega9r2HxXS8CXEuiVr/PTQ94cpU3W ZH11GKL2+hKTkKMBr6+lhuzVxqGZ X-Google-Smtp-Source: AMsMyM5Kw7ah71tYV/iC+ybPRmVG3rfkAl7w8cVptlQnt2+dIUnwRkQLB9u9CCPGAkCpQQF1KgGeUw== X-Received: by 2002:ac8:5e51:0:b0:35c:e40f:d898 with SMTP id i17-20020ac85e51000000b0035ce40fd898mr21600568qtx.685.1664274349310; Tue, 27 Sep 2022 03:25:49 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a0c:8d8a:0:b0:4aa:a12f:3556 with SMTP id t10-20020a0c8d8a000000b004aaa12f3556ls1098440qvb.6.-pod-prod-gmail; Tue, 27 Sep 2022 03:25:48 -0700 (PDT) X-Received: by 2002:ad4:594e:0:b0:4ad:5d6d:137d with SMTP id eo14-20020ad4594e000000b004ad5d6d137dmr20652124qvb.125.1664274348715; Tue, 27 Sep 2022 03:25:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664274348; cv=none; d=google.com; s=arc-20160816; b=WwcjhhaQyCqI8FFrhhALVbzSyo7QbqleC6EYoUEPoTBrfeb2wf8q9l0s/TqMJ8qFV6 YaLe3+urw1rN9vCXi5gGV2diDogtKmrGANZG+QwKBjBaLtPaGh2fkzY6wFSOAyqV/9GL 4u0Ede/q5XqCJBZgUfYnMeGRQYlCcJH3jjQ5vJGeVIzNp42i9OEuqiLhhMJ/79xWJptB cWcqwwvV+hszerQkvjln6Q3Ar4DNDJ28T99W7tYW9zw8BcecmVyztA9NLbDEYL8V/eCZ shhcx9i1OW+5nlgg5aw6RpfrtykfBpwpPGrvwj7RKS716fHm3ETNuWtRkIOFjj8aGKEa sN5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=qxRifoF09ZiTT0TIB3VV1imho2MAnwgjaHJMUL83XxU=; b=ayg1UPEZNvGZGI9iu9fSv5yW1WaXabs/iChgOD4ow9arBAfeesdeTL2sRl/e7sj0Vs dezBmyE5K/UHxCRw5m5viuFNaqkkP5WdYUVwK+TAui+OOJgIAMjjdFQrSNnH/aUPBZXh XkdRq3tGL9EGAO8CZ2r+kA+7uRHG4I3Mq7ALBxTctu3z02HEIOeb/V6Li6+Bxy835ptN kzdBJBsXGhP4ThuyAxMHcRMS+/x0nvYwlu0bmOfQ/PVS1cizcjdPr995qjRd3xQ2TYdG CeAPQPICH6CFsNt2iqETjKTjtn60Gx9YfPsRwAINFq/F0bYYIeoD/9lPtJ2xtwfW6Zjt FESg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=YnySFrjd; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id dm4-20020a05620a1d4400b006cf8361b727sor285827qkb.13.2022.09.27.03.25.48 for (Google Transport Security); Tue, 27 Sep 2022 03:25:48 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a05:620a:bcd:b0:6cf:a7b9:44ce with SMTP id s13-20020a05620a0bcd00b006cfa7b944cemr4435280qki.38.1664274348207; Tue, 27 Sep 2022 03:25:48 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.pdxnet.pdxeng.ch (host-95-232-92-192.retail.telecomitalia.it. [95.232.92.192]) by smtp.gmail.com with ESMTPSA id d11-20020a05620a240b00b006be8713f742sm752220qkn.38.2022.09.27.03.25.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Sep 2022 03:25:47 -0700 (PDT) From: Dario Binacchi To: linux-amarula@amarulasolutions.com Cc: michael@amarulasolutions.com, Dario Binacchi Subject: [PATCH 5/6] mtd: mxs_nand: get the clock with the right name Date: Tue, 27 Sep 2022 12:24:42 +0200 Message-Id: <20220927102443.1816168-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220927102443.1816168-1-dario.binacchi@amarulasolutions.com> References: <20220927102443.1816168-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=YnySFrjd; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Rename the gpmi_apb_bch clock name to gpmi_bch_apb, as you can find in the device tree. Fixes: commit a59691280daca ("MXS_NAND: Add clock support for iMX8") Signed-off-by: Dario Binacchi --- drivers/mtd/nand/raw/mxs_nand_dt.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/nand/raw/mxs_nand_dt.c b/drivers/mtd/nand/raw/mxs_nand_dt.c index c1e784832f33..94ee7ed9ec83 100644 --- a/drivers/mtd/nand/raw/mxs_nand_dt.c +++ b/drivers/mtd/nand/raw/mxs_nand_dt.c @@ -132,15 +132,15 @@ static int mxs_nand_dt_probe(struct udevice *dev) return ret; } - ret = clk_get_by_name(dev, "gpmi_apb_bch", &gpmi_clk); + ret = clk_get_by_name(dev, "gpmi_bch_apb", &gpmi_clk); if (ret < 0) { - debug("Can't get gpmi_apb_bch clk: %d\n", ret); + debug("Can't get gpmi_bch_apb clk: %d\n", ret); return ret; } ret = clk_enable(&gpmi_clk); if (ret < 0) { - debug("Can't enable gpmi_apb_bch clk: %d\n", ret); + debug("Can't enable gpmi_bch_apb clk: %d\n", ret); return ret; } } From patchwork Tue Sep 27 10:24:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2392 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-qk1-f200.google.com (mail-qk1-f200.google.com [209.85.222.200]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 4C5AB3F1C8 for ; Tue, 27 Sep 2022 12:25:54 +0200 (CEST) Received: by mail-qk1-f200.google.com with SMTP id f12-20020a05620a408c00b006ced53b80e5sf6984656qko.17 for ; Tue, 27 Sep 2022 03:25:54 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1664274353; cv=pass; d=google.com; s=arc-20160816; b=G+4U7MXnz2tmW3I7fD/d2g4IRWF7qZuunKDEP7EQAdRX2gBotsALuL4+mKnA8KkkAm Z071KSnGF6rh0nrKuJ3BrZBnQqfPYVD8P1QFNn5DO+bkROTBdlvICu/hsZwsZq3yHI3n irrSaiUPh0HwZu5T+Q+0KpN/dn1UzpXlulIQ6PMltyhgKYzB5ZMIgcguscpwZBQs1Eef RPGUemWJTaWrxsZzLhR5Ao2U68iSasr6RsiliakBy7LY0APB6d/lPxvgFEdoxU25tkKr Siv91TvQ0VKJC2p899nsoeFN7hADxbfrTM7OT33xvmX8fT9f2hA4Cn5XtK7sXHsBGJxI DF6A== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=IEAU1bo4TM6+E16rIDOjMSOIYjwCsfBozn3lJ3qjKyc=; b=tJS0kAfKQG9ZLX9zNYOsoERoSqcOl0U7+kCOCNrUqPy4GGvL0V8kpF2YJj3rapmv8d QZDb3JlytlJw14LbHsj/ytywXFoCRxmvNbWk3s61CsnjHpf6f5VxvaUjHlRxGYdog/MP EJVDDHCzWkGkbFn5xNVoL5ca3DslIBC3+VCi/g8xXbK4hZfjEZ+jWMwZIMVL3LE3rE8W DlbhdvzTB1KSdR4tuum3ZU+LjdaUUX416pb4ZFPg+srR29ZPo1+W2TYRbmGBCAL+PsDg JWNUQCo8SodiR1qWZ/KW+rTEfd5f6iY8I8EsMPzLQ60mz4nWQTb+noTmEjsGbdNbTcJt LGhA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=pg28ZVXV; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date; bh=IEAU1bo4TM6+E16rIDOjMSOIYjwCsfBozn3lJ3qjKyc=; b=UO1RiIA8jUYMs7KGx881TWxGvPIN+2GKVCgVIJp/2gMVXe4OwlPrhb+Fe5/hf9A9fc /ODHO6DlJS8Qm9UQULwu9dctFxBoxHp93VMyHwmIQboxw8dPR/GgVbfLiE6pzZoYLMv2 YLHOAIEo7BnbjiZppjgJ9YRznV8saUIX3gp/g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date; bh=IEAU1bo4TM6+E16rIDOjMSOIYjwCsfBozn3lJ3qjKyc=; b=UFOneBGVIPLql6XhEo5c3cfEVE/+1HKTA//MB3e7j5UZuOFXPCc/6u1nq5W1n449pf zX+R0KTdpYnFf/sabrHd0vOpekWJbjbsy+SGj33uTaQZ/8eLDnNPTIckVmRQmbrx38tE Mc1/s7tbz55ShkavCLp+6RnJebxNx4jIH+x80rW+Ng+fYnvlkvWreOTz7fYWpRxJ/LUi rYsNcQeDuYORc4ch2aeY0+u6GLPxc7LY8+/cHqQacMvwUhQ4lsrd541hZQGJ/q4cv7na icL10bMYiyyxIahUKgLu5cyiNqv74vtkZAgWaNCRKZCJV4OalHnXjSTDNnUr5oM/uDHI NVEQ== X-Gm-Message-State: ACrzQf1dh8lehDLCUvBEdW++DFeBS4bQJbTRMbX7vZ2lZyHhHNFEPqnd 4bvg2wAM93mKdBI81UzdP1+dvL4U X-Google-Smtp-Source: AMsMyM60dWwJpuzA15xnDE7gm0uwlbAI1lBc4BHS3P3ui7jt/YdjBXeOHEAahAxaqzTa/iLwW3Hxxw== X-Received: by 2002:a05:6214:20a6:b0:4ac:ba17:e20f with SMTP id 6-20020a05621420a600b004acba17e20fmr21139470qvd.101.1664274353336; Tue, 27 Sep 2022 03:25:53 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:ac8:5298:0:b0:35c:f240:4bfd with SMTP id s24-20020ac85298000000b0035cf2404bfdls1407850qtn.4.-pod-prod-gmail; Tue, 27 Sep 2022 03:25:52 -0700 (PDT) X-Received: by 2002:a05:622a:3d4:b0:35c:fc79:684d with SMTP id k20-20020a05622a03d400b0035cfc79684dmr21813370qtx.331.1664274352704; Tue, 27 Sep 2022 03:25:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664274352; cv=none; d=google.com; s=arc-20160816; b=rHU1uSpXDeooO0+aLpTEHFOqyAGo5xztiJnvEkEnXbvmgzmYnLRh2q55P0XurD0YO/ C9TcR349D/rDjGMe4oNtMzxvqGFxu2oSv2S1kUFUZ6ccFO+NzetBYGquyJNM1JCm8vLj eXuZC21NPmNl5sX52QBzG2VlfDkae9GESor/cN3JlkvVvRQj8bJL1QWC8hXFuqSKJc2e lDKkR7xUjfbDWyKv8gykq5j+2f5HeRoNSUzA8OHm6ZMwxcyxPxXwuhaAjfV84XF4sSJd MbfQUazORzaY+oE1ItKs/sHm294ZxD2Y95p+Vmfbs8UkyRfVsfiVGgwhv50w5Q4zH62x sklA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=1drZW2xETy3lTFU3GTxoZL8qNeiXk22X8/XCBPr1lx0=; b=FqgimBLGtBCjYmrurJiGcauNw7PMAm1LCKk4vMkhcSnabM/DK9Ue7ilGXLWKakuoh+ M+8oEcGp9O0MvIq5IDuZGXeZvw3OhxIlSF3Y/3XDTakP1PHYjnFUMxEGBz2sk7LC+pjJ NURgMFKhFRJBP7ZgJvJvNZe4YYuI6xiBobtfAsT2qh6PEWGXLJVmsVr5lx4BC8H40cPd m3PTly5e2OgVIoHUgwolnzABGYTENXGQ/r6OCGq8V0aBh/z7n0rLwwm/lJ4wvw5tugi+ cAUQXM359DLHk2Oz/iw3dtCIabdgCjkYka+WpTy6BZSK0bTP0PpTOKuXNudJ5XJ6f/jM 2znQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=pg28ZVXV; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id q15-20020a056214194f00b004ad77b613bfsor781384qvk.31.2022.09.27.03.25.52 for (Google Transport Security); Tue, 27 Sep 2022 03:25:52 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a05:6214:2aaa:b0:4ac:acbd:7ef8 with SMTP id js10-20020a0562142aaa00b004acacbd7ef8mr20466699qvb.126.1664274351995; Tue, 27 Sep 2022 03:25:51 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.pdxnet.pdxeng.ch (host-95-232-92-192.retail.telecomitalia.it. [95.232.92.192]) by smtp.gmail.com with ESMTPSA id d11-20020a05620a240b00b006be8713f742sm752220qkn.38.2022.09.27.03.25.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Sep 2022 03:25:51 -0700 (PDT) From: Dario Binacchi To: linux-amarula@amarulasolutions.com Cc: michael@amarulasolutions.com, Dario Binacchi Subject: [PATCH 6/6] mtd: mxs_nand: Support EDO mode for imx8mn architecture Date: Tue, 27 Sep 2022 12:24:43 +0200 Message-Id: <20220927102443.1816168-6-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220927102443.1816168-1-dario.binacchi@amarulasolutions.com> References: <20220927102443.1816168-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=pg28ZVXV; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Michael Trimarchi Add support for imx8mn architecture in order to run the NAND in fast edo mode Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi --- drivers/mtd/nand/raw/mxs_nand.c | 202 +++++++++++++++++++++++++++++ drivers/mtd/nand/raw/mxs_nand_dt.c | 66 ++++++---- include/mxs_nand.h | 3 + 3 files changed, 244 insertions(+), 27 deletions(-) diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index 7893e9d7e343..4439f9846013 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -14,6 +14,7 @@ */ #include +#include #include #include #include @@ -26,10 +27,12 @@ #include #include #include +#include #include #include #include #include +#include #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4 @@ -49,6 +52,10 @@ #endif #define MXS_NAND_BCH_TIMEOUT 10000 +#define USEC_PER_SEC 1000000 +#define NSEC_PER_SEC 1000000000L + +#define TO_CYCLES(duration, period) DIV_ROUND_UP_ULL(duration, period) struct nand_ecclayout fake_ecc_layout; @@ -1344,6 +1351,198 @@ err1: return ret; } +/* + * <1> Firstly, we should know what's the GPMI-clock means. + * The GPMI-clock is the internal clock in the gpmi nand controller. + * If you set 100MHz to gpmi nand controller, the GPMI-clock's period + * is 10ns. Mark the GPMI-clock's period as GPMI-clock-period. + * + * <2> Secondly, we should know what's the frequency on the nand chip pins. + * The frequency on the nand chip pins is derived from the GPMI-clock. + * We can get it from the following equation: + * + * F = G / (DS + DH) + * + * F : the frequency on the nand chip pins. + * G : the GPMI clock, such as 100MHz. + * DS : GPMI_HW_GPMI_TIMING0:DATA_SETUP + * DH : GPMI_HW_GPMI_TIMING0:DATA_HOLD + * + * <3> Thirdly, when the frequency on the nand chip pins is above 33MHz, + * the nand EDO(extended Data Out) timing could be applied. + * The GPMI implements a feedback read strobe to sample the read data. + * The feedback read strobe can be delayed to support the nand EDO timing + * where the read strobe may deasserts before the read data is valid, and + * read data is valid for some time after read strobe. + * + * The following figure illustrates some aspects of a NAND Flash read: + * + * |<---tREA---->| + * | | + * | | | + * |<--tRP-->| | + * | | | + * __ ___|__________________________________ + * RDN \________/ | + * | + * /---------\ + * Read Data --------------< >--------- + * \---------/ + * | | + * |<-D->| + * FeedbackRDN ________ ____________ + * \___________/ + * + * D stands for delay, set in the HW_GPMI_CTRL1:RDN_DELAY. + * + * + * <4> Now, we begin to describe how to compute the right RDN_DELAY. + * + * 4.1) From the aspect of the nand chip pins: + * Delay = (tREA + C - tRP) {1} + * + * tREA : the maximum read access time. + * C : a constant to adjust the delay. default is 4000ps. + * tRP : the read pulse width, which is exactly: + * tRP = (GPMI-clock-period) * DATA_SETUP + * + * 4.2) From the aspect of the GPMI nand controller: + * Delay = RDN_DELAY * 0.125 * RP {2} + * + * RP : the DLL reference period. + * if (GPMI-clock-period > DLL_THRETHOLD) + * RP = GPMI-clock-period / 2; + * else + * RP = GPMI-clock-period; + * + * Set the HW_GPMI_CTRL1:HALF_PERIOD if GPMI-clock-period + * is greater DLL_THRETHOLD. In other SOCs, the DLL_THRETHOLD + * is 16000ps, but in mx6q, we use 12000ps. + * + * 4.3) since {1} equals {2}, we get: + * + * (tREA + 4000 - tRP) * 8 + * RDN_DELAY = ----------------------- {3} + * RP + */ +static void mxs_compute_timings(struct nand_chip *chip, + const struct nand_sdr_timings *sdr) +{ + struct mxs_nand_info *nand_info = nand_get_controller_data(chip); + unsigned long int clk_rate; + unsigned int dll_wait_time_us; + unsigned int dll_threshold_ps = nand_info->max_chain_delay; + unsigned int period_ps, reference_period_ps; + unsigned int data_setup_cycles, data_hold_cycles, addr_setup_cycles; + unsigned int tRP_ps; + bool use_half_period; + int sample_delay_ps, sample_delay_factor; + u16 busy_timeout_cycles; + u8 wrn_dly_sel; + u32 timing0; + u32 timing1; + u32 ctrl1n; + + if (sdr->tRC_min >= 30000) { + /* ONFI non-EDO modes [0-3] */ + clk_rate = 22000000; + wrn_dly_sel = GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS; + } else if (sdr->tRC_min >= 25000) { + /* ONFI EDO mode 4 */ + clk_rate = 80000000; + wrn_dly_sel = GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY; + debug("%s, setting ONFI onfi edo 4\n", __func__); + } else { + /* ONFI EDO mode 5 */ + clk_rate = 100000000; + wrn_dly_sel = GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY; + debug("%s, setting ONFI onfi edo 5\n", __func__); + } + + /* SDR core timings are given in picoseconds */ + period_ps = div_u64((u64)NSEC_PER_SEC * 1000, clk_rate); + + addr_setup_cycles = TO_CYCLES(sdr->tALS_min, period_ps); + data_setup_cycles = TO_CYCLES(sdr->tDS_min, period_ps); + data_hold_cycles = TO_CYCLES(sdr->tDH_min, period_ps); + busy_timeout_cycles = TO_CYCLES(sdr->tWB_max + sdr->tR_max, period_ps); + + timing0 = (addr_setup_cycles << GPMI_TIMING0_ADDRESS_SETUP_OFFSET) | + (data_hold_cycles << GPMI_TIMING0_DATA_HOLD_OFFSET) | + (data_setup_cycles << GPMI_TIMING0_DATA_SETUP_OFFSET); + timing1 = (busy_timeout_cycles * 4096) << GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_OFFSET; + + /* + * Derive NFC ideal delay from {3}: + * + * (tREA + 4000 - tRP) * 8 + * RDN_DELAY = ----------------------- + * RP + */ + if (period_ps > dll_threshold_ps) { + use_half_period = true; + reference_period_ps = period_ps / 2; + } else { + use_half_period = false; + reference_period_ps = period_ps; + } + + tRP_ps = data_setup_cycles * period_ps; + sample_delay_ps = (sdr->tREA_max + 4000 - tRP_ps) * 8; + if (sample_delay_ps > 0) + sample_delay_factor = sample_delay_ps / reference_period_ps; + else + sample_delay_factor = 0; + + ctrl1n = (wrn_dly_sel << GPMI_CTRL1_WRN_DLY_SEL_OFFSET); + if (sample_delay_factor) + ctrl1n |= (sample_delay_factor << GPMI_CTRL1_RDN_DELAY_OFFSET) | + GPMI_CTRL1_DLL_ENABLE | + (use_half_period ? GPMI_CTRL1_HALF_PERIOD : 0); + + + writel(timing0, &nand_info->gpmi_regs->hw_gpmi_timing0); + writel(timing1, &nand_info->gpmi_regs->hw_gpmi_timing1); + + /* + * Clear several CTRL1 fields, DLL must be disabled when setting + * RDN_DELAY or HALF_PERIOD. + */ + writel(GPMI_CTRL1_CLEAR_MASK, &nand_info->gpmi_regs->hw_gpmi_ctrl1_clr); + writel(ctrl1n, &nand_info->gpmi_regs->hw_gpmi_ctrl1_set); + + clk_set_rate(nand_info->gpmi_clk, clk_rate); + + /* Wait 64 clock cycles before using the GPMI after enabling the DLL */ + dll_wait_time_us = USEC_PER_SEC / clk_rate * 64; + if (!dll_wait_time_us) + dll_wait_time_us = 1; + + /* Wait for the DLL to settle. */ + udelay(dll_wait_time_us); +} + +static int mxs_nand_setup_interface(struct mtd_info *mtd, int chipnr, + const struct nand_data_interface *conf) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + const struct nand_sdr_timings *sdr; + + + sdr = nand_get_sdr_timings(conf); + if (IS_ERR(sdr)) + return PTR_ERR(sdr); + + /* Stop here if this call was just a check */ + if (chipnr < 0) + return 0; + + /* Do the actual derivation of the controller timings */ + mxs_compute_timings(chip, sdr); + + return 0; +} + int mxs_nand_init_spl(struct nand_chip *nand) { struct mxs_nand_info *nand_info; @@ -1432,6 +1631,9 @@ int mxs_nand_init_ctrl(struct mxs_nand_info *nand_info) nand->read_buf = mxs_nand_read_buf; nand->write_buf = mxs_nand_write_buf; + if (nand_info->gpmi_clk) + nand->setup_data_interface = mxs_nand_setup_interface; + /* first scan to find the device and get the page size */ if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) goto err_free_buffers; diff --git a/drivers/mtd/nand/raw/mxs_nand_dt.c b/drivers/mtd/nand/raw/mxs_nand_dt.c index 94ee7ed9ec83..102143d28a81 100644 --- a/drivers/mtd/nand/raw/mxs_nand_dt.c +++ b/drivers/mtd/nand/raw/mxs_nand_dt.c @@ -22,22 +22,27 @@ struct mxs_nand_dt_data { unsigned int max_ecc_strength_supported; + int max_chain_delay; /* See the async EDO mode */ }; static const struct mxs_nand_dt_data mxs_nand_imx6q_data = { .max_ecc_strength_supported = 40, + .max_chain_delay = 12000, }; static const struct mxs_nand_dt_data mxs_nand_imx6sx_data = { .max_ecc_strength_supported = 62, + .max_chain_delay = 12000, }; static const struct mxs_nand_dt_data mxs_nand_imx7d_data = { .max_ecc_strength_supported = 62, + .max_chain_delay = 12000, }; static const struct mxs_nand_dt_data mxs_nand_imx8qxp_data = { .max_ecc_strength_supported = 62, + .max_chain_delay = 12000, }; static const struct udevice_id mxs_nand_dt_ids[] = { @@ -72,8 +77,10 @@ static int mxs_nand_dt_probe(struct udevice *dev) int ret; data = (void *)dev_get_driver_data(dev); - if (data) + if (data) { info->max_ecc_strength_supported = data->max_ecc_strength_supported; + info->max_chain_delay = data->max_chain_delay; + } info->dev = dev; @@ -92,44 +99,49 @@ static int mxs_nand_dt_probe(struct udevice *dev) info->use_minimum_ecc = dev_read_bool(dev, "fsl,use-minimum-ecc"); - if (IS_ENABLED(CONFIG_CLK) && IS_ENABLED(CONFIG_IMX8)) { + if (IS_ENABLED(CONFIG_CLK) && + (IS_ENABLED(CONFIG_IMX8) || IS_ENABLED(CONFIG_IMX8M))) { /* Assigned clock already set clock */ struct clk gpmi_clk; - ret = clk_get_by_name(dev, "gpmi_io", &gpmi_clk); - if (ret < 0) { + info->gpmi_clk = devm_clk_get(dev, "gpmi_io"); + + if (IS_ERR(info->gpmi_clk)) { + ret = PTR_ERR(info->gpmi_clk); debug("Can't get gpmi io clk: %d\n", ret); return ret; } - ret = clk_enable(&gpmi_clk); + ret = clk_enable(info->gpmi_clk); if (ret < 0) { debug("Can't enable gpmi io clk: %d\n", ret); return ret; } - ret = clk_get_by_name(dev, "gpmi_apb", &gpmi_clk); - if (ret < 0) { - debug("Can't get gpmi_apb clk: %d\n", ret); - return ret; - } - - ret = clk_enable(&gpmi_clk); - if (ret < 0) { - debug("Can't enable gpmi_apb clk: %d\n", ret); - return ret; - } - - ret = clk_get_by_name(dev, "gpmi_bch", &gpmi_clk); - if (ret < 0) { - debug("Can't get gpmi_bch clk: %d\n", ret); - return ret; - } - - ret = clk_enable(&gpmi_clk); - if (ret < 0) { - debug("Can't enable gpmi_bch clk: %d\n", ret); - return ret; + if (IS_ENABLED(CONFIG_IMX8)) { + ret = clk_get_by_name(dev, "gpmi_apb", &gpmi_clk); + if (ret < 0) { + debug("Can't get gpmi_apb clk: %d\n", ret); + return ret; + } + + ret = clk_enable(&gpmi_clk); + if (ret < 0) { + debug("Can't enable gpmi_apb clk: %d\n", ret); + return ret; + } + + ret = clk_get_by_name(dev, "gpmi_bch", &gpmi_clk); + if (ret < 0) { + debug("Can't get gpmi_bch clk: %d\n", ret); + return ret; + } + + ret = clk_enable(&gpmi_clk); + if (ret < 0) { + debug("Can't enable gpmi_bch clk: %d\n", ret); + return ret; + } } ret = clk_get_by_name(dev, "gpmi_bch_apb", &gpmi_clk); diff --git a/include/mxs_nand.h b/include/mxs_nand.h index 741dc8734eae..bb5b84b8c26e 100644 --- a/include/mxs_nand.h +++ b/include/mxs_nand.h @@ -12,6 +12,7 @@ #include #include #include +#include /** * @gf_len: The length of Galois Field. (e.g., 13 or 14) @@ -43,6 +44,7 @@ struct mxs_nand_info { struct nand_chip chip; struct udevice *dev; unsigned int max_ecc_strength_supported; + int max_chain_delay; bool use_minimum_ecc; int cur_chip; @@ -59,6 +61,7 @@ struct mxs_nand_info { struct mxs_gpmi_regs *gpmi_regs; struct mxs_bch_regs *bch_regs; + struct clk *gpmi_clk; /* Functions with altered behaviour */ int (*hooked_read_oob)(struct mtd_info *mtd,