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[95.233.42.253]) by smtp.gmail.com with ESMTPSA id b27-20020a17090630db00b0073dbaeb50f6sm9237983ejb.169.2022.10.19.10.20.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 10:20:23 -0700 (PDT) From: Dario Binacchi To: linux-amarula@amarulasolutions.com Cc: anthony@amarulasolutions.com, jagan@amarulasolutions.com, dario.binacchi@amarulasolutions.com, michael@amarulasolutions.com, tommaso.merciai@amarulasolutions.com Subject: [RFC PATCH 1/8] clk: imx: add structure to extend register accesses Date: Wed, 19 Oct 2022 19:20:12 +0200 Message-Id: <20221019172019.2303223-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221019172019.2303223-1-dario.binacchi@amarulasolutions.com> References: <20221019172019.2303223-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=r1gkfl+m; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Signed-off-by: Dario Binacchi --- drivers/clk/imx/clk.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index a7cbbcd1a3f4..802afb3481c4 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -88,6 +88,17 @@ struct imx_fracn_gppll_clk { int flags; }; +/** + * struct clk_omap_reg - OMAP register declaration + * @offset: offset from the master IP module base address + * @index: index of the master IP module + */ +struct imx_clk_iomap { + void __iomem *mem; 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[95.233.42.253]) by smtp.gmail.com with ESMTPSA id b27-20020a17090630db00b0073dbaeb50f6sm9237983ejb.169.2022.10.19.10.20.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 10:20:24 -0700 (PDT) From: Dario Binacchi To: linux-amarula@amarulasolutions.com Cc: anthony@amarulasolutions.com, jagan@amarulasolutions.com, dario.binacchi@amarulasolutions.com, michael@amarulasolutions.com, tommaso.merciai@amarulasolutions.com Subject: [RFC PATCH 2/8] clk: imx: add imx_dt_clk_name() helper to use clock-output-names Date: Wed, 19 Oct 2022 19:20:13 +0200 Message-Id: <20221019172019.2303223-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221019172019.2303223-1-dario.binacchi@amarulasolutions.com> References: <20221019172019.2303223-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=Vx3XJK4L; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Let's create the clock alias based on the clock-output-names property if available. Also the component clock drivers can use imx_dt_clk_name() in the following patches. Signed-off-by: Dario Binacchi --- drivers/clk/imx/clk.c | 11 +++++++++++ drivers/clk/imx/clk.h | 2 ++ 2 files changed, 13 insertions(+) diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c index 7cc669934253..96db803647f4 100644 --- a/drivers/clk/imx/clk.c +++ b/drivers/clk/imx/clk.c @@ -17,6 +17,17 @@ DEFINE_SPINLOCK(imx_ccm_lock); EXPORT_SYMBOL_GPL(imx_ccm_lock); +const char *imx_dt_clk_name(struct device_node *np) +{ + const char *name; + + if (!of_property_read_string_index(np, "clock-output-names", 0, + &name)) + return name; + + return np->name; +} + void imx_unregister_clocks(struct clk *clks[], unsigned int count) { unsigned int i; diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 802afb3481c4..e3262ce035f7 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -99,6 +99,8 @@ struct imx_clk_iomap { u16 offset; }; +const char *imx_dt_clk_name(struct device_node *np); + struct clk_hw *imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base, const struct imx_fracn_gppll_clk *pll_clk); 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[209.85.220.41]) by mx.google.com with SMTPS id h26-20020a1709066d9a00b0078183bda914sor7391047ejt.37.2022.10.19.10.20.26 for (Google Transport Security); Wed, 19 Oct 2022 10:20:26 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:906:d54d:b0:78e:2fbf:ca2a with SMTP id cr13-20020a170906d54d00b0078e2fbfca2amr7851889ejc.488.1666200025784; Wed, 19 Oct 2022 10:20:25 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-95-233-42-253.retail.telecomitalia.it. [95.233.42.253]) by smtp.gmail.com with ESMTPSA id b27-20020a17090630db00b0073dbaeb50f6sm9237983ejb.169.2022.10.19.10.20.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 10:20:25 -0700 (PDT) From: Dario Binacchi To: linux-amarula@amarulasolutions.com Cc: anthony@amarulasolutions.com, jagan@amarulasolutions.com, dario.binacchi@amarulasolutions.com, michael@amarulasolutions.com, tommaso.merciai@amarulasolutions.com Subject: [RFC PATCH 3/8] clk: imx: add imx_get_clk_hw_from_dt() helper Date: Wed, 19 Oct 2022 19:20:14 +0200 Message-Id: <20221019172019.2303223-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221019172019.2303223-1-dario.binacchi@amarulasolutions.com> References: <20221019172019.2303223-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=Wj7lt+pp; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Signed-off-by: Dario Binacchi --- drivers/clk/imx/clk.c | 21 +++++++++++++++++++++ drivers/clk/imx/clk.h | 3 +++ 2 files changed, 24 insertions(+) diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c index 96db803647f4..39034a7b73cd 100644 --- a/drivers/clk/imx/clk.c +++ b/drivers/clk/imx/clk.c @@ -76,6 +76,27 @@ void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count) } EXPORT_SYMBOL_GPL(imx_check_clk_hws); +struct clk_hw *imx_get_clk_hw_from_dt(struct device_node *np, + const char *name) +{ + struct of_phandle_args clkspec; + struct clk *clk; + + clkspec.np = of_find_node_by_name(np, name); + if (clkspec.np) { + clk = of_clk_get_from_provider(&clkspec); + if (!IS_ERR(clk)) { + pr_debug("%s: got %s clock\n", __func__, name); + of_node_put(clkspec.np); + return __clk_get_hw(clk); + } + } + + pr_err("%s: failed to %s clock\n", __func__, name); + return ERR_PTR(-ENODEV); +} +EXPORT_SYMBOL_GPL(imx_get_clk_hw_from_dt); + static struct clk *imx_obtain_fixed_clock_from_dt(const char *name) { struct of_phandle_args phandle; diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index e3262ce035f7..1daeaf1e4729 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -294,6 +294,9 @@ struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name, u8 clk_gate_flags, spinlock_t *lock, unsigned int *share_count); +struct clk_hw *imx_get_clk_hw_from_dt(struct device_node *np, + const char *name); + struct clk * imx_obtain_fixed_clock( const char *name, unsigned long rate); From patchwork Wed Oct 19 17:20:15 2022 Content-Type: text/plain; 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[95.233.42.253]) by smtp.gmail.com with ESMTPSA id b27-20020a17090630db00b0073dbaeb50f6sm9237983ejb.169.2022.10.19.10.20.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 10:20:26 -0700 (PDT) From: Dario Binacchi To: linux-amarula@amarulasolutions.com Cc: anthony@amarulasolutions.com, jagan@amarulasolutions.com, dario.binacchi@amarulasolutions.com, michael@amarulasolutions.com, tommaso.merciai@amarulasolutions.com Subject: [RFC PATCH 4/8] clk: imx: add support for imx8mn gate clock Date: Wed, 19 Oct 2022 19:20:15 +0200 Message-Id: <20221019172019.2303223-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221019172019.2303223-1-dario.binacchi@amarulasolutions.com> References: <20221019172019.2303223-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=AWVK4yfV; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This patch adds support for freescale imx8mn gate clock. Let's start with this specific clock driver and hope that other variants can be handled in the future as well. Signed-off-by: Dario Binacchi --- drivers/clk/imx/Makefile | 1 + drivers/clk/imx/clk-gate.c | 180 +++++++++++++++++++++++++++++++++++++ 2 files changed, 181 insertions(+) create mode 100644 drivers/clk/imx/clk-gate.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 88b9b9285d22..539add92be47 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -11,6 +11,7 @@ mxc-clk-objs += clk-divider-gate.o mxc-clk-objs += clk-fixup-div.o mxc-clk-objs += clk-fixup-mux.o mxc-clk-objs += clk-frac-pll.o +mxc-clk-objs += clk-gate.o mxc-clk-objs += clk-gate2.o mxc-clk-objs += clk-gate-exclusive.o mxc-clk-objs += clk-pfd.o diff --git a/drivers/clk/imx/clk-gate.c b/drivers/clk/imx/clk-gate.c new file mode 100644 index 000000000000..70b0d95e8f3d --- /dev/null +++ b/drivers/clk/imx/clk-gate.c @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Amarula Solutions + * + * Dario Binacchi + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +#define to_clk_imx_gate(_hw) container_of(_hw, struct clk_imx_gate, hw) + +struct clk_imx_gate { + struct clk_hw hw; + struct imx_clk_iomap iomap; + u32 enable_mask; +}; + +static int imx_clk_gate_enable(struct clk_hw *hw) +{ + struct clk_imx_gate *gate = to_clk_imx_gate(hw); + struct imx_clk_iomap *io = &gate->iomap; + + return regmap_update_bits(io->regmap, io->offset, gate->enable_mask, + gate->enable_mask); +} + +static void imx_clk_gate_disable(struct clk_hw *hw) +{ + struct clk_imx_gate *gate = to_clk_imx_gate(hw); + struct imx_clk_iomap *io = &gate->iomap; + + regmap_update_bits(io->regmap, io->offset, gate->enable_mask, 0); +} + +static int imx_clk_gate_is_enabled(struct clk_hw *hw) +{ + struct clk_imx_gate *gate = to_clk_imx_gate(hw); + struct imx_clk_iomap *io = &gate->iomap; + unsigned int val; + + if (regmap_read(io->regmap, io->offset, &val)) + return -EIO; + + return !!(val & gate->enable_mask); +} + +const struct clk_ops imx_clk_gate_ops = { + .enable = &imx_clk_gate_enable, + .disable = &imx_clk_gate_disable, + .is_enabled = &imx_clk_gate_is_enabled, +}; + +static void imx_clk_hw_unregister_gate(struct clk_hw *hw) +{ + struct clk_imx_gate *gate = to_clk_imx_gate(hw); + + clk_hw_unregister(hw); + kfree(gate); +} + +static struct clk_hw *imx_clk_hw_register_gate(struct device *dev, + const char *name, + const char *parent_name, + unsigned long flags, + struct imx_clk_iomap *iomap, + u8 enable_bit) +{ + struct clk_init_data init = { NULL }; + struct clk_imx_gate *gate; + struct clk_hw *hw; + int ret; + + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.flags = flags; + init.ops = &imx_clk_gate_ops; + init.parent_names = &parent_name; + init.num_parents = 1; + + memcpy(&gate->iomap, iomap, sizeof(*iomap)); + gate->enable_mask = BIT(enable_bit); + gate->hw.init = &init; + + hw = &gate->hw; + ret = clk_hw_register(dev, hw); + if (ret) { + kfree(gate); + return ERR_PTR(ret); + } + + return hw; +} + +static struct clk_hw *_of_imx_gate_clk_setup(struct device_node *node) +{ + struct clk_hw *hw; + struct imx_clk_iomap io; + struct device_node *parent_node; + const char *name, *parent_name; + u8 enable_bit = 0; + u32 val; + int ret; + + parent_node = of_get_parent(node); + if (!parent_node) { + pr_err("%s: %pOFn must have 1 parent\n", __func__, node); + return ERR_PTR(-ENODEV); + } + + io.regmap = syscon_node_to_regmap(parent_node); + of_node_put(parent_node); + if (IS_ERR(io.regmap)) { + pr_err("%s: missing regmap for %pOFn\n", __func__, node); + return ERR_CAST(io.regmap); + } + + if (of_property_read_u32(node, "fsl,regmap-offset", &val)) { + pr_err("%s: missing regmap offset for %pOFn\n", __func__, + node); + return ERR_PTR(-EIO); + } + + io.offset = val; + + if (!of_property_read_u32(node, "fsl,bit-shift", &val)) + enable_bit = val; + + if (of_clk_get_parent_count(node) != 1) { + pr_err("%s: %pOFn must have 1 parent clock\n", __func__, node); + return ERR_PTR(-EIO); + } + + parent_name = of_clk_get_parent_name(node, 0); + name = imx_dt_clk_name(node); + + hw = imx_clk_hw_register_gate(NULL, name, parent_name, 0, &io, + enable_bit); + if (IS_ERR(hw)) { + /* + * Clear OF_POPULATED flag so that clock registration can be + * attempted again from probe function. + */ + of_node_clear_flag(node, OF_POPULATED); + return ERR_CAST(hw); + } + + ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw); + if (ret) { + imx_clk_hw_unregister_gate(hw); + return ERR_PTR(ret); + } + + pr_debug("%s: name: %s, parent: %s, offset: 0x%x, enable-bit: %d\n", + __func__, name, parent_name, io.offset, enable_bit); + + return hw; +} + +/** + * of_imx_gate_clk_setup() - Setup function for imx gate clock + * @node: device node for the clock + */ +void __init of_imx_gate_clk_setup(struct device_node *node) +{ + _of_imx_gate_clk_setup(node); +} +CLK_OF_DECLARE(fsl_imx8mn_gate_clk, "fsl,imx8mn-gate-clock", + of_imx_gate_clk_setup); From patchwork Wed Oct 19 17:20:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2451 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f70.google.com (mail-ed1-f70.google.com [209.85.208.70]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id C6BBA3F342 for ; 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[95.233.42.253]) by smtp.gmail.com with ESMTPSA id b27-20020a17090630db00b0073dbaeb50f6sm9237983ejb.169.2022.10.19.10.20.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 10:20:27 -0700 (PDT) From: Dario Binacchi To: linux-amarula@amarulasolutions.com Cc: anthony@amarulasolutions.com, jagan@amarulasolutions.com, dario.binacchi@amarulasolutions.com, michael@amarulasolutions.com, tommaso.merciai@amarulasolutions.com Subject: [RFC PATCH 5/8] clk: imx: add support for imx8mn mux clock Date: Wed, 19 Oct 2022 19:20:16 +0200 Message-Id: <20221019172019.2303223-6-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221019172019.2303223-1-dario.binacchi@amarulasolutions.com> References: <20221019172019.2303223-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="fON5/9dx"; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This patch adds support for freescale imx8mn mux clock. Let's start with this specific clock driver and hope that other variants can be handled in the future as well. Signed-off-by: Dario Binacchi --- drivers/clk/imx/Makefile | 1 + drivers/clk/imx/clk-mux.c | 239 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 240 insertions(+) create mode 100644 drivers/clk/imx/clk-mux.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 539add92be47..ea8c4bed7709 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -14,6 +14,7 @@ mxc-clk-objs += clk-frac-pll.o mxc-clk-objs += clk-gate.o mxc-clk-objs += clk-gate2.o mxc-clk-objs += clk-gate-exclusive.o +mxc-clk-objs += clk-mux.o mxc-clk-objs += clk-pfd.o mxc-clk-objs += clk-pfdv2.o mxc-clk-objs += clk-pllv1.o diff --git a/drivers/clk/imx/clk-mux.c b/drivers/clk/imx/clk-mux.c new file mode 100644 index 000000000000..a54129756318 --- /dev/null +++ b/drivers/clk/imx/clk-mux.c @@ -0,0 +1,239 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Amarula Solutions + * + * Dario Binacchi + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +#define to_clk_imx_mux(_hw) container_of(_hw, struct clk_imx_mux, hw) + +struct clk_imx_mux { + struct clk_hw hw; + struct imx_clk_iomap iomap; + u32 mask; + u8 shift; + u8 saved_parent; +}; + +static u8 imx_clk_mux_get_parent(struct clk_hw *hw) +{ + + struct clk_imx_mux *mux = to_clk_imx_mux(hw); + struct imx_clk_iomap *io = &mux->iomap; + int num_parents = clk_hw_get_num_parents(hw); + unsigned int val; + + if (regmap_read(io->regmap, io->offset, &val)) + return -EIO; + + val = (val >> mux->shift) && mux->mask; + + if (val >= num_parents) + return -EINVAL; + + return val; +} + +static int imx_clk_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct clk_imx_mux *mux = to_clk_imx_mux(hw); + struct imx_clk_iomap *io = &mux->iomap; + unsigned int val; + + if (regmap_read(io->regmap, io->offset, &val)) + return -EIO; + + val &= ~(mux->mask << mux->shift); + val |= index << mux->shift; + return regmap_write(io->regmap, io->offset, val); +} + +/** + * imx_clk_mux_save_context - Save the parent selcted in the mux + * @hw: pointer struct clk_hw + * + * Save the parent mux value. + */ +static int imx_clk_mux_save_context(struct clk_hw *hw) +{ + struct clk_imx_mux *mux = to_clk_imx_mux(hw); + + mux->saved_parent = imx_clk_mux_get_parent(hw); + return 0; +} + +/** + * imx_clk_mux_restore_context - Restore the parent in the mux + * @hw: pointer struct clk_hw + * + * Restore the saved parent mux value. + */ +static void imx_clk_mux_restore_context(struct clk_hw *hw) +{ + struct clk_imx_mux *mux = to_clk_imx_mux(hw); + + imx_clk_mux_set_parent(hw, mux->saved_parent); +} + +const struct clk_ops imx_clk_mux_ops = { + .get_parent = imx_clk_mux_get_parent, + .set_parent = imx_clk_mux_set_parent, + .determine_rate = __clk_mux_determine_rate, + .save_context = imx_clk_mux_save_context, + .restore_context = imx_clk_mux_restore_context, +}; + +static void imx_clk_hw_unregister_mux(struct clk_hw *hw) +{ + struct clk_imx_mux *mux = to_clk_imx_mux(hw); + + clk_hw_unregister(hw); + kfree(mux); +} + +static struct clk_hw *imx_clk_hw_register_mux(struct device *dev, + const char *name, + const char * const *parent_names, + u8 num_parents, + unsigned long flags, + struct imx_clk_iomap *iomap, + u8 shift, u32 mask) +{ + struct clk_init_data init = { NULL }; + struct clk_imx_mux *mux; + struct clk_hw *hw; + + int ret; + + mux = kzalloc(sizeof(*mux), GFP_KERNEL); + if (!mux) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.flags = flags; + init.ops = &imx_clk_mux_ops; + init.parent_names = parent_names; + init.num_parents = 1; + + /* struct clk_mux assignments */ + memcpy(&mux->iomap, iomap, sizeof(*iomap)); + mux->hw.init = &init; + + hw = &mux->hw; + ret = clk_hw_register(dev, hw); + if (ret) { + kfree(mux); + return ERR_PTR(ret); + } + + return hw; +} + +static struct clk_hw *_of_imx_mux_clk_setup(struct device_node *node) +{ + struct clk_hw *hw; + struct device_node *parent_node; + unsigned int num_parents; + const char **parent_names; + const char *name; + struct imx_clk_iomap io; + u32 shift = 0; + u32 flags = CLK_SET_RATE_NO_REPARENT; + u32 val; + u32 mask; + int ret; + + parent_node = of_get_parent(node); + if (!parent_node) { + pr_err("%s: %pOFn must have 1 parent\n", __func__, node); + return ERR_PTR(-ENODEV); + } + + num_parents = of_clk_get_parent_count(node); + if (num_parents < 2) { + pr_err("%s: %pOFn must have parents\n", __func__, node); + return ERR_PTR(-ENODEV); + } + + parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL); + if (!parent_names) + return ERR_PTR(-ENOMEM); + + of_clk_parent_fill(node, parent_names, num_parents); + io.regmap = syscon_node_to_regmap(parent_node); + of_node_put(parent_node); + if (IS_ERR(io.regmap)) { + pr_err("%s: missing regmap for %pOFn\n", __func__, node); + ret = PTR_ERR(io.regmap); + goto free_parent_names; + } + + if (of_property_read_u32(node, "fsl,regmap-offset", &val)) { + pr_err("%s: missing regmap offset for %pOFn\n", __func__, + node); + ret = -EIO; + goto free_parent_names; + } + + io.offset = val; + + of_property_read_u32(node, "fsl,bit-shift", &shift); + + if (of_property_read_bool(node, "fsl,set-rate-parent")) + flags |= CLK_SET_RATE_PARENT; + + if (of_property_read_bool(node, "fsl,ops-parent-enable")) + flags |= CLK_OPS_PARENT_ENABLE; + + /* Generate bit-mask based on parent info */ + mask = num_parents - 1; + mask = (1 << fls(mask)) - 1; + + name = imx_dt_clk_name(node); + hw = imx_clk_hw_register_mux(NULL, name, parent_names, num_parents, + flags, &io, shift, mask); + if (IS_ERR(hw)) { + /* + * Clear OF_POPULATED flag so that clock registration can be + * attempted again from probe function. + */ + of_node_clear_flag(node, OF_POPULATED); + ret = PTR_ERR(hw); + goto free_parent_names; + } + + ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw); + if (ret) { + imx_clk_hw_unregister_mux(hw); + goto free_parent_names; + } + + pr_debug("%s: name: %s, offset: 0x%x, shift: %d, mask: 0x%x, ret: %d\n", + __func__, name, io.offset, shift, mask, ret); + +free_parent_names: + kfree(parent_names); + return ret ? ERR_PTR(ret) : hw; +} + +/** + * of_imx_mux_clk_setup() - Setup function for imx mux clock + * @node: device node for the clock + */ +void __init of_imx_mux_clk_setup(struct device_node *node) +{ + _of_imx_mux_clk_setup(node); +} +CLK_OF_DECLARE(fsl_imx8mn_mux_clk, "fsl,imx8mn-mux-clock", + of_imx_mux_clk_setup); From patchwork Wed Oct 19 17:20:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2452 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f71.google.com (mail-ed1-f71.google.com [209.85.208.71]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 9A18C3F342 for ; Wed, 19 Oct 2022 19:20:30 +0200 (CEST) Received: by mail-ed1-f71.google.com with SMTP id w20-20020a05640234d400b0045d0d1afe8esf12991315edc.15 for ; Wed, 19 Oct 2022 10:20:30 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; 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[95.233.42.253]) by smtp.gmail.com with ESMTPSA id b27-20020a17090630db00b0073dbaeb50f6sm9237983ejb.169.2022.10.19.10.20.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 10:20:28 -0700 (PDT) From: Dario Binacchi To: linux-amarula@amarulasolutions.com Cc: anthony@amarulasolutions.com, jagan@amarulasolutions.com, dario.binacchi@amarulasolutions.com, michael@amarulasolutions.com, tommaso.merciai@amarulasolutions.com Subject: [RFC PATCH 6/8] clk: imx: pll14xx: support driver's registration by device tree Date: Wed, 19 Oct 2022 19:20:17 +0200 Message-Id: <20221019172019.2303223-7-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221019172019.2303223-1-dario.binacchi@amarulasolutions.com> References: <20221019172019.2303223-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=WrySYmte; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The patch, backwards compatible, extends the driver to be able to be registered from the device tree. Signed-off-by: Dario Binacchi --- drivers/clk/imx/clk-pll14xx.c | 242 ++++++++++++++++++++++++++++------ 1 file changed, 200 insertions(+), 42 deletions(-) diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index 1d0f79e9c346..e7404bf5f6f2 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -12,6 +12,10 @@ #include #include #include +#include +#include +#include +#include #include #include @@ -36,7 +40,9 @@ struct clk_pll14xx { struct clk_hw hw; - void __iomem *base; + struct imx_clk_iomap gnrl_ctl; + struct imx_clk_iomap div_ctl0; + struct imx_clk_iomap div_ctl1; enum imx_pll14xx_type type; const struct imx_pll14xx_rate_table *rate_table; int rate_count; @@ -88,6 +94,30 @@ struct imx_pll14xx_clk imx_1416x_pll = { }; EXPORT_SYMBOL_GPL(imx_1416x_pll); +static void imx_pll14xx_writel(u32 val, const struct imx_clk_iomap *reg) +{ + if (reg->mem) + writel_relaxed(val, reg->mem + reg->offset); + else if (reg->regmap) + regmap_write(reg->regmap, reg->offset, val); + else + pr_err("%s: memory address not set\n", __func__); +} + +static u32 imx_pll14xx_readl(const struct imx_clk_iomap *reg) +{ + u32 val = 0; + + if (reg->mem) + val = readl_relaxed(reg->mem + reg->offset); + else if (reg->regmap) + regmap_read(reg->regmap, reg->offset, &val); + else + pr_err("%s: memory address not set\n", __func__); + + return val; +} + static const struct imx_pll14xx_rate_table *imx_get_pll_settings( struct clk_pll14xx *pll, unsigned long rate) { @@ -159,11 +189,11 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat return; } - pll_div_ctl0 = readl_relaxed(pll->base + DIV_CTL0); + pll_div_ctl0 = imx_pll14xx_readl(&pll->div_ctl0); mdiv = FIELD_GET(MDIV_MASK, pll_div_ctl0); pdiv = FIELD_GET(PDIV_MASK, pll_div_ctl0); sdiv = FIELD_GET(SDIV_MASK, pll_div_ctl0); - pll_div_ctl1 = readl_relaxed(pll->base + DIV_CTL1); + pll_div_ctl1 = imx_pll14xx_readl(&pll->div_ctl1); /* Then see if we can get the desired rate by only adjusting kdiv (glitch free) */ rate_min = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, KDIV_MIN, prate); @@ -247,13 +277,13 @@ static unsigned long clk_pll14xx_recalc_rate(struct clk_hw *hw, struct clk_pll14xx *pll = to_clk_pll14xx(hw); u32 mdiv, pdiv, sdiv, kdiv, pll_div_ctl0, pll_div_ctl1; - pll_div_ctl0 = readl_relaxed(pll->base + DIV_CTL0); + pll_div_ctl0 = imx_pll14xx_readl(&pll->div_ctl0); mdiv = FIELD_GET(MDIV_MASK, pll_div_ctl0); pdiv = FIELD_GET(PDIV_MASK, pll_div_ctl0); sdiv = FIELD_GET(SDIV_MASK, pll_div_ctl0); if (pll->type == PLL_1443X) { - pll_div_ctl1 = readl_relaxed(pll->base + DIV_CTL1); + pll_div_ctl1 = imx_pll14xx_readl(&pll->div_ctl1); kdiv = FIELD_GET(KDIV_MASK, pll_div_ctl1); } else { kdiv = 0; @@ -275,10 +305,22 @@ static inline bool clk_pll14xx_mp_change(const struct imx_pll14xx_rate_table *ra static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll) { + struct imx_clk_iomap *reg = &pll->gnrl_ctl; u32 val; - return readl_poll_timeout(pll->base + GNRL_CTL, val, val & LOCK_STATUS, 0, - LOCK_TIMEOUT_US); + if (reg->mem) + return readl_poll_timeout(reg->mem + reg->offset, val, + val & LOCK_STATUS, 0, + LOCK_TIMEOUT_US); + + if (reg->regmap) + return regmap_read_poll_timeout(reg->regmap, reg->offset, val, + val & LOCK_STATUS, 0, + LOCK_TIMEOUT_US); + + pr_err("%s: memory address not set\n", __func__); + + return -EIO; } static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, @@ -296,32 +338,32 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, return -EINVAL; } - tmp = readl_relaxed(pll->base + DIV_CTL0); + tmp = imx_pll14xx_readl(&pll->div_ctl0); if (!clk_pll14xx_mp_change(rate, tmp)) { tmp &= ~SDIV_MASK; tmp |= FIELD_PREP(SDIV_MASK, rate->sdiv); - writel_relaxed(tmp, pll->base + DIV_CTL0); + imx_pll14xx_writel(tmp, &pll->div_ctl0); return 0; } /* Bypass clock and set lock to pll output lock */ - tmp = readl_relaxed(pll->base + GNRL_CTL); + tmp = imx_pll14xx_readl(&pll->gnrl_ctl); tmp |= LOCK_SEL_MASK; - writel_relaxed(tmp, pll->base + GNRL_CTL); + imx_pll14xx_writel(tmp, &pll->gnrl_ctl); /* Enable RST */ tmp &= ~RST_MASK; - writel_relaxed(tmp, pll->base + GNRL_CTL); + imx_pll14xx_writel(tmp, &pll->gnrl_ctl); /* Enable BYPASS */ tmp |= BYPASS_MASK; - writel(tmp, pll->base + GNRL_CTL); + imx_pll14xx_writel(tmp, &pll->gnrl_ctl); div_val = FIELD_PREP(MDIV_MASK, rate->mdiv) | FIELD_PREP(PDIV_MASK, rate->pdiv) | FIELD_PREP(SDIV_MASK, rate->sdiv); - writel_relaxed(div_val, pll->base + DIV_CTL0); + imx_pll14xx_writel(div_val, &pll->div_ctl0); /* * According to SPEC, t3 - t2 need to be greater than @@ -333,7 +375,7 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, /* Disable RST */ tmp |= RST_MASK; - writel_relaxed(tmp, pll->base + GNRL_CTL); + imx_pll14xx_writel(tmp, &pll->gnrl_ctl); /* Wait Lock */ ret = clk_pll14xx_wait_lock(pll); @@ -342,7 +384,7 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, /* Bypass */ tmp &= ~BYPASS_MASK; - writel_relaxed(tmp, pll->base + GNRL_CTL); + imx_pll14xx_writel(tmp, &pll->gnrl_ctl); return 0; } @@ -357,35 +399,35 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, imx_pll14xx_calc_settings(pll, drate, prate, &rate); - div_ctl0 = readl_relaxed(pll->base + DIV_CTL0); + div_ctl0 = imx_pll14xx_readl(&pll->div_ctl0); if (!clk_pll14xx_mp_change(&rate, div_ctl0)) { /* only sdiv and/or kdiv changed - no need to RESET PLL */ div_ctl0 &= ~SDIV_MASK; div_ctl0 |= FIELD_PREP(SDIV_MASK, rate.sdiv); - writel_relaxed(div_ctl0, pll->base + DIV_CTL0); + imx_pll14xx_writel(div_ctl0, &pll->div_ctl0); - writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv), - pll->base + DIV_CTL1); + imx_pll14xx_writel(FIELD_PREP(KDIV_MASK, rate.kdiv), + &pll->div_ctl1); return 0; } /* Enable RST */ - gnrl_ctl = readl_relaxed(pll->base + GNRL_CTL); + gnrl_ctl = imx_pll14xx_readl(&pll->gnrl_ctl); gnrl_ctl &= ~RST_MASK; - writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); + imx_pll14xx_writel(gnrl_ctl, &pll->gnrl_ctl); /* Enable BYPASS */ gnrl_ctl |= BYPASS_MASK; - writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); + imx_pll14xx_writel(gnrl_ctl, &pll->gnrl_ctl); div_ctl0 = FIELD_PREP(MDIV_MASK, rate.mdiv) | FIELD_PREP(PDIV_MASK, rate.pdiv) | FIELD_PREP(SDIV_MASK, rate.sdiv); - writel_relaxed(div_ctl0, pll->base + DIV_CTL0); + imx_pll14xx_writel(div_ctl0, &pll->div_ctl0); - writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv), pll->base + DIV_CTL1); + imx_pll14xx_writel(FIELD_PREP(KDIV_MASK, rate.kdiv), &pll->div_ctl1); /* * According to SPEC, t3 - t2 need to be greater than @@ -397,7 +439,7 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, /* Disable RST */ gnrl_ctl |= RST_MASK; - writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); + imx_pll14xx_writel(gnrl_ctl, &pll->gnrl_ctl); /* Wait Lock*/ ret = clk_pll14xx_wait_lock(pll); @@ -406,7 +448,7 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, /* Bypass */ gnrl_ctl &= ~BYPASS_MASK; - writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); + imx_pll14xx_writel(gnrl_ctl, &pll->gnrl_ctl); return 0; } @@ -421,20 +463,20 @@ static int clk_pll14xx_prepare(struct clk_hw *hw) * RESETB = 1 from 0, PLL starts its normal * operation after lock time */ - val = readl_relaxed(pll->base + GNRL_CTL); + val = imx_pll14xx_readl(&pll->gnrl_ctl); if (val & RST_MASK) return 0; val |= BYPASS_MASK; - writel_relaxed(val, pll->base + GNRL_CTL); + imx_pll14xx_writel(val, &pll->gnrl_ctl); val |= RST_MASK; - writel_relaxed(val, pll->base + GNRL_CTL); + imx_pll14xx_writel(val, &pll->gnrl_ctl); ret = clk_pll14xx_wait_lock(pll); if (ret) return ret; val &= ~BYPASS_MASK; - writel_relaxed(val, pll->base + GNRL_CTL); + imx_pll14xx_writel(val, &pll->gnrl_ctl); return 0; } @@ -444,7 +486,7 @@ static int clk_pll14xx_is_prepared(struct clk_hw *hw) struct clk_pll14xx *pll = to_clk_pll14xx(hw); u32 val; - val = readl_relaxed(pll->base + GNRL_CTL); + val = imx_pll14xx_readl(&pll->gnrl_ctl); return (val & RST_MASK) ? 1 : 0; } @@ -458,9 +500,9 @@ static void clk_pll14xx_unprepare(struct clk_hw *hw) * Set RST to 0, power down mode is enabled and * every digital block is reset */ - val = readl_relaxed(pll->base + GNRL_CTL); + val = imx_pll14xx_readl(&pll->gnrl_ctl); val &= ~RST_MASK; - writel_relaxed(val, pll->base + GNRL_CTL); + imx_pll14xx_writel(val, &pll->gnrl_ctl); } static const struct clk_ops clk_pll1416x_ops = { @@ -485,13 +527,23 @@ static const struct clk_ops clk_pll1443x_ops = { .set_rate = clk_pll1443x_set_rate, }; -struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, - const char *parent_name, void __iomem *base, - const struct imx_pll14xx_clk *pll_clk) +static void imx_clk_hw_unregister_pll14xx(struct clk_hw *hw) { + struct clk_pll14xx *pll = to_clk_pll14xx(hw); + + clk_hw_unregister(hw); + kfree(pll); +} + +static struct clk_hw * +imx_clk_hw_register_pll14xx(struct device *dev, const char *name, + const char *parent_name, + struct imx_clk_iomap *iomap, + const struct imx_pll14xx_clk *pll_clk) +{ + struct clk_init_data init = { NULL }; struct clk_pll14xx *pll; struct clk_hw *hw; - struct clk_init_data init; int ret; u32 val; @@ -520,18 +572,23 @@ struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, return ERR_PTR(-EINVAL); } - pll->base = base; + memcpy(&pll->gnrl_ctl, iomap, sizeof(*iomap)); + pll->gnrl_ctl.offset += GNRL_CTL; + memcpy(&pll->div_ctl0, iomap, sizeof(*iomap)); + pll->div_ctl0.offset += DIV_CTL0; + memcpy(&pll->div_ctl1, iomap, sizeof(*iomap)); + pll->div_ctl1.offset += DIV_CTL1; + pll->hw.init = &init; pll->type = pll_clk->type; pll->rate_table = pll_clk->rate_table; pll->rate_count = pll_clk->rate_count; - val = readl_relaxed(pll->base + GNRL_CTL); + val = imx_pll14xx_readl(&pll->gnrl_ctl); val &= ~BYPASS_MASK; - writel_relaxed(val, pll->base + GNRL_CTL); + imx_pll14xx_writel(val, &pll->gnrl_ctl); hw = &pll->hw; - ret = clk_hw_register(dev, hw); if (ret) { pr_err("failed to register pll %s %d\n", name, ret); @@ -541,4 +598,105 @@ struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, return hw; } + +struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, + const char *parent_name, void __iomem *base, + const struct imx_pll14xx_clk *pll_clk) +{ + struct imx_clk_iomap _base = {}; + + _base.mem = base; + return imx_clk_hw_register_pll14xx(dev, name, parent_name, &_base, + pll_clk); +} EXPORT_SYMBOL_GPL(imx_dev_clk_hw_pll14xx); + +static struct clk_hw *_of_imx_pll14xx_clk_setup(struct device_node *node) +{ + struct clk_hw *hw; + struct imx_clk_iomap io; + struct device_node *parent_node; + const char *name, *parent_name; + const struct imx_pll14xx_clk *pll_clk; + const char *pll_type; + u32 val; + int ret; + + parent_node = of_get_parent(node); + if (!parent_node) { + pr_err("%s: %pOFn must have 1 parent\n", __func__, node); + return ERR_PTR(-ENODEV); + } + + io.mem = 0; + io.regmap = syscon_node_to_regmap(parent_node); + of_node_put(parent_node); + if (IS_ERR(io.regmap)) { + pr_err("%s: missing regmap for %pOFn\n", __func__, node); + return ERR_CAST(io.regmap); + } + + if (of_property_read_u32(node, "fsl,regmap-offset", &val)) { + pr_err("%s: missing regmap offset for %pOFn\n", __func__, + node); + return ERR_PTR(-EIO); + } + + io.offset = val; + if (of_clk_get_parent_count(node) != 1) { + pr_err("%s: %pOFn must have 1 parent clock\n", __func__, node); + return ERR_PTR(-EIO); + } + + parent_name = of_clk_get_parent_name(node, 0); + name = imx_dt_clk_name(node); + if (of_property_read_string(node, "fsl,type", &pll_type)) { + pr_err("%s: missing 'fsl,type' for %pOFn\n", __func__, + node); + return ERR_PTR(-EIO); + } + + if (!strcmp(pll_type, "1443x")) { + if (of_property_read_bool(node, "fsl,get-rate-nocache")) + pll_clk = &imx_1443x_dram_pll; + else + pll_clk = &imx_1443x_pll; + } else if (!strcmp(pll_type, "1416x")) { + pll_clk = &imx_1416x_pll; + } else { + pr_err("%s: failed to get pll clock for %pOFn\n", __func__, + node); + return ERR_PTR(-EIO); + } + + hw = imx_clk_hw_register_pll14xx(NULL, name, parent_name, &io, pll_clk); + if (IS_ERR(hw)) { + /* + * Clear OF_POPULATED flag so that clock registration can be + * attempted again from probe function. + */ + of_node_clear_flag(node, OF_POPULATED); + return ERR_CAST(hw); + } + + ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw); + if (ret) { + imx_clk_hw_unregister_pll14xx(hw); + return ERR_PTR(ret); + } + + pr_debug("%s: name: %s, parent: %s, offset: 0x%x, pll_type: %s\n", + __func__, name, parent_name, io.offset, pll_type); + + return hw; +} + +/** + * of_imx_pll14xx_clk_setup() - Setup function for imx pll14xx clock + * @node: device node for the clock + */ +void __init of_imx_pll14xx_clk_setup(struct device_node *node) +{ + _of_imx_pll14xx_clk_setup(node); +} +CLK_OF_DECLARE(fsl_pll14xx_clk, "fsl,pll14xx-clock", of_imx_pll14xx_clk_setup); From patchwork Wed Oct 19 17:20:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2453 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ej1-f71.google.com (mail-ej1-f71.google.com [209.85.218.71]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 6761C3F342 for ; Wed, 19 Oct 2022 19:20:31 +0200 (CEST) Received: by mail-ej1-f71.google.com with SMTP id ho8-20020a1709070e8800b0078db5e53032sf8405657ejc.9 for ; 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[95.233.42.253]) by smtp.gmail.com with ESMTPSA id b27-20020a17090630db00b0073dbaeb50f6sm9237983ejb.169.2022.10.19.10.20.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 10:20:29 -0700 (PDT) From: Dario Binacchi To: linux-amarula@amarulasolutions.com Cc: anthony@amarulasolutions.com, jagan@amarulasolutions.com, dario.binacchi@amarulasolutions.com, michael@amarulasolutions.com, tommaso.merciai@amarulasolutions.com Subject: [RFC PATCH 7/8] arm64: dts: imx8mn: add dumy clock Date: Wed, 19 Oct 2022 19:20:18 +0200 Message-Id: <20221019172019.2303223-8-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221019172019.2303223-1-dario.binacchi@amarulasolutions.com> References: <20221019172019.2303223-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=Usdz+ulR; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Signed-off-by: Dario Binacchi --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 11 +++++++++-- drivers/clk/imx/clk-imx8mn.c | 2 +- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 5c0ca2490561..089fa3c4a526 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -216,6 +216,13 @@ clk_ext4: clock-ext4 { clock-output-names = "clk_ext4"; }; + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "dummy"; + }; + pmu { compatible = "arm,cortex-a53-pmu"; interrupts = ; #clock-cells = <1>; clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; + <&clk_ext3>, <&clk_ext4>, <&clk_dummy>; clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; + "clk_ext3", "clk_ext4", "dummy"; assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>, <&clk IMX8MN_CLK_A53_CORE>, <&clk IMX8MN_CLK_NOC>, diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index 92fcbab4f5be..6bee953a60ed 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -307,7 +307,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) clk_hw_data->num = IMX8MN_CLK_END; hws = clk_hw_data->hws; - hws[IMX8MN_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); + hws[IMX8MN_CLK_DUMMY] = imx_obtain_fixed_clk_hw(np, "dummy"); hws[IMX8MN_CLK_24M] = imx_obtain_fixed_clk_hw(np, "osc_24m"); hws[IMX8MN_CLK_32K] = imx_obtain_fixed_clk_hw(np, "osc_32k"); hws[IMX8MN_CLK_EXT1] = imx_obtain_fixed_clk_hw(np, "clk_ext1"); From patchwork Wed Oct 19 17:20:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2454 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f69.google.com (mail-ed1-f69.google.com [209.85.208.69]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 299333F342 for ; Wed, 19 Oct 2022 19:20:33 +0200 (CEST) Received: by mail-ed1-f69.google.com with SMTP id b8-20020a056402278800b0045d410dec69sf10381446ede.2 for ; Wed, 19 Oct 2022 10:20:33 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1666200033; cv=pass; d=google.com; s=arc-20160816; b=ih/EeRIicx+5bAEAGIHDWaxMSDDmF9wENz1Sa9rRhDQGhcsCDdBMAO4eL4vW4brNTg mFs2Li2dXVSKhDefC35yTYeswQS19xnC8Fykom9Hb7v8P6JpwPOa97m7tx8+/K/IU0mS Sby4N0Db7QiwmhgBJ5seaWZ8H8T3/EDNAufaL26M/16F57cj7kwYbbxvE3bNHwH6kgNf c/PUqyaFTX7Nh9uz5WbLlV1crXqUyTQnLuZ2sIhfENDHVm20QxSdKKRS/h8k7m+oru6W F0soIsa/TJCTXVHKX1HP64Li4V/lRwloy1y1MSIC6Tnw0lUmakPe+bDc7z4FXm8kmg8A J2QA== ARC-Message-Signature: i=2; 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[95.233.42.253]) by smtp.gmail.com with ESMTPSA id b27-20020a17090630db00b0073dbaeb50f6sm9237983ejb.169.2022.10.19.10.20.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 10:20:30 -0700 (PDT) From: Dario Binacchi To: linux-amarula@amarulasolutions.com Cc: anthony@amarulasolutions.com, jagan@amarulasolutions.com, dario.binacchi@amarulasolutions.com, michael@amarulasolutions.com, tommaso.merciai@amarulasolutions.com Subject: [RFC PATCH 8/8] arm64: dts: imx8mn: add imx8mn-clocks.dtsi Date: Wed, 19 Oct 2022 19:20:19 +0200 Message-Id: <20221019172019.2303223-9-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221019172019.2303223-1-dario.binacchi@amarulasolutions.com> References: <20221019172019.2303223-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=CIJlM2DD; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Signed-off-by: Dario Binacchi --- .../boot/dts/freescale/imx8mn-clocks.dtsi | 581 ++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8mn.dtsi | 51 +- drivers/clk/imx/clk-imx8mn.c | 126 ++-- 3 files changed, 641 insertions(+), 117 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-clocks.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8mn-clocks.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-clocks.dtsi new file mode 100644 index 000000000000..70ca66f24325 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-clocks.dtsi @@ -0,0 +1,581 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for imx8mn clock data + * + * Copyright (c) 2022 Amarula Solutions + * + * Dario Binacchi + */ + +/ { + osc_32k: clock-osc-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "osc_32k"; + }; + + osc_24m: clock-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + clk_ext1: clock-ext1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext1"; + }; + + clk_ext2: clock-ext2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext2"; + }; + + clk_ext3: clock-ext3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext3"; + }; + + clk_ext4: clock-ext4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency= <133000000>; + clock-output-names = "clk_ext4"; + }; + + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "dummy"; + }; +}; + +&anatop { + clk_sys_pll1: clock-sys-pll1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + clock-output-names = "sys_pll1"; + }; + + clk_sys_pll2: clock-sys-pll2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000000>; + clock-output-names = "sys_pll2"; + }; + + clk_sys_pll1_40m: clock-sys-pll1-40m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll1_out>; + clock-mult = <1>; + clock-div = <20>; + clock-output-names = "sys_pll1_40m"; + }; + + clk_sys_pll1_80m: clock-sys-pll1-80m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll1_out>; + clock-mult = <1>; + clock-div = <10>; + clock-output-names = "sys_pll1_80m"; + }; + + clk_sys_pll1_100m: clock-sys-pll1-100m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll1_out>; + clock-mult = <1>; + clock-div = <8>; + clock-output-names = "sys_pll1_100m"; + }; + + clk_sys_pll1_133m: clock-sys-pll1-133m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll1_out>; + clock-mult = <1>; + clock-div = <6>; + clock-output-names = "sys_pll1_133m"; + }; + + clk_sys_pll1_160m: clock-sys-pll1-160m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll1_out>; + clock-mult = <1>; + clock-div = <5>; + }; + + clk_sys_pll1_200m: clock-sys-pll1-200m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll1_out>; + clock-mult = <1>; + clock-div = <4>; + clock-output-names = "sys_pll1_200m"; + }; + + clk_sys_pll1_266m: clock-sys-pll1-266m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll1_out>; + clock-mult = <1>; + clock-div = <3>; + clock-output-names = "sys_pll1_266m"; + }; + + clk_sys_pll1_400m: clock-sys-pll1-400m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll1_out>; + clock-mult = <1>; + clock-div = <2>; + clock-output-names = "sys_pll1_400m"; + }; + + clk_sys_pll1_800m: clock-sys-pll1-800m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll1_out>; + clock-mult = <1>; + clock-div = <1>; + clock-output-names = "sys_pll1_800m"; + }; + + clk_sys_pll2_out: clock-sys-pll2-out@104 { + compatible = "fsl,imx8mn-gate-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll2>; + fsl,regmap-offset = <0x104>; + fsl,bit-shift = <11>; + clock-output-names = "sys_pll2_out"; + }; + + clk_sys_pll2_50m: clock-sys-pll2-50m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll2_out>; + clock-mult = <1>; + clock-div = <20>; + clock-output-names = "sys_pll2_50m"; + }; + + clk_sys_pll2_100m: clock-sys-pll2-100m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll2_out>; + clock-mult = <1>; + clock-div = <10>; + clock-output-names = "sys_pll2_100m"; + }; + + clk_sys_pll2_125m: clock-sys-pll2-125m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll2_out>; + clock-mult = <1>; + clock-div = <8>; + clock-output-names = "sys_pll2_125m"; + }; + + clk_sys_pll2_166m: clock-sys-pll2-166m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll2_out>; + clock-mult = <1>; + clock-div = <6>; + clock-output-names = "sys_pll2_166m"; + }; + + clk_sys_pll2_200m: clock-sys-pll2-200m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll2_out>; + clock-mult = <1>; + clock-div = <5>; + clock-output-names = "sys_pll2_200m"; + }; + + clk_sys_pll2_250m: clock-sys-pll2-250m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll2_out>; + clock-mult = <1>; + clock-div = <4>; + clock-output-names = "sys_pll2_250m"; + }; + + clk_sys_pll2_333m: clock-sys-pll2-333m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll2_out>; + clock-mult = <1>; + clock-div = <3>; + clock-output-names = "sys_pll2_333m"; + }; + + clk_sys_pll2_500m: clock-sys-pll2-500m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll2_out>; + clock-mult = <1>; + clock-div = <2>; + clock-output-names = "sys_pll2_500m"; + }; + + clk_sys_pll2_1000m: clock-sys-pll2-1000m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll2_out>; + clock-mult = <1>; + clock-div = <1>; + clock-output-names = "sys_pll2_1000m"; + }; + + clk_audio_pll1_ref_sel: clock-audio-pll1-ref-sel@0 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&osc_24m>, <&clk_dummy>, <&clk_dummy>, <&clk_dummy>; + fsl,regmap-offset = <0x0>; + fsl,bit-shift = <0>; + clock-output-names = "audio_pll1_ref_sel"; + }; + + clk_audio_pll1: clock-audio-pll1@0 { + compatible = "fsl,pll14xx-clock"; + #clock-cells = <0>; + clocks = <&clk_audio_pll1_ref_sel>; + fsl,regmap-offset = <0x0>; + fsl,type = "1443x"; + clock-output-names = "audio_pll1"; + }; + + clk_audio_pll1_bypass: clock-audio-pll1-bypass@0 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&clk_audio_pll1>, <&clk_audio_pll1_ref_sel>; + fsl,regmap-offset = <0x0>; + fsl,bit-shift = <16>; + fsl,set-rate-parent; + clock-output-names = "audio_pll1_bypass"; + }; + + clk_audio_pll1_out: clock-audio-pll1-out@0 { + compatible = "fsl,imx8mn-gate-clock"; + #clock-cells = <0>; + clocks = <&clk_audio_pll1_bypass>; + fsl,regmap-offset = <0x0>; + fsl,bit-shift = <13>; + clock-output-names = "audio_pll1_out"; + }; + + clk_audio_pll2_ref_sel: clock-audio-pll2-ref-sel@14 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&osc_24m>, <&clk_dummy>, <&clk_dummy>, <&clk_dummy>; + fsl,regmap-offset = <0x14>; + fsl,bit-shift = <0>; + clock-output-names = "audio_pll2_ref_sel"; + }; + + clk_audio_pll2: clock-audio-pll2@14 { + compatible = "fsl,pll14xx-clock"; + #clock-cells = <0>; + clocks = <&clk_audio_pll2_ref_sel>; + fsl,regmap-offset = <0x14>; + fsl,type = "1443x"; + clock-output-names = "audio_pll2"; + }; + + clk_audio_pll2_bypass: clock-audio-pll2-bypass@14 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&clk_audio_pll2>, <&clk_audio_pll2_ref_sel>; + fsl,regmap-offset = <0x14>; + fsl,bit-shift = <16>; + fsl,set-rate-parent; + clock-output-names = "audio_pll2_bypass"; + }; + + clk_audio_pll2_out: clock-audio-pll2-out@14 { + compatible = "fsl,imx8mn-gate-clock"; + #clock-cells = <0>; + clocks = <&clk_audio_pll2_bypass>; + fsl,regmap-offset = <0x14>; + fsl,bit-shift = <13>; + clock-output-names = "audio_pll2_out"; + }; + + clk_video_pll1_ref_sel: clock-video-pll1-ref-sel@28 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&osc_24m>, <&clk_dummy>, <&clk_dummy>, <&clk_dummy>; + fsl,regmap-offset = <0x28>; + fsl,bit-shift = <0>; + clock-output-names = "video_pll1_ref_sel"; + }; + + clk_video_pll1: clock-video-pll1@28 { + compatible = "fsl,pll14xx-clock"; + #clock-cells = <0>; + clocks = <&clk_video_pll1_ref_sel>; + fsl,regmap-offset = <0x28>; + fsl,type = "1443x"; + clock-output-names = "video_pll1"; + }; + + clk_video_pll1_bypass: clock-video-pll1-bypass@28 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&clk_video_pll1>, <&clk_video_pll1_ref_sel>; + fsl,regmap-offset = <0x28>; + fsl,bit-shift = <16>; + fsl,set-rate-parent; + clock-output-names = "video_pll1_bypass"; + }; + + clk_video_pll1_out: clock-video-pll1-out@28 { + compatible = "fsl,imx8mn-gate-clock"; + #clock-cells = <0>; + clocks = <&clk_video_pll1_bypass>; + fsl,regmap-offset = <0x28>; + fsl,bit-shift = <13>; + clock-output-names = "video_pll1_out"; + }; + + clk_dram_pll_ref_sel: clock-dram-pll-ref-sel@50 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&osc_24m>, <&clk_dummy>, <&clk_dummy>, <&clk_dummy>; + fsl,regmap-offset = <0x50>; + fsl,bit-shift = <0>; + clock-output-names = "dram_pll_ref_sel"; + }; + + clk_dram_pll: clock-dram-pll@50 { + compatible = "fsl,pll14xx-clock"; + #clock-cells = <0>; + clocks = <&clk_dram_pll_ref_sel>; + fsl,regmap-offset = <0x50>; + fsl,get-rate-nocache; + fsl,type = "1443x"; + clock-output-names = "dram_pll"; + }; + + clk_dram_pll_bypass: clock-dram-pll-bypass@50 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&clk_dram_pll>, <&clk_dram_pll_ref_sel>; + fsl,regmap-offset = <0x50>; + fsl,bit-shift = <16>; + fsl,set-rate-parent; + clock-output-names = "dram_pll_bypass"; + }; + + clk_dram_pll_out: clock-dram-pll-out@50 { + compatible = "fsl,imx8mn-gate-clock"; + #clock-cells = <0>; + clocks = <&clk_dram_pll_bypass>; + fsl,regmap-offset = <0x50>; + fsl,bit-shift = <13>; + clock-output-names = "dram_pll_out"; + }; + + clk_gpu_pll_ref_sel: clock-gpu-pll-ref-sel@64 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&osc_24m>, <&clk_dummy>, <&clk_dummy>, <&clk_dummy>; + fsl,regmap-offset = <0x64>; + fsl,bit-shift = <0>; + clock-output-names = "gpu_pll_ref_sel"; + }; + + clk_gpu_pll: clock-gpu-pll@64 { + compatible = "fsl,pll14xx-clock"; + #clock-cells = <0>; + clocks = <&clk_gpu_pll_ref_sel>; + fsl,regmap-offset = <0x64>; + fsl,type = "1416x"; + clock-output-names = "gpu_pll"; + }; + + clk_gpu_pll_bypass: clock-gpu-pll-bypass@64 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&clk_gpu_pll>, <&clk_gpu_pll_ref_sel>; + fsl,regmap-offset = <0x64>; + fsl,bit-shift = <28>; + fsl,set-rate-parent; + clock-output-names = "gpu_pll_bypass"; + }; + + clk_gpu_pll_out: clock-gpu-pll-out@64 { + compatible = "fsl,imx8mn-gate-clock"; + #clock-cells = <0>; + clocks = <&clk_gpu_pll_bypass>; + fsl,regmap-offset = <0x64>; + fsl,bit-shift = <11>; + clock-output-names = "gpu_pll_out"; + }; + + clk_vpu_pll_ref_sel: clock-vpu-pll-ref-sel@74 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&osc_24m>, <&clk_dummy>, <&clk_dummy>, <&clk_dummy>; + fsl,regmap-offset = <0x74>; + fsl,bit-shift = <0>; + clock-output-names = "vpu_pll_ref_sel"; + }; + + clk_vpu_pll: clock-vpu-pll@74 { + compatible = "fsl,pll14xx-clock"; + #clock-cells = <0>; + clocks = <&clk_vpu_pll_ref_sel>; + fsl,regmap-offset = <0x74>; + fsl,type = "1416x"; + clock-output-names = "vpu_pll"; + }; + + clk_vpu_pll_bypass: clock-vpu-pll-bypass@74 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&clk_vpu_pll>, <&clk_vpu_pll_ref_sel>; + fsl,regmap-offset = <0x74>; + fsl,bit-shift = <28>; + fsl,set-rate-parent; + clock-output-names = "vpu_pll_bypass"; + }; + + clk_vpu_pll_out: clock-vpu-pll-out@74 { + compatible = "fsl,imx8mn-gate-clock"; + #clock-cells = <0>; + clocks = <&clk_vpu_pll_bypass>; + fsl,regmap-offset = <0x74>; + fsl,bit-shift = <11>; + clock-output-names = "vpu_pll_out"; + }; + + clk_arm_pll_ref_sel: clock-arm-pll-ref-sel@84 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&osc_24m>, <&clk_dummy>, <&clk_dummy>, <&clk_dummy>; + fsl,regmap-offset = <0x84>; + fsl,bit-shift = <0>; + clock-output-names = "arm_pll_ref_sel"; + }; + + clk_arm_pll: clock-arm-pll@84 { + compatible = "fsl,pll14xx-clock"; + #clock-cells = <0>; + clocks = <&clk_arm_pll_ref_sel>; + fsl,regmap-offset = <0x84>; + fsl,type = "1416x"; + clock-output-names = "arm_pll"; + }; + + clk_arm_pll_bypass: clock-arm-pll-bypass@84 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&clk_arm_pll>, <&clk_arm_pll_ref_sel>; + fsl,regmap-offset = <0x84>; + fsl,bit-shift = <28>; + fsl,set-rate-parent; + clock-output-names = "arm_pll_bypass"; + }; + + clk_arm_pll_out: clock-arm-pll-out@84 { + compatible = "fsl,imx8mn-gate-clock"; + #clock-cells = <0>; + clocks = <&clk_arm_pll_bypass>; + fsl,regmap-offset = <0x84>; + fsl,bit-shift = <11>; + clock-output-names = "arm_pll_out"; + }; + + clk_sys_pll1_out: clock-sys-pll1-out@94 { + compatible = "fsl,imx8mn-gate-clock"; + clocks = <&clk_sys_pll1>; + fsl,regmap-offset = <0x094>; + fsl,bit-shift = <11>; + clock-output-names = "sys_pll1_out"; + #clock-cells = <0>; + }; + + clk_sys_pll3_ref_sel: clock-sys-pll3-ref-sel@114 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&osc_24m>, <&clk_dummy>, <&clk_dummy>, <&clk_dummy>; + fsl,regmap-offset = <0x114>; + fsl,bit-shift = <0>; + clock-output-names = "sys_pll3_ref_sel"; + }; + + clk_sys_pll3: clock-sys-pll3@114 { + compatible = "fsl,pll14xx-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll3_ref_sel>; + fsl,regmap-offset = <0x114>; + fsl,type = "1416x"; + clock-output-names = "sys_pll3"; + }; + + clk_sys_pll3_bypass: clock-sys-pll3-bypass@114 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll3>, <&clk_sys_pll3_ref_sel>; + fsl,regmap-offset = <0x114>; + fsl,bit-shift = <28>; + fsl,set-rate-parent; + clock-output-names = "sys_pll3_bypass"; + }; + + clk_sys_pll3_out: clock-sys-pll3-out@114 { + compatible = "fsl,imx8mn-gate-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll3_bypass>; + fsl,regmap-offset = <0x114>; + fsl,bit-shift = <11>; + clock-output-names = "sys_pll3_out"; + }; + + clk_out1_sel: clock-out1-sel@128 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&clk_audio_pll1_out>, <&clk_audio_pll2_out>, + <&clk_video_pll1_out>, <&clk_dummy>, <&clk_dummy>, + <&clk_gpu_pll_out>, <&clk_dummy>, <&clk_arm_pll_out>, + <&clk_sys_pll1>, <&clk_sys_pll2>, <&clk_sys_pll3>, + <&clk_dummy>, <&clk_dummy>, <&osc_24m>, <&clk_dummy>, + <&osc_32k>; + fsl,regmap-offset = <0x128>; + fsl,bit-shift = <4>; + fsl,ops-parent-enable; + clock-output-names = "clkout1_sel"; + }; + + clk_out2_sel: clock-out2-sel@128 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&clk_audio_pll1_out>, <&clk_audio_pll2_out>, + <&clk_video_pll1_out>, <&clk_dummy>, <&clk_dummy>, + <&clk_gpu_pll_out>, <&clk_dummy>, <&clk_arm_pll_out>, + <&clk_sys_pll1>, <&clk_sys_pll2>, <&clk_sys_pll3>, + <&clk_dummy>, <&clk_dummy>, <&osc_24m>, <&clk_dummy>, + <&osc_32k>; + fsl,regmap-offset = <0x128>; + fsl,bit-shift = <20>; + fsl,ops-parent-enable; + clock-output-names = "clkout2_sel"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 089fa3c4a526..ab3fed912528 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -174,55 +174,6 @@ opp-1500000000 { }; }; - osc_32k: clock-osc-32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "osc_32k"; - }; - - osc_24m: clock-osc-24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc_24m"; - }; - - clk_ext1: clock-ext1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext1"; - }; - - clk_ext2: clock-ext2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext2"; - }; - - clk_ext3: clock-ext3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext3"; - }; - - clk_ext4: clock-ext4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency= <133000000>; - clock-output-names = "clk_ext4"; - }; - - clk_dummy: clock-dummy { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "dummy"; - }; - pmu { compatible = "arm,cortex-a53-pmu"; interrupts =