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[79.25.102.201]) by smtp.gmail.com with ESMTPSA id s4-20020a1709062ec400b0087da4172178sm2018401eji.44.2023.01.28.08.04.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 28 Jan 2023 08:04:08 -0800 (PST) From: Dario Binacchi To: u-boot@lists.denx.de Cc: Dario Binacchi , Michael Trimarchi , Adam Ford , Fabio Estevam , "NXP i.MX U-Boot Team" , Stefano Babic , Tom Rini , linux-amarula@amarulasolutions.com Subject: [RESEND PATCH v2] arm: dts: imx8mn-u-boot: fix DDR3 only support Date: Sat, 28 Jan 2023 17:04:04 +0100 Message-Id: <20230128160405.62324-1-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=nEIEAlyf; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , In case the CONFIG_IMX8M_LPDDR4 and CONFIG_IMX8M_DDR4 options are both disabled (i. e. BSH boards), binmain fails because DDR4 bin files are missing. Fixes: 93c4c0e4dd1e75 ("arm: dts: imx8mn-u-boot: Create common imx8mn-u-boot.dtsi") Signed-off-by: Dario Binacchi Reviewed-by: Michael Trimarchi Reviewed-by: Fabio Estevam --- Changes in v2: - Fix typos in the commit message (DD3 --> DDR3, DD4 --> DDR4) arch/arm/dts/imx8mn-u-boot.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/imx8mn-u-boot.dtsi b/arch/arm/dts/imx8mn-u-boot.dtsi index 95f45ad2522d..ec53390afb30 100644 --- a/arch/arm/dts/imx8mn-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-u-boot.dtsi @@ -105,10 +105,11 @@ align-end = <4>; }; +#if defined(CONFIG_IMX8M_LPDDR4) || defined(CONFIG_IMX8M_DDR4) ddr-2d-imem-fw { #ifdef CONFIG_IMX8M_LPDDR4 filename = "lpddr4_pmu_train_2d_imem.bin"; -#elif CONFIG_IMX8M_DDR4 +#else filename = "ddr4_imem_2d.bin"; #endif type = "blob-ext"; @@ -118,12 +119,13 @@ ddr-2d-dmem-fw { #ifdef CONFIG_IMX8M_LPDDR4 filename = "lpddr4_pmu_train_2d_dmem.bin"; -#elif CONFIG_IMX8M_DDR4 +#else filename = "ddr4_dmem_2d.bin"; #endif type = "blob-ext"; align-end = <4>; }; +#endif }; spl {