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[209.85.220.41]) by mx.google.com with SMTPS id 188-20020a6214c5000000b005826e2da293sor874921pfu.66.2023.02.09.06.31.20 for (Google Transport Security); Thu, 09 Feb 2023 06:31:20 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a62:5f43:0:b0:593:91e4:99e2 with SMTP id t64-20020a625f43000000b0059391e499e2mr9249144pfb.34.1675953080011; Thu, 09 Feb 2023 06:31:20 -0800 (PST) Received: from localhost.localdomain ([183.83.141.79]) by smtp.gmail.com with ESMTPSA id j7-20020aa783c7000000b005938bd2bfd3sm1501226pfn.120.2023.02.09.06.31.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Feb 2023 06:31:19 -0800 (PST) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v3 1/7] dt-bindings: rockchip: Sync rockchip, vop2.h from Linux Date: Thu, 9 Feb 2023 20:00:54 +0530 Message-Id: <20230209143100.113376-1-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=HAzkyWyC; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Sync rockchip,vop2.h from linux-next, and the last commit is commit <604be85547ce> ("drm/rockchip: Add VOP2 driver") Reviewed-by: Kever Yang Signed-off-by: Jagan Teki --- Changes for v3: - none Changes for v2: - collect Kever RB include/dt-bindings/soc/rockchip,vop2.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 include/dt-bindings/soc/rockchip,vop2.h diff --git a/include/dt-bindings/soc/rockchip,vop2.h b/include/dt-bindings/soc/rockchip,vop2.h new file mode 100644 index 0000000000..6e66a802b9 --- /dev/null +++ b/include/dt-bindings/soc/rockchip,vop2.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ + +#ifndef __DT_BINDINGS_ROCKCHIP_VOP2_H +#define __DT_BINDINGS_ROCKCHIP_VOP2_H + +#define ROCKCHIP_VOP2_EP_RGB0 1 +#define ROCKCHIP_VOP2_EP_HDMI0 2 +#define ROCKCHIP_VOP2_EP_EDP0 3 +#define ROCKCHIP_VOP2_EP_MIPI0 4 +#define ROCKCHIP_VOP2_EP_LVDS0 5 +#define ROCKCHIP_VOP2_EP_MIPI1 6 +#define ROCKCHIP_VOP2_EP_LVDS1 7 + +#endif /* __DT_BINDINGS_ROCKCHIP_VOP2_H */ From patchwork Thu Feb 9 14:30:55 2023 Content-Type: text/plain; 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[209.85.220.41]) by mx.google.com with SMTPS id 75-20020a62164e000000b005a846f49e73sor909804pfw.52.2023.02.09.06.31.52 for (Google Transport Security); Thu, 09 Feb 2023 06:31:52 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a62:6182:0:b0:5a8:5d89:3ae6 with SMTP id v124-20020a626182000000b005a85d893ae6mr1783214pfb.20.1675953112494; Thu, 09 Feb 2023 06:31:52 -0800 (PST) Received: from localhost.localdomain ([183.83.141.79]) by smtp.gmail.com with ESMTPSA id j7-20020aa783c7000000b005938bd2bfd3sm1501226pfn.120.2023.02.09.06.31.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Feb 2023 06:31:51 -0800 (PST) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com, Jagan Teki , FUKAUMI Naoki Subject: [PATCH v3 2/7] arm64: dts: rockchip: rk3566: Add Radxa Compute Module 3 Date: Thu, 9 Feb 2023 20:00:55 +0530 Message-Id: <20230209143100.113376-2-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230209143100.113376-1-jagan@amarulasolutions.com> References: <20230209143100.113376-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="pvOhe/bh"; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Radxa Compute Module 3(CM3) is one of the modules from a series System On Module based on the Radxa ROCK 3 series and is compatible with Raspberry Pi CM4 pinout and form factor. Specification: - Rockchip RK3566 - up to 8GB LPDDR4 - up to 128GB high performance eMMC - Optional wireless LAN, 2.4GHz and 5.0GHz IEEE 802.11b/g/n/ac wireless, BT 5.0, BLE with onboard and external antenna. - Gigabit Ethernet PHY Radxa CM3 needs to mount on top of this IO board in order to create complete Radxa CM3 IO board platform. Since Radxa CM3 is compatible with Raspberry Pi CM4 pinout so it is possible to mount Radxa CM3 on top of the Rasberry Pi CM4 IO board. linux-next commit for the same, commit <8f19828844f2> ("arm64: dts: rockchip: Fix compatible for Radxa CM3") Add support for Radxa CM3. Reviewed-by: Kever Yang Co-developed-by: FUKAUMI Naoki Signed-off-by: FUKAUMI Naoki Signed-off-by: Jagan Teki --- Changes for v3: - updated linux-next commit Changes for v2: - collect Kever RB - add linux-next commit arch/arm/dts/rk3566-radxa-cm3.dtsi | 425 +++++++++++++++++++++++++++++ 1 file changed, 425 insertions(+) create mode 100644 arch/arm/dts/rk3566-radxa-cm3.dtsi diff --git a/arch/arm/dts/rk3566-radxa-cm3.dtsi b/arch/arm/dts/rk3566-radxa-cm3.dtsi new file mode 100644 index 0000000000..45de2630bb --- /dev/null +++ b/arch/arm/dts/rk3566-radxa-cm3.dtsi @@ -0,0 +1,425 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Radxa Limited + * Copyright (c) 2022 Amarula Solutions(India) + */ + +#include +#include + +/ { + compatible = "radxa,cm3", "rockchip,rk3566"; + + aliases { + mmc0 = &sdhci; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_STATUS; + linux,default-trigger = "timer"; + default-state = "on"; + pinctrl-names = "default"; + pinctrl-0 = <&user_led2>; + }; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_1v8: vcc-1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_p>; + }; + + vcc_3v3: vcc-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcca_1v8: vcca-1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_p>; + }; + + sdio_pwrseq: pwrseq-sdio { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h>; + reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gpu { + mali-supply = <&vdd_gpu_npu>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + #clock-cells = <1>; + clock-output-names = "rk817-clkout1", "rk817-clkout2"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_gpu_npu: DCDC_REG2 { + regulator-name = "vdd_gpu_npu"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG4 { + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca1v8_pmu: LDO_REG1 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v8_p: LDO_REG7 { + regulator-name = "vcc_1v8_p"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-name = "vcc1v8_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG9 { + regulator-name = "vcc2v8_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + }; + }; +}; + +&pinctrl { + bluetooth { + bt_host_wake_h: bt-host-wake-h { + rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reg_on_h: bt-reg-on-h { + rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host_h: bt-wake-host-h { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + user_led2: user-led2 { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_reg_on_h: wifi-reg-on-h { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_host_wake_h: wifi-host-wake-h { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc_3v3>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdmmc1 { + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm43455-fmac"; + reg = <1>; + interrupt-parent = <&gpio2>; + interrupts = ; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_h>; + }; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_ctsn &uart1m0_rtsn &uart1m0_xfer>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&rk817 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_h &bt_reg_on_h &bt_wake_host_h>; + vbat-supply = <&vcc_3v3>; + vddio-supply = <&vcc_1v8>; + }; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; From patchwork Thu Feb 9 14:30:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 2707 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pl1-f197.google.com (mail-pl1-f197.google.com [209.85.214.197]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 97FF93F046 for ; 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[209.85.220.41]) by mx.google.com with SMTPS id x2-20020a056a000bc200b00580e6a35dd5sor864201pfu.70.2023.02.09.06.31.56 for (Google Transport Security); Thu, 09 Feb 2023 06:31:56 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:aa7:943b:0:b0:5a7:6568:2a09 with SMTP id y27-20020aa7943b000000b005a765682a09mr9268360pfo.2.1675953115884; Thu, 09 Feb 2023 06:31:55 -0800 (PST) Received: from localhost.localdomain ([183.83.141.79]) by smtp.gmail.com with ESMTPSA id j7-20020aa783c7000000b005938bd2bfd3sm1501226pfn.120.2023.02.09.06.31.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Feb 2023 06:31:55 -0800 (PST) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com, Jagan Teki , FUKAUMI Naoki , Manoj Sai Subject: [PATCH v3 3/7] arm64: dts: rockchip: rk3566: Add Radxa Compute Module 3 IO Date: Thu, 9 Feb 2023 20:00:56 +0530 Message-Id: <20230209143100.113376-3-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230209143100.113376-1-jagan@amarulasolutions.com> References: <20230209143100.113376-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=psgyvUX4; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Radxa Compute Module 3(CM3) IO board an application board from Radxa and is compatible with Raspberry Pi CM4 IO form factor. Specification: - 1x HDMI, - 2x MIPI DSI - 2x MIPI CSI2 - 1x eDP - 1x PCIe card - 2x SATA - 2x USB 2.0 Host - 1x USB 3.0 - 1x USB 2.0 OTG - Phone jack - microSD slot - 40-pin GPIO expansion header - 12V DC Radxa CM3 needs to mount on top of this IO board in order to create complete Radxa CM3 IO board platform. linux-next commit for the same, commit <8f19828844f2> ("arm64: dts: rockchip: Fix compatible for Radxa CM3") Add support for Radxa CM3 IO Board. Co-developed-by: FUKAUMI Naoki Signed-off-by: FUKAUMI Naoki Co-developed-by: Manoj Sai Signed-off-by: Manoj Sai Signed-off-by: Jagan Teki --- Changes for v3: - updated linux-next commit Changes for v2: - collect Kever RB - add linux-next commit arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3566-radxa-cm3-io.dts | 272 +++++++++++++++++++++++++++ 2 files changed, 273 insertions(+) create mode 100644 arch/arm/dts/rk3566-radxa-cm3-io.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d9b719f85d..8d45050c2a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -165,6 +165,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399pro-rock-pi-n10.dtb dtb-$(CONFIG_ROCKCHIP_RK3568) += \ + rk3566-radxa-cm3-io.dtb \ rk3568-evb.dtb dtb-$(CONFIG_ROCKCHIP_RV1108) += \ diff --git a/arch/arm/dts/rk3566-radxa-cm3-io.dts b/arch/arm/dts/rk3566-radxa-cm3-io.dts new file mode 100644 index 0000000000..d89d5263cb --- /dev/null +++ b/arch/arm/dts/rk3566-radxa-cm3-io.dts @@ -0,0 +1,272 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Radxa Limited + * Copyright (c) 2022 Amarula Solutions(India) + */ + +/dts-v1/; +#include +#include "rk3566.dtsi" +#include "rk3566-radxa-cm3.dtsi" + +/ { + model = "Radxa Compute Module 3(CM3) IO Board"; + compatible = "radxa,cm3-io", "radxa,cm3", "rockchip,rk3566"; + + aliases { + mmc1 = &sdmmc0; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac1_clkin: external-gmac1-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac1_clkin"; + #clock-cells = <0>; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-1 { + gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_LOW>; + color = ; + function = LED_FUNCTION_ACTIVITY; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&pi_nled_activity>; + }; + }; + + vcc5v0_usb30: vcc5v0-usb30-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb30"; + enable-active-high; + gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb30_en_h>; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_sys>; + }; + + vcca1v8_image: vcca1v8-image-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcca1v8_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_p>; + }; + + vdda0v9_image: vdda0v9-image-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcca0v9_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vdda_0v9>; + }; +}; + +&combphy1 { + status = "okay"; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "input"; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m0_miim + &gmac1m0_tx_bus2 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk + &gmac1m0_rgmii_bus + &gmac1m0_clkinout>; + snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + tx_delay = <0x46>; + rx_delay = <0x2e>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@0 { + compatible="ethernet-phy-ieee802.3-c22"; + reg= <0x0>; + }; +}; + +&pinctrl { + gmac1 { + gmac1m0_miim: gmac1m0-miim { + rockchip,pins = + /* gmac1_mdcm0 */ + <3 RK_PC4 3 &pcfg_pull_none_drv_level_15>, + /* gmac1_mdiom0 */ + <3 RK_PC5 3 &pcfg_pull_none_drv_level_15>; + }; + + gmac1m0_rx_bus2: gmac1m0-rx-bus2 { + rockchip,pins = + /* gmac1_rxd0m0 */ + <3 RK_PB1 3 &pcfg_pull_none_drv_level_15>, + /* gmac1_rxd1m0 */ + <3 RK_PB2 3 &pcfg_pull_none_drv_level_15>, + /* gmac1_rxdvcrsm0 */ + <3 RK_PB3 3 &pcfg_pull_none_drv_level_15>; + }; + + gmac1m0_tx_bus2: gmac1m0-tx-bus2 { + rockchip,pins = + /* gmac1_txd0m0 */ + <3 RK_PB5 3 &pcfg_pull_none_drv_level_15>, + /* gmac1_txd1m0 */ + <3 RK_PB6 3 &pcfg_pull_none_drv_level_15>, + /* gmac1_txenm0 */ + <3 RK_PB7 3 &pcfg_pull_none_drv_level_15>; + }; + + gmac1m0_rgmii_clk: gmac1m0-rgmii-clk { + rockchip,pins = + /* gmac1_rxclkm0 */ + <3 RK_PA7 3 &pcfg_pull_none_drv_level_15>, + /* gmac1_txclkm0 */ + <3 RK_PA6 3 &pcfg_pull_none_drv_level_15>; + }; + + gmac1m0_rgmii_bus: gmac1m0-rgmii-bus { + rockchip,pins = + /* gmac1_rxd2m0 */ + <3 RK_PA4 3 &pcfg_pull_none_drv_level_15>, + /* gmac1_rxd3m0 */ + <3 RK_PA5 3 &pcfg_pull_none_drv_level_15>, + /* gmac1_txd2m0 */ + <3 RK_PA2 3 &pcfg_pull_none_drv_level_15>, + /* gmac1_txd3m0 */ + <3 RK_PA3 3 &pcfg_pull_none_drv_level_15>; + }; + + gmac1m0_clkinout: gmac1m0-clkinout { + rockchip,pins = + /* gmac1_mclkinoutm0 */ + <3 RK_PC0 3 &pcfg_pull_none_drv_level_15>; + }; + }; + + leds { + pi_nled_activity: pi-nled-activity { + rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdcard { + sdmmc_pwren: sdmmc-pwren { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_usb30_en_h: vcc5v0-host-en-h { + rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc0 { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_pwren>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb30>; + status = "okay"; +}; + +&usb2phy1_host { + status = "okay"; +}; + +&usb2phy1_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; From patchwork Thu Feb 9 14:30:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 2708 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pg1-f199.google.com (mail-pg1-f199.google.com [209.85.215.199]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 849193F046 for ; Thu, 9 Feb 2023 15:32:01 +0100 (CET) Received: by mail-pg1-f199.google.com with SMTP id 201-20020a6300d2000000b004ccf545f44fsf1167062pga.12 for ; Thu, 09 Feb 2023 06:32:01 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1675953120; 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[209.85.220.41]) by mx.google.com with SMTPS id y19-20020a1709029b9300b001963f6b6bf5sor974061plp.88.2023.02.09.06.31.59 for (Google Transport Security); Thu, 09 Feb 2023 06:31:59 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a05:6a20:7d8d:b0:c2:faf8:364b with SMTP id v13-20020a056a207d8d00b000c2faf8364bmr8079170pzj.51.1675953118948; Thu, 09 Feb 2023 06:31:58 -0800 (PST) Received: from localhost.localdomain ([183.83.141.79]) by smtp.gmail.com with ESMTPSA id j7-20020aa783c7000000b005938bd2bfd3sm1501226pfn.120.2023.02.09.06.31.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Feb 2023 06:31:58 -0800 (PST) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v3 4/7] board: rockchip: Add Radxa Compute Module 3 IO Board Date: Thu, 9 Feb 2023 20:00:57 +0530 Message-Id: <20230209143100.113376-4-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230209143100.113376-1-jagan@amarulasolutions.com> References: <20230209143100.113376-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=n5kj1mYE; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Radxa Compute Module 3(CM3) IO board an application board from Radxa and is compatible with Raspberry Pi CM4 IO form factor. Radxa CM3 needs to mount on top of this IO board in order to create complete Radxa CM3 IO board platform. Add support for Radxa CM3 IO Board defconfig and -u-boot.dtsi Reviewed-by: Kever Yang Signed-off-by: Jagan Teki --- Changes for v3: - none Changes for v2: - collect Kever RB arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi | 18 ++++++ board/rockchip/evb_rk3568/MAINTAINERS | 5 ++ configs/radxa-cm3-io-rk3566_defconfig | 68 ++++++++++++++++++++ 3 files changed, 91 insertions(+) create mode 100644 arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi create mode 100644 configs/radxa-cm3-io-rk3566_defconfig diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi new file mode 100644 index 0000000000..3c925161d4 --- /dev/null +++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2021 Rockchip Electronics Co., Ltd + */ + +#include "rk356x-u-boot.dtsi" + +/ { + chosen { + stdout-path = &uart2; + }; +}; + +&uart2 { + clock-frequency = <24000000>; + u-boot,dm-spl; + status = "okay"; +}; diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS index b6ea498d2b..88d11f05c2 100644 --- a/board/rockchip/evb_rk3568/MAINTAINERS +++ b/board/rockchip/evb_rk3568/MAINTAINERS @@ -4,3 +4,8 @@ S: Maintained F: board/rockchip/evb_rk3568 F: include/configs/evb_rk3568.h F: configs/evb-rk3568_defconfig + +RADXA-CM3 +M: Jagan Teki +S: Maintained +F: configs/radxa-cm3-io-rk3566_defconfig diff --git a/configs/radxa-cm3-io-rk3566_defconfig b/configs/radxa-cm3-io-rk3566_defconfig new file mode 100644 index 0000000000..10b81e0c6d --- /dev/null +++ b/configs/radxa-cm3-io-rk3566_defconfig @@ -0,0 +1,68 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3566-radxa-cm3-io" +CONFIG_DM_RESET=y +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_EVB_RK3568=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-radxa-cm3-io.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_REGULATOR_PWM=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +# CONFIG_BINMAN_FDT is not set +CONFIG_ERRNO_STR=y From patchwork Thu Feb 9 14:30:58 2023 Content-Type: text/plain; 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[209.85.220.41]) by mx.google.com with SMTPS id w1-20020a1709026f0100b00192dea2eceesor917803plk.166.2023.02.09.06.32.02 for (Google Transport Security); Thu, 09 Feb 2023 06:32:02 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a05:6a20:840d:b0:bf:6cd3:954a with SMTP id c13-20020a056a20840d00b000bf6cd3954amr15962308pzd.42.1675953122247; Thu, 09 Feb 2023 06:32:02 -0800 (PST) Received: from localhost.localdomain ([183.83.141.79]) by smtp.gmail.com with ESMTPSA id j7-20020aa783c7000000b005938bd2bfd3sm1501226pfn.120.2023.02.09.06.31.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Feb 2023 06:32:01 -0800 (PST) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com, Jagan Teki , Manoj Sai Subject: [PATCH v3 5/7] phy: rockchip: inno-usb2: Add support #address_cells = 2 Date: Thu, 9 Feb 2023 20:00:58 +0530 Message-Id: <20230209143100.113376-5-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230209143100.113376-1-jagan@amarulasolutions.com> References: <20230209143100.113376-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=M1IE8IQm; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , New Rockchip devices have the usb phy nodes as standalone devices. These nodes have register nodes with #address_cells = 2, but only use 32 bit addresses. Adjust the driver to check if the returned address is "0", and adjust the index in that case. Derived and adjusted the similar change from linux-next with below commit <9c19c531dc98> ("phy: phy-rockchip-inno-usb2: support #address_cells = 2") Co-developed-by: Manoj Sai Signed-off-by: Manoj Sai Signed-off-by: Jagan Teki --- Changes for v3: - new patch drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index b32a498ea7..a01148db22 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -179,12 +179,21 @@ static int rockchip_usb2phy_probe(struct udevice *dev) if (IS_ERR(priv->reg_base)) return PTR_ERR(priv->reg_base); - ret = ofnode_read_u32(dev_ofnode(dev), "reg", ®); + ret = ofnode_read_u32_index(dev_ofnode(dev), "reg", 0, ®); if (ret) { dev_err(dev, "failed to read reg property (ret = %d)\n", ret); return ret; } + /* support address_cells=2 */ + if (reg == 0) { + if (ofnode_read_u32_index(dev_ofnode(dev), "reg", 1, ®)) { + dev_err(dev, "%s must have reg[1]\n", + ofnode_get_name(dev_ofnode(dev))); + return -EINVAL; + } + } + phy_cfgs = (const struct rockchip_usb2phy_cfg *) dev_get_driver_data(dev); if (!phy_cfgs) From patchwork Thu Feb 9 14:30:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 2710 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pf1-f200.google.com (mail-pf1-f200.google.com [209.85.210.200]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 024283F046 for ; Thu, 9 Feb 2023 15:32:08 +0100 (CET) Received: by mail-pf1-f200.google.com with SMTP id m16-20020a62a210000000b005a851506993sf1137895pff.4 for ; Thu, 09 Feb 2023 06:32:07 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1675953126; cv=pass; d=google.com; s=arc-20160816; b=O/oWtRA4GARzZXAwLkK2mYqHxKxNRPbQqv8WFYe2qz+X5Z9FhStCr0YFAqitmZkLnr R1nR9YZxy3dJ7aYeNX/EMcGPzV1+EQL8C+SlfqBXa2RtdpW2eEqvhFLlpHJQdDc2wDzB wlsn1qRtZBWGAsW9Sl4sn4PKCy/A/cytcKFqSpveKcev0iKwu+zU0N/OvC4n2uQ132z8 jo6LEQsLnyGBv3I4sZ/EHn2mXYdsVkYBDEh93yZ7+7JCCl9mRREEfAPZ46dT+jOzO1N/ duOitI6eUniGjLwh839/N367AnjqxpsF7azdXNIlB+WwbgDm+8WzbLkdCxeu4WWsp68F i3UQ== ARC-Message-Signature: i=2; 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[209.85.220.41]) by mx.google.com with SMTPS id i22-20020aa787d6000000b00582d770ffe4sor892129pfo.3.2023.02.09.06.32.05 for (Google Transport Security); Thu, 09 Feb 2023 06:32:05 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a62:2587:0:b0:5a8:5fa0:3d6 with SMTP id l129-20020a622587000000b005a85fa003d6mr1611635pfl.19.1675953125485; Thu, 09 Feb 2023 06:32:05 -0800 (PST) Received: from localhost.localdomain ([183.83.141.79]) by smtp.gmail.com with ESMTPSA id j7-20020aa783c7000000b005938bd2bfd3sm1501226pfn.120.2023.02.09.06.32.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Feb 2023 06:32:04 -0800 (PST) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com, Manoj Sai , Ren Jianing , Jagan Teki Subject: [PATCH v3 6/7] phy: rockchip-inno-usb2: Add USB2 PHY for rk3568 Date: Thu, 9 Feb 2023 20:00:59 +0530 Message-Id: <20230209143100.113376-6-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230209143100.113376-1-jagan@amarulasolutions.com> References: <20230209143100.113376-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=EZQLyhSo; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Manoj Sai RK3568 has two USB 2.0 PHYs, and each PHY has two ports, the OTG port of PHY0 support OTG mode with charging detection function, they are similar to previous Rockchip SoCs. However, there are three different designs for RK3568 USB 2.0 PHY. 1. RK3568 uses independent USB GRF module for each USB 2.0 PHY. 2. RK3568 accesses the registers of USB 2.0 PHY IP directly by APB. 3. The two ports of USB 2.0 PHY share one interrupt. This patch only PHY1 with necessary attributes required to function USBPHY1 on U-Boot. Co-developed-by: Ren Jianing Signed-off-by: Ren Jianing Co-developed-by: Jagan Teki Signed-off-by: Jagan Teki Signed-off-by: Manoj Sai --- Changes for v3: - new patch drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index a01148db22..38cd0f0f33 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -298,11 +298,40 @@ static const struct rockchip_usb2phy_cfg rk3399_usb2phy_cfgs[] = { { /* sentinel */ } }; +static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { + { + .reg = 0xfe8b0000, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d1 }, + .ls_det_en = { 0x0080, 0, 0, 0, 1 }, + .ls_det_st = { 0x0084, 0, 0, 0, 1 }, + .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, + .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, + .utmi_hstdet = { 0x00c0, 7, 7, 0, 1 } + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, + .ls_det_en = { 0x0080, 1, 1, 0, 1 }, + .ls_det_st = { 0x0084, 1, 1, 0, 1 }, + .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, + .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, + .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } + } + }, + }, + { /* sentinel */ } +}; + static const struct udevice_id rockchip_usb2phy_ids[] = { { .compatible = "rockchip,rk3399-usb2phy", .data = (ulong)&rk3399_usb2phy_cfgs, }, + { + .compatible = "rockchip,rk3568-usb2phy", + .data = (ulong)&rk3568_phy_cfgs, + }, { /* sentinel */ } }; From patchwork Thu Feb 9 14:31:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 2711 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pl1-f199.google.com (mail-pl1-f199.google.com [209.85.214.199]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 148333F046 for ; Thu, 9 Feb 2023 15:32:11 +0100 (CET) Received: by mail-pl1-f199.google.com with SMTP id z8-20020a170902834800b001990ad8de5bsf1369287pln.10 for ; Thu, 09 Feb 2023 06:32:11 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1675953130; cv=pass; d=google.com; s=arc-20160816; b=wRVtLb+8kg2St0wrSqKmzVxIQjbpuAqNciJPSuzUwWUuy+FSL0zafZ/ri3e65260Yn hzNeSgWu7M7zNFwhUceqL52grRNcT7WUSvxOoJ472agy9WbL1jU7clNC5bKWXE2l6aLL nmyvjx16yuueeKGUE/MwOAGMRhfyWKR+0T2O1pdfiM2/golMQofTtoR9mY5gHH/CGS03 EBk/8if5VgeUIlCJt8ybFYH3u9EY/DayDT1+OcvfiECABcU1l56oPz/ONSmzYADpRXzi TXl7nrH0fuGAKu4VZlP6QyqW4gE8DvfZGteiaCxX9Hz3tpOL69F55vIsqLNHEryPh5FE tCag== ARC-Message-Signature: i=2; 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[209.85.220.41]) by mx.google.com with SMTPS id a19-20020aa79713000000b0059346fe4bf6sor851246pfg.67.2023.02.09.06.32.08 for (Google Transport Security); Thu, 09 Feb 2023 06:32:08 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a62:7b82:0:b0:58d:9ad4:adaa with SMTP id w124-20020a627b82000000b0058d9ad4adaamr10428517pfc.17.1675953128643; Thu, 09 Feb 2023 06:32:08 -0800 (PST) Received: from localhost.localdomain ([183.83.141.79]) by smtp.gmail.com with ESMTPSA id j7-20020aa783c7000000b005938bd2bfd3sm1501226pfn.120.2023.02.09.06.32.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Feb 2023 06:32:07 -0800 (PST) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com, Jagan Teki , Manoj Sai Subject: [PATCH v3 7/7] config: Enable USB 2.0 for Radxa CM3-IO Date: Thu, 9 Feb 2023 20:01:00 +0530 Message-Id: <20230209143100.113376-7-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230209143100.113376-1-jagan@amarulasolutions.com> References: <20230209143100.113376-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=riZE7IRc; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , => usb start starting USB... Bus usb@fd800000: USB EHCI 1.00 scanning bus usb@fd800000 for devices... 4 USB Device(s) found scanning usb for storage devices... 1 Storage Device(s) found => usb tree USB device tree: 1 Hub (480 Mb/s, 0mA) | u-boot EHCI Host Controller | +-2 Hub (480 Mb/s, 100mA) | USB 2.0 Hub | +-3 Mass Storage (480 Mb/s, 224mA) | SanDisk Dual Drive 04019c9b2e1a58f24ee318c3c123aa5 | +-4 Human Interface (12 Mb/s, 100mA) CX 2.4G Receiver Co-developed-by: Manoj Sai Signed-off-by: Manoj Sai Signed-off-by: Jagan Teki --- Changes for v3: - new patch configs/radxa-cm3-io-rk3566_defconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/configs/radxa-cm3-io-rk3566_defconfig b/configs/radxa-cm3-io-rk3566_defconfig index 10b81e0c6d..404ada3323 100644 --- a/configs/radxa-cm3-io-rk3566_defconfig +++ b/configs/radxa-cm3-io-rk3566_defconfig @@ -39,6 +39,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y @@ -58,11 +59,15 @@ CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_REGULATOR_PWM=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y # CONFIG_BINMAN_FDT is not set CONFIG_ERRNO_STR=y