From patchwork Fri Feb 17 11:58:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 2716 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pl1-f197.google.com (mail-pl1-f197.google.com [209.85.214.197]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 587823F07F for ; Fri, 17 Feb 2023 12:58:59 +0100 (CET) Received: by mail-pl1-f197.google.com with SMTP id jb4-20020a170903258400b00195e237dc8bsf429454plb.13 for ; Fri, 17 Feb 2023 03:58:59 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1676635138; cv=pass; d=google.com; s=arc-20160816; b=AksbmIJxY409+srRcv1zgo97Iir3GcLqTkuZ/MI6nMr+7jHQF3QcakfVSmRZq8e0oM +LInO4IPyRJqFn32OpZh9UBIfpbo14xEi+MP4aRnMEdbyvlYQ8obnuAXN+/k2gzL6QpI PKDRSYm7fEqj44FywGveIQPCs9Y8ohuqsUahvaTqDjoiFoyMP2wmnjwgyJV3HJO9Ofr8 cVxMRFDDzXX3gGdjyBN2raM10LYLwa+pIqcE+rPgV/HNo5wALXaIybdGpmxMzmTfEKoR WZzXhkQCIo21TZ2ZlF7u3zq2fd2KqFgn3KYoSEOIF+HxZiUhFANNlrjFMPKxeR5kI5w1 57aQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=G1ZqegNT27Lm2TL/0HFwMTOIc9tW6xWJP7hwMcfyGvI=; b=l1zDQHWLMPmIxT2oU1ZDqe0GkBFwm4CZKfBx6wR0fjYMSW+oTlg6sDFoGCGqnT2Vjd EdyHP4eMy9MMUw1Tpc6VPE/lslYroRfbmzsRjGcNhh5Utzmg/LXorY5zjxYpAgwQWTR7 CsNpIgxwYeM5MeYnCxMeQoWhJe2A0/m5WLJQQhheAcP99NoKrYbt9ycmteAvJmwsmRin fAGv3xwFPp4weL718G9REwnx8CPDA2id3AumAy7dAYVGFaiivxje09fGVjrc2aUAOT0L oMcna3v5ksTNA3E0an3R1aVHfNInVex4s6w9MvdsPYALIPWinJPWj/IRw+gVq9K4g4J2 0jhA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=oi1kd8cG; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1676635138; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date:message-id:reply-to; bh=G1ZqegNT27Lm2TL/0HFwMTOIc9tW6xWJP7hwMcfyGvI=; b=mju29OlERqhe832xVfg3w68yr/XQH52trqK7urgTAPhMM/rtdg8Tw2v5fr7oeDB2/R m7SwaeA6L+ymGmI3t7SMK9/U5Gu07l0GOTebtHHY7tI09di+ZpMdVGj9Okt2PPUH9Rx9 9JD7ez+kVL1iDgCMi2UgyRnSqiC6aEc3FQHLg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1676635138; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=G1ZqegNT27Lm2TL/0HFwMTOIc9tW6xWJP7hwMcfyGvI=; b=LCZzeFKRARxfN8+Mbb6CDYJbv2L9NuWCkz7OpnlzJH51Y5fK9D7TYMIV4XYevPVds0 lBVWxboKHViNPFlyTRgYgNTGjMilk4zFjCfOiu+HD7lk3+dSo4VrDN9rSOdGF57RQiBE nEBNz0GZLhJ6dKO+XeiXqjsu97PhgNxtdVoByk5lKGj5wfggkv3JFtRIvwpc50ezFnsd V2mSgDQBE+cCp1wVdwZZsTmItz0aKGCd7LyNOQdGIAYEDqh5Byqpqs3dYYwMJCT5Gx63 tjPASafgaTlbj8iXL47QMPE8QBVZJV894jlgW41v1GlIu+AoinQMH4ILH87qFSmdwe5b XePg== X-Gm-Message-State: AO0yUKV04bGTbaG76s6vlKuFH953QcgVmEsbMUojbTvDtu2ANTwJKKEI kxWdlRKZQnJQlpqav2r1V986PV3c X-Google-Smtp-Source: AK7set+A7PqqGe1oMu7U9PNbU/M4jQDeai1uR0D273d7waZObkgV/MG8dIqKcBKpCB0O5agdvpmX0g== X-Received: by 2002:a17:902:d898:b0:19a:b302:5172 with SMTP id b24-20020a170902d89800b0019ab3025172mr6680plz.3.1676635138025; Fri, 17 Feb 2023 03:58:58 -0800 (PST) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:902:f64c:b0:194:d87a:ffa6 with SMTP id m12-20020a170902f64c00b00194d87affa6ls1452646plg.1.-pod-prod-gmail; Fri, 17 Feb 2023 03:58:57 -0800 (PST) X-Received: by 2002:a17:902:fa8d:b0:19b:c14:9f4d with SMTP id lc13-20020a170902fa8d00b0019b0c149f4dmr2922835plb.38.1676635137132; Fri, 17 Feb 2023 03:58:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676635137; cv=none; d=google.com; s=arc-20160816; b=wwn6NDDd41PH9e5nCXVUKOFdYYZHcNXwkuGGb83fQPpB7Pj0bbvue1nrxFBoBPoZ8P Mh2h6oIs1tu80gP+ajQHH2NXaP0Xo6DwZfNQ4abOjt4Zv4v4aVL+pi+EjBN56w6UyV9i 26Z0FBJL88zF4auIk1VS897/kYZswRBaFapDRd4dwAbRbozHL39oYYDkSD4/RsYKIDkT TjYrN/XN8fXKY7hxVrEJh4G5BXYZFkacMRVJpF2Zwm8P9OAOfTWqttfdIF6MV1JlHjYU WV79ZDxL/m1ouMNZM/www8kV/PcYGXU4U0EUXZWavqTMymGGTyCBBOBBAaxIF+1LntM3 qKkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=LM8hqhv0htwS469rAYzoqmPj2c9P1mVfvINgipRu+ac=; b=nn40siIADTwLIEKiUlLIpjU/ji6FI1gQThIOpOSWZttVfa6DzMp37xYKVJFE+B71+l zK6SA22TplFans54tvxbBsQhVS5I7ai4EcywCSq6DmiNglBUmtXhNG4vseTv03mEDLPD ygGxpobXzNDtOwZCRVZMgfWKNjw/0v9ByrHbVqQ6sGN6zHh066V9NGDkSJg+gEwDD00T I/VxdLwJkTavJ7HAcrpAdOfP1JnykTOAUKYS/uWlvUBuHVhpd64ZMB0kP6lYVL5QiM6M CBZncYxMdzLypAgDkZ/B83GBlULvSLcJvOWyDOdcyPEDXvVnUExtmwmMrjCKSPQQP5Jw HC1g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=oi1kd8cG; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id d14-20020a170902654e00b0019ae40b11cbsor2057355pln.202.2023.02.17.03.58.57 for (Google Transport Security); Fri, 17 Feb 2023 03:58:57 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:902:e74a:b0:19a:90ed:af6f with SMTP id p10-20020a170902e74a00b0019a90edaf6fmr10142675plf.60.1676635136786; Fri, 17 Feb 2023 03:58:56 -0800 (PST) Received: from localhost.localdomain ([183.83.141.79]) by smtp.gmail.com with ESMTPSA id ik15-20020a170902ab0f00b001991d6c6c64sm2989418plb.185.2023.02.17.03.58.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Feb 2023 03:58:56 -0800 (PST) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v4 01/12] rockchip: rk3568: Move DM_RESET in arch kconfig Date: Fri, 17 Feb 2023 17:28:34 +0530 Message-Id: <20230217115845.75303-2-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230217115845.75303-1-jagan@amarulasolutions.com> References: <20230217115845.75303-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=oi1kd8cG; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Like other rockchip SoCs, DM_RESET is useful across rk3568 platform. Select it from arch kconfig. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/Kconfig | 1 + configs/evb-rk3568_defconfig | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index b678ec4131..3dc85df65d 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -286,6 +286,7 @@ config ROCKCHIP_RK3568 select REGMAP select SYSCON select BOARD_LATE_INIT + select DM_RESET imply ROCKCHIP_COMMON_BOARD help The Rockchip RK3568 is a ARM-based SoC with quad-core Cortex-A55, diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig index a76d924d38..0b2325ff24 100644 --- a/configs/evb-rk3568_defconfig +++ b/configs/evb-rk3568_defconfig @@ -60,7 +60,6 @@ CONFIG_GMAC_ROCKCHIP=y CONFIG_REGULATOR_PWM=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y -CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y From patchwork Fri Feb 17 11:58:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 2717 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pl1-f200.google.com (mail-pl1-f200.google.com [209.85.214.200]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 04D1C3F07F for ; Fri, 17 Feb 2023 12:59:02 +0100 (CET) Received: by mail-pl1-f200.google.com with SMTP id n18-20020a170902d2d200b0019af23e69dcsf484604plc.19 for ; Fri, 17 Feb 2023 03:59:01 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1676635140; cv=pass; d=google.com; s=arc-20160816; b=B9dsPaNTRUV9wSo7YobMC6SBgXrDmDph9UTdkRz8z9rYTYCr1iDmlEECPJH6zKW+bN AZE4ke6YJgPffPJKjGAOZBxQzGLKGSuFBZZbFJEarliaK66nF4GIirREZkq16XOBToi2 zMa7z5m6Miivuz1lEb/98j0qM0e+pmeVTWTimT8G3SgCW3vYI5IY6gGX6VhqTZxs5v8W sxRz1XVcol7DcV0hKYbHIG8e3s1ifF2wkqpJx1f6OgoRTJwrPtL/l2vOrEH1pIWgW1P0 Eigdx0YQhBoW4ZedLaW+TCXDqmfTVrLQRxnYTMLDET1fcjftIJ6M9FazjlGq+9/wRY4i gWmA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=b+JSTwWwREKQ+D1AYjxJbnxNJXdu1ragwQgWNo1LpkU=; b=ItC2dpQ5vE2ZLkkEkuSF+T7aLHiv89l4kU7KSamtDLJyii6awburWkQx9fzh5pBhTU 1INeTVfGydfgGDLu1nAEy7fzjNycRXLY/NLlRwtRdYlaU5BjyZkEp1eGcMFCDrCMAGm8 PmN/8EpjQH45snOeAu8d3bdov780lN4foOAdI0o1V6n9Ytod8ENQToIWIC0VKXJlM6BJ y5F+4bvwwJkBT3O7VRM2TJOwMshojTAhPzlEa3sJTt1lI4iH8Orv6p9yEmImNor9NDAZ ZFirqnQbcx6MBI5CoJ7VeavJlo5TYP8e9ghVDECC3XaBn98M8PmzrxQAWYmDE2FZMpy6 wPzg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="Ot/ABWxd"; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date:message-id:reply-to; bh=b+JSTwWwREKQ+D1AYjxJbnxNJXdu1ragwQgWNo1LpkU=; b=jqTD2mfPcVgqWn5JYFA8OwC25otQ97CZweoCbGS2WyoLYn0J/yNkHIT6i8uQKL9UaE gmRTIQcnGmymwW62JeivJauKtHVIF06V9OLNzunmot9Vsuv0FH36ea5ZVi1S3eBzSh+1 mbVvSml93J1mPow85fEieWG4SSEJWwYDth6AY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=b+JSTwWwREKQ+D1AYjxJbnxNJXdu1ragwQgWNo1LpkU=; b=L6fn+bnRIAqiu2sTEc6LWqKJa4zSZWhpJLFS/P6vw6OiMNiB2dgaiLI430wlnNuV+A Jk0JCwjsfWpjZWYxL5tRazySzRVltQ2pCSgnmQ/moo/mMaYzxtoVj+T4bsIHCgukvwiD 7GScEbVlduSXsL6a/ewf8kQEKrg/4QeBUwGRbTFs9OuXBS0VTpZloCED/UVu/Jv2KJ+r M8NhMnjzSjVy6QghfPv/Qdi6ByAmS8RFtMX7fc2GaPW1prasJn2X+QIe5Y2uoAykStHW kOFWPz1oYeO6FmTwaP6euoBhYuVwkIvrl47Q+BByQIq5maRVxL8rLhajiy/rMR1UHHt0 mh9A== X-Gm-Message-State: AO0yUKU/oqILV1mv/D1jJzExXAuVcTFuWJlODqRWIgHsK9WQscopTRma NBtOkT/3rEgiz/g5VFzx6ucUJ8sA X-Google-Smtp-Source: AK7set8A5kONxu82+kQ3tUKoEOwhH2tOqw0OJiEcBYxSalb8TWMbjr3htNzqUBLCQxgbFuaasDKz7Q== X-Received: by 2002:a17:90b:1a8a:b0:233:fbf8:6876 with SMTP id ng10-20020a17090b1a8a00b00233fbf86876mr1362284pjb.57.1676635140643; Fri, 17 Feb 2023 03:59:00 -0800 (PST) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:903:2309:b0:196:f81:2760 with SMTP id d9-20020a170903230900b001960f812760ls1300773plh.2.-pod-prod-gmail; Fri, 17 Feb 2023 03:59:00 -0800 (PST) X-Received: by 2002:a17:903:22c8:b0:19b:64bb:d546 with SMTP id y8-20020a17090322c800b0019b64bbd546mr2419832plg.18.1676635139726; Fri, 17 Feb 2023 03:58:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676635139; cv=none; d=google.com; s=arc-20160816; b=ajoZkbo6kU6dFr53zzOhpa3XoKCK9c+Haj36WkDFNesksx68kNBPwP6isKDlYGKfT6 4kxXpicrVtikf5TtNc23oKv2ZswTt8j0IT1hibgS5fGzgPq1ot0axt/Ubsw9xVxPpRyY DS4X3QUJ+nOO31yYoT+Qlmnh2nLIg0tL7wWXV/OYs3J+567mJ9RoUIoW+UXX4Ds8lmSS pfya2+IWVRiVGb6//2A3haDaPTOSjzbl5ZUzXLiK1KnzESnuJBU5DJKGsHvuTpb53IU6 LGgS2HK+8pdJj82kCONJI0LYZUFm1t1LfAl2cULePiZYb5oTaYfSMarTbWWXs4bkZvbI 6mPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=qfT2kVhpxbm5LVCc+/RKcaDZ7uZit4VX2zfU5dGxTfY=; b=rB4r1/N7VtlF7L4Z9/uXdJ5tzprrYq70Txv00yothbh6Cgn2gsIzYEQ2TmHiKzWZYV 0Tqkevc+f/AmL+YaQZ5oPndOtRhWZgid2+ioNdf1Ga4ZzzEZ8EQRsuF8V983bLjmDbMy kw1zI9IGATbF7SURraXZi9AamfCB8Q6V150nHsYCXfECaxycd6vXJvBDq290TNcRUBwg HlQtBMa27QwKccc7F+bUZ5WUzMNhbgnYQ7HwpB8oGEIS9iETRlOh/bVGgwp+XPj3nX8t NHIekvJTYEtq/BussjMS9LsuewgxN3qbNY6608VBf+VERbwp2ljPDScaK8p52D785zQN Yn5g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="Ot/ABWxd"; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id t7-20020a1709027fc700b0019aa44ec68esor2095413plb.35.2023.02.17.03.58.59 for (Google Transport Security); Fri, 17 Feb 2023 03:58:59 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a05:6a20:54a0:b0:be:ed2a:b2dd with SMTP id i32-20020a056a2054a000b000beed2ab2ddmr5866105pzk.6.1676635139435; Fri, 17 Feb 2023 03:58:59 -0800 (PST) Received: from localhost.localdomain ([183.83.141.79]) by smtp.gmail.com with ESMTPSA id ik15-20020a170902ab0f00b001991d6c6c64sm2989418plb.185.2023.02.17.03.58.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Feb 2023 03:58:58 -0800 (PST) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v4 02/12] dt-bindings: rockchip: Sync rockchip, vop2.h from Linux Date: Fri, 17 Feb 2023 17:28:35 +0530 Message-Id: <20230217115845.75303-3-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230217115845.75303-1-jagan@amarulasolutions.com> References: <20230217115845.75303-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="Ot/ABWxd"; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Sync rockchip,vop2.h from linux-next, and the last commit is commit <604be85547ce> ("drm/rockchip: Add VOP2 driver") Reviewed-by: Kever Yang Signed-off-by: Jagan Teki --- include/dt-bindings/soc/rockchip,vop2.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 include/dt-bindings/soc/rockchip,vop2.h diff --git a/include/dt-bindings/soc/rockchip,vop2.h b/include/dt-bindings/soc/rockchip,vop2.h new file mode 100644 index 0000000000..6e66a802b9 --- /dev/null +++ b/include/dt-bindings/soc/rockchip,vop2.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ + +#ifndef __DT_BINDINGS_ROCKCHIP_VOP2_H +#define __DT_BINDINGS_ROCKCHIP_VOP2_H + +#define ROCKCHIP_VOP2_EP_RGB0 1 +#define ROCKCHIP_VOP2_EP_HDMI0 2 +#define ROCKCHIP_VOP2_EP_EDP0 3 +#define ROCKCHIP_VOP2_EP_MIPI0 4 +#define ROCKCHIP_VOP2_EP_LVDS0 5 +#define ROCKCHIP_VOP2_EP_MIPI1 6 +#define ROCKCHIP_VOP2_EP_LVDS1 7 + +#endif /* __DT_BINDINGS_ROCKCHIP_VOP2_H */ From patchwork Fri Feb 17 11:58:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 2718 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pj1-f72.google.com (mail-pj1-f72.google.com [209.85.216.72]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 342EE3F07F for ; Fri, 17 Feb 2023 12:59:05 +0100 (CET) Received: by mail-pj1-f72.google.com with SMTP id g6-20020a17090a3c8600b002368c5a30bdsf35180pjc.5 for ; Fri, 17 Feb 2023 03:59:05 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1676635144; cv=pass; d=google.com; s=arc-20160816; b=icWkEhLgy+7UhA+FFFU6cHvLgsAg3aHPsu+boo+Xc9Qt9t3jkc8jlpE/YwwksXYqXS g7FkKrVECU+GmlM/DL5zdB6hvup4GCTH5AmHoeqtdfJS70gx/z5xzcvWBog+5w4xsegE bnWGRBXsQ18bB5ENUi1qVFzxLerrf0hznzuUcu7ws92E6p/iYrlbCN0eYPNYciYNqNo/ 90x3jmv4uTh2cWiK7Kjb5HCwNrHCS57yJAqH3KlzA+do7Emaa1VvTm3aSQV6A6Tn7YBW 8bwr9hHT+tTyDVHqtDcdP0jdfzStRqPNVROCpXV/ypTHJ9cBRCHT0Snp5MSZCnL66QdE krNA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Cthj6tYQAx2Zo0CJptoTWI3gkPX3NXMelbOuQOs6YQk=; b=eSpl1dItXlnlsDPwuE9bc7h33mxKXwMvUaWDOo3WhfeWEYiDC4XYW9+XbRiSWEdCSE aBxBMVWXx75TZGrrkgIKwOm/xbWMLRkZeoCzyFgAWGAbLoyvjCsHBJTil5RzldtMvbF2 GR0iFN6yAHZu4v4CJLQNU7EwVTPNHaBDvBSjbV4DpnT3iYAmP1z+JfCajI9ohc2Fyc1b esvN3hDLFVTjKF/q4SU/F9L8jIaM/V7n9aqN7eQvFsrSUQWIbOrhF+Bvi2m2V02msAuW N+xsjiwm6Veq7Wu0ZQcTp4V5TulOLngyuOwlySq5B8qcblBuuQVpSjSS4vmG9MdTSk7g aHhA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=e1px38kC; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:content-transfer-encoding:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:from:to:cc:subject :date:message-id:reply-to; bh=Cthj6tYQAx2Zo0CJptoTWI3gkPX3NXMelbOuQOs6YQk=; b=Nt+Pl1kAkq8J2Du72/iaC33HTP4/7Kh6MoF51FVp/Ull03mVtDizBUcQ7MV/A6wGYj z6SvCkcIuYSc5CK8AIQpkZcE5182qg8bbJxywG7o47/rtXSXgl6PIhps/thSTm7Ah2d+ tBmuVXYjwwFazFTbA+sK7RZWSLrYtLtF+cneo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Cthj6tYQAx2Zo0CJptoTWI3gkPX3NXMelbOuQOs6YQk=; b=FCa07XY+E/rzz1Fa2wF2g5F0hRWmvTi0XjYt8TXvAGLEJlNWDWsWe5XdqV73ePbuIK 5ZJFqNp112K5TZzGLG+w8ttKBYPeOIXZs8jIS8aWKAfxQqgE7knO3OuoWasSXL3eFQLC VkoYNc1BDdgJy8/YWVcG6Gv5ra7ztGlSSy3iWiaAObcqX/7FvYmBBi1EIConnXTs5kFH R5O2qe2vtdDmfOXr6h0SWx6zXu8J9WUKwxvEL2Q2C48I2bobkCpXTCI5J3s4v/HocyNy NL8bxMJmdDwxrZCyfzuqiWVTBT8ATf2M2LjMv4mUBUB9FeSzPpoGPyR2HreXnGn6LfaL 8B0Q== X-Gm-Message-State: AO0yUKUMxqPu/dsXM0/XGQsWPBsmrknYn8jY576Eardsyctd3fVWKWnJ h9CmD0EDhuFZOekgMGyQ9uWvYJjg X-Google-Smtp-Source: AK7set9mJuUGdFXDCgIZFN/5ckg2HnB0Z0jOz5+X4ifF4HGz/xXBK8X/dNSRvzxNMG9PwC+tV+aCvg== X-Received: by 2002:a17:90b:48c2:b0:233:ba2c:16a6 with SMTP id li2-20020a17090b48c200b00233ba2c16a6mr1612200pjb.109.1676635143817; Fri, 17 Feb 2023 03:59:03 -0800 (PST) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:90a:fcb:b0:234:a618:558a with SMTP id 69-20020a17090a0fcb00b00234a618558als1075217pjz.1.-pod-control-gmail; Fri, 17 Feb 2023 03:59:03 -0800 (PST) X-Received: by 2002:a17:902:f9c6:b0:19a:8378:bddf with SMTP id kz6-20020a170902f9c600b0019a8378bddfmr444698plb.4.1676635142832; Fri, 17 Feb 2023 03:59:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676635142; cv=none; d=google.com; s=arc-20160816; b=LznGoCb1zKOhBCiD4l41QH7LX4BeA8qhAPUauHlzAA++VezDpU+SCZ0YJ535vam9JA NhX+rK4YTRBF1TCIhAmK7iGEJhaiHRyAMuJNU+nPe4J1NuI9mzOo+UvpSxf++pOTV9DO IA9adFM2unW+vSL5WGS67GJujXdRysk8AsiJXqbvdZ+Zz11SE68Cr3ecwtzb13NdNiir CcsWHlf3SrqmU54JtdOTXsnGC4TR0bcrQ11evT3IxFl6p/d4jYVbyIHCe07kOsZT+F1G PBwhdT3868vJOReV2pG3c9BTxSxUHBfzy5z5vaP29KSFeLLNFyU1Si3cZhoeY8Zvghl3 eabA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=APeMavjI/OTYTScST9eaMgD+tsOOXaMw4NZ/hPkakMM=; b=T/A4lUnGFr1rGw20PeT4czx4Cnq0wsda2MqvC5CnQKqsflX049ht5vkWYQ1H1YKPmH QJZktkr70iddFTDDAeHLJUMHLyj9inUWlv3J8o6PFvIepZxM9Q3HCnjfX6WoavJ9lh6R 3PDXQMlOADPqUO5Nkbdhjb9uaz4HpBsxaDVJUcm9Fu1Nt4V5aoxd/zB/k6IK6scFSc6B TTsz00R0vq6HzfvsqlbTMAwDk7+eNkpx/w9UunDSB6XMUO+7PpFG/ym/ZC3rX0NW2ouI /boU/fAjiz2Yxi58PCkgtrqomHMHiEkoHC+aqzAlMmTsnLlIRBoaWOoA6ZwdRlE2oiJI MExg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=e1px38kC; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id 4-20020a170902c10400b00195ff2ce91asor1996110pli.184.2023.02.17.03.59.02 for (Google Transport Security); Fri, 17 Feb 2023 03:59:02 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:903:18a:b0:19a:a815:285e with SMTP id z10-20020a170903018a00b0019aa815285emr11109360plg.62.1676635142481; Fri, 17 Feb 2023 03:59:02 -0800 (PST) Received: from localhost.localdomain ([183.83.141.79]) by smtp.gmail.com with ESMTPSA id ik15-20020a170902ab0f00b001991d6c6c64sm2989418plb.185.2023.02.17.03.58.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Feb 2023 03:59:01 -0800 (PST) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com, Jagan Teki , FUKAUMI Naoki Subject: [PATCH v4 03/12] arm64: dts: rockchip: rk3566: Add Radxa Compute Module 3 Date: Fri, 17 Feb 2023 17:28:36 +0530 Message-Id: <20230217115845.75303-4-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230217115845.75303-1-jagan@amarulasolutions.com> References: <20230217115845.75303-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=e1px38kC; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Radxa Compute Module 3(CM3) is one of the modules from a series System On Module based on the Radxa ROCK 3 series and is compatible with Raspberry Pi CM4 pinout and form factor. Specification: - Rockchip RK3566 - up to 8GB LPDDR4 - up to 128GB high performance eMMC - Optional wireless LAN, 2.4GHz and 5.0GHz IEEE 802.11b/g/n/ac wireless, BT 5.0, BLE with onboard and external antenna. - Gigabit Ethernet PHY Radxa CM3 needs to mount on top of this IO board in order to create complete Radxa CM3 IO board platform. Since Radxa CM3 is compatible with Raspberry Pi CM4 pinout so it is possible to mount Radxa CM3 on top of the Rasberry Pi CM4 IO board. linux-next commit for the same, commit <8f19828844f2> ("arm64: dts: rockchip: Fix compatible for Radxa CM3") Add support for Radxa CM3. Reviewed-by: Kever Yang Co-developed-by: FUKAUMI Naoki Signed-off-by: FUKAUMI Naoki Signed-off-by: Jagan Teki --- arch/arm/dts/rk3566-radxa-cm3.dtsi | 425 +++++++++++++++++++++++++++++ 1 file changed, 425 insertions(+) create mode 100644 arch/arm/dts/rk3566-radxa-cm3.dtsi diff --git a/arch/arm/dts/rk3566-radxa-cm3.dtsi b/arch/arm/dts/rk3566-radxa-cm3.dtsi new file mode 100644 index 0000000000..45de2630bb --- /dev/null +++ b/arch/arm/dts/rk3566-radxa-cm3.dtsi @@ -0,0 +1,425 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Radxa Limited + * Copyright (c) 2022 Amarula Solutions(India) + */ + +#include +#include + +/ { + compatible = "radxa,cm3", "rockchip,rk3566"; + + aliases { + mmc0 = &sdhci; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_STATUS; + linux,default-trigger = "timer"; + default-state = "on"; + pinctrl-names = "default"; + pinctrl-0 = <&user_led2>; + }; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_1v8: vcc-1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_p>; + }; + + vcc_3v3: vcc-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcca_1v8: vcca-1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_p>; + }; + + sdio_pwrseq: pwrseq-sdio { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h>; + reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gpu { + mali-supply = <&vdd_gpu_npu>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + #clock-cells = <1>; + clock-output-names = "rk817-clkout1", "rk817-clkout2"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_gpu_npu: DCDC_REG2 { + regulator-name = "vdd_gpu_npu"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG4 { + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca1v8_pmu: LDO_REG1 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v8_p: LDO_REG7 { + regulator-name = "vcc_1v8_p"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-name = "vcc1v8_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG9 { + regulator-name = "vcc2v8_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + }; + }; +}; + +&pinctrl { + bluetooth { + bt_host_wake_h: bt-host-wake-h { + rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reg_on_h: bt-reg-on-h { + rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host_h: bt-wake-host-h { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + user_led2: user-led2 { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_reg_on_h: wifi-reg-on-h { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_host_wake_h: wifi-host-wake-h { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc_3v3>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdmmc1 { + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm43455-fmac"; + reg = <1>; + interrupt-parent = <&gpio2>; + interrupts = ; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_h>; + }; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_ctsn &uart1m0_rtsn &uart1m0_xfer>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&rk817 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_h &bt_reg_on_h &bt_wake_host_h>; + vbat-supply = <&vcc_3v3>; + vddio-supply = <&vcc_1v8>; + }; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; From patchwork Fri Feb 17 11:58:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 2719 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pl1-f200.google.com (mail-pl1-f200.google.com [209.85.214.200]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 5E7EE3F07F for ; Fri, 17 Feb 2023 12:59:08 +0100 (CET) Received: by mail-pl1-f200.google.com with SMTP id h18-20020a170902f71200b0019af43e2fa6sf263457plo.4 for ; Fri, 17 Feb 2023 03:59:08 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1676635147; cv=pass; d=google.com; s=arc-20160816; b=Yhb5/9r+TZrLcnnoxkQ1U7NnlbFH5aAxFtFbte0+FtoHCgO/jmfCVILX97O4gmoOWP crHPGUg04erw9sO9fxs8veLVSCFfgdjY3Ntn/eC68dnEG5l6gG68euS6o+Sh1UTrgM5s N18t84Deylny6NGZjoQ1o0KtyCgjFQ0fPsDNQx4DDbMoHd/XUJoYGhWAVHjjreM2aNBF i1ZSmhNLYmnYcLQkNIbm8hs2pXBTJxIduSbDpn3ES1mQSNwAuFUUl/Biz/5e23QiCP5O BpmuQysUfMvxr7QpIAX9S31GYTBRNrysQ0vbP2406FxA3c/XBlUr43oOWwEQ24hZQjrS Nz3A== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=4EiEUXNK8OsK7LWmXbo4vh6tw1NY6GcsLsSS50VYns0=; b=NAXw5fxFgQNNECgROVIecjp0ngqVSILtk4iC0tUo+B6uoXoZI+TPSZ8yi9SMaCPvB5 vsxVfHRJDbsRQOu5Eq8PAn8BHHlhBezA0b05P92LMOTGVO7XN48F77JWyVeRbDOXtSEV uJGs8CK+yFb/Thpka9WcPbQEZAMUIBntk89r9jV0qsi0tyHKvR7yXCvVuQ/D9m9M8PAb os4/0ERtI21lohgKGrdoGm2ZkyfvS1lRcaveZz1I6lrxh0nBqNq/dMmAVgkGNCzCCXfH A4cmkLNosrV8QNi+pwU1JgcXTvlopb088PoPsBBBlRZldFQG43hU5PAfjft8aIxF2V6n JedQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=lJELhyNe; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date:message-id:reply-to; bh=4EiEUXNK8OsK7LWmXbo4vh6tw1NY6GcsLsSS50VYns0=; b=b7rfyC43d/3QjEiwA/fMtxVl6j4DE53JGKa1cfJ70xsEAsRcwswPpGU5t29G7a+Jpg Sh2P/FndJXyMh0871nq+/LqbM74hHUjaCL9ujfdzh27HXX9AJS5f0dJ5FxBTMeRDtNCU TmZqzHRmOFw0NsVgOnu2wGe10dplupDQdepBU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=4EiEUXNK8OsK7LWmXbo4vh6tw1NY6GcsLsSS50VYns0=; b=boAPVB01AAzH+/xIz8AqlscILHcYpApK0av4QiEjJ/sIGywIlkwYLJTMU0oDLzARQ9 15P77bFHDidocoPtN7PcYMGKqXxxnAPtGPdKkbSz7UQ0ujQuy90ZofKj1odMZGxhfubf vTpmMlCzK4o9xcDi0M2Du+p2c2XkfSh0NEbXUaEwophZoV9CC+xxTJN3nc3LnJE00iCr XAMR9IOaaUpTLZeEO6io8stgu2+bvDvSGRgzHfOPa/2cdx1uecYY97ePwenuJRFe1RVu Q65vPZRKKCM+JYCkM5uCHBZILV5zqY2C1H4mC2jQAvy+4rTj81lLhUkN0qUGQt0rbNoe 0OAw== X-Gm-Message-State: AO0yUKVydDIPIQgYlqNW0gB9Y6j0GSoWrb1AEoyYWAjW8g8c4rj+RyHF 5zKSEf74cnAjCk32mpUVSM9B8E7E X-Google-Smtp-Source: AK7set8jW7dzxAhwaz/2ckxrr3dznpYaj4la7OIaPVN4JQutnG/u7QNl6Axbt/icUI7v0XVDQr0baQ== X-Received: by 2002:a62:aa0d:0:b0:5a8:b093:ff67 with SMTP id e13-20020a62aa0d000000b005a8b093ff67mr153660pff.4.1676635147153; Fri, 17 Feb 2023 03:59:07 -0800 (PST) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:902:c103:b0:196:751e:4f6e with SMTP id 3-20020a170902c10300b00196751e4f6els1576077pli.10.-pod-prod-gmail; Fri, 17 Feb 2023 03:59:06 -0800 (PST) X-Received: by 2002:a17:902:f682:b0:199:2ee:6238 with SMTP id l2-20020a170902f68200b0019902ee6238mr795890plg.16.1676635146157; Fri, 17 Feb 2023 03:59:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676635146; cv=none; d=google.com; s=arc-20160816; b=vVpe8pQz3I0+XDmY9Q059oMTGVQimMGyoxjEjzSq/u+9nVes2I2D7400PGOBySEQVg kTvbiWT6u5JVjWnekpfCAtvyPDnPE/lF2/LRZqb4epLgzOo4DQZFMveR+HYx9cFtLXNI 8RatovbT1RVY/7US9XlTDdhSLijy3VWhrRdxuplZZs5CxWRAlk/GwQTraW2EyWBup5yN ZjOuQggXgQMZgQZG19DgUGeUMeEZ7C8yCWEW2ozQ8psr9AATHNj8L71bxhtbnk9Vg9qB jMpM8JAwIy7HjtSHdJhPFa8UjGLgGdKt8P79Ijt3iPcPhpMkGx9Exm0aN0CY8GUbfm+g BA1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=j+JPnqZKvocXg8/fZ/5MxRnXgwp0mUaDPJt4v9EX4JQ=; b=E0xxvdTXoovH57mjNf6GxqknZDJ3kjyBtVZXyC/K6a7SVuo1izeMqCEc9z3vCpGCQt zc7ilBzlKW8W44Mh2E7Qrkq3oASsAs+9V//TEB6xAGUnV8/7lK8EkhTPlzEkZSeS9TO8 EAfcyFd5jHaMOlh8a9NPhPt309KFXa1b5ywvrdK0ku7iqxfCVz+Lm/8M6EZU/aMN37oc 2+PWRwxmfOiXZwaU82BPtkYtSOrsDVnKykHuSaViTkHTf8Gzr97WQhECexSZyM+f61lz OX8wROz3EEjySiBVCTmPV45D4zPKCqGSIewJ4p4fx5mm2fX6JT5RmpjtdV9/FJWuxN6+ 54WA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=lJELhyNe; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id b9-20020a170902d40900b0019a826eea48sor2002830ple.204.2023.02.17.03.59.06 for (Google Transport Security); Fri, 17 Feb 2023 03:59:06 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:902:f20a:b0:19a:743e:b152 with SMTP id m10-20020a170902f20a00b0019a743eb152mr1104204plc.63.1676635145779; Fri, 17 Feb 2023 03:59:05 -0800 (PST) Received: from localhost.localdomain ([183.83.141.79]) by smtp.gmail.com with ESMTPSA id ik15-20020a170902ab0f00b001991d6c6c64sm2989418plb.185.2023.02.17.03.59.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Feb 2023 03:59:05 -0800 (PST) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com, Jagan Teki , FUKAUMI Naoki , Manoj Sai Subject: [PATCH v4 04/12] arm64: dts: rockchip: rk3566: Add Radxa Compute Module 3 IO Date: Fri, 17 Feb 2023 17:28:37 +0530 Message-Id: <20230217115845.75303-5-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230217115845.75303-1-jagan@amarulasolutions.com> References: <20230217115845.75303-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=lJELhyNe; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Radxa Compute Module 3(CM3) IO board an application board from Radxa and is compatible with Raspberry Pi CM4 IO form factor. Specification: - 1x HDMI, - 2x MIPI DSI - 2x MIPI CSI2 - 1x eDP - 1x PCIe card - 2x SATA - 2x USB 2.0 Host - 1x USB 3.0 - 1x USB 2.0 OTG - Phone jack - microSD slot - 40-pin GPIO expansion header - 12V DC Radxa CM3 needs to mount on top of this IO board in order to create complete Radxa CM3 IO board platform. linux-next commit for the same, commit <8f19828844f2> ("arm64: dts: rockchip: Fix compatible for Radxa CM3") Add support for Radxa CM3 IO Board. Co-developed-by: FUKAUMI Naoki Signed-off-by: FUKAUMI Naoki Co-developed-by: Manoj Sai Signed-off-by: Manoj Sai Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3566-radxa-cm3-io.dts | 272 +++++++++++++++++++++++++++ 2 files changed, 273 insertions(+) create mode 100644 arch/arm/dts/rk3566-radxa-cm3-io.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9d647b9639..037ffc09b1 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -165,6 +165,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399pro-rock-pi-n10.dtb dtb-$(CONFIG_ROCKCHIP_RK3568) += \ + rk3566-radxa-cm3-io.dtb \ rk3568-evb.dtb dtb-$(CONFIG_ROCKCHIP_RV1108) += \ diff --git a/arch/arm/dts/rk3566-radxa-cm3-io.dts b/arch/arm/dts/rk3566-radxa-cm3-io.dts new file mode 100644 index 0000000000..d89d5263cb --- /dev/null +++ b/arch/arm/dts/rk3566-radxa-cm3-io.dts @@ -0,0 +1,272 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Radxa Limited + * Copyright (c) 2022 Amarula Solutions(India) + */ + +/dts-v1/; +#include +#include "rk3566.dtsi" +#include "rk3566-radxa-cm3.dtsi" + +/ { + model = "Radxa Compute Module 3(CM3) IO Board"; + compatible = "radxa,cm3-io", "radxa,cm3", "rockchip,rk3566"; + + aliases { + mmc1 = &sdmmc0; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac1_clkin: external-gmac1-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac1_clkin"; + #clock-cells = <0>; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-1 { + gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_LOW>; + color = ; + function = LED_FUNCTION_ACTIVITY; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&pi_nled_activity>; + }; + }; + + vcc5v0_usb30: vcc5v0-usb30-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb30"; + enable-active-high; + gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb30_en_h>; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_sys>; + }; + + vcca1v8_image: vcca1v8-image-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcca1v8_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_p>; + }; + + vdda0v9_image: vdda0v9-image-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcca0v9_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vdda_0v9>; + }; +}; + +&combphy1 { + status = "okay"; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "input"; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m0_miim + &gmac1m0_tx_bus2 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk + &gmac1m0_rgmii_bus + &gmac1m0_clkinout>; + snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + tx_delay = <0x46>; + rx_delay = <0x2e>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@0 { + compatible="ethernet-phy-ieee802.3-c22"; + reg= <0x0>; + }; +}; + +&pinctrl { + gmac1 { + gmac1m0_miim: gmac1m0-miim { + rockchip,pins = + /* gmac1_mdcm0 */ + <3 RK_PC4 3 &pcfg_pull_none_drv_level_15>, + /* gmac1_mdiom0 */ + <3 RK_PC5 3 &pcfg_pull_none_drv_level_15>; + }; + + gmac1m0_rx_bus2: gmac1m0-rx-bus2 { + rockchip,pins = + /* gmac1_rxd0m0 */ + <3 RK_PB1 3 &pcfg_pull_none_drv_level_15>, + /* gmac1_rxd1m0 */ + <3 RK_PB2 3 &pcfg_pull_none_drv_level_15>, + /* gmac1_rxdvcrsm0 */ + <3 RK_PB3 3 &pcfg_pull_none_drv_level_15>; + }; + + gmac1m0_tx_bus2: gmac1m0-tx-bus2 { + rockchip,pins = + /* gmac1_txd0m0 */ + <3 RK_PB5 3 &pcfg_pull_none_drv_level_15>, + /* gmac1_txd1m0 */ + <3 RK_PB6 3 &pcfg_pull_none_drv_level_15>, + /* gmac1_txenm0 */ + <3 RK_PB7 3 &pcfg_pull_none_drv_level_15>; + }; + + gmac1m0_rgmii_clk: gmac1m0-rgmii-clk { + rockchip,pins = + /* gmac1_rxclkm0 */ + <3 RK_PA7 3 &pcfg_pull_none_drv_level_15>, + /* gmac1_txclkm0 */ + <3 RK_PA6 3 &pcfg_pull_none_drv_level_15>; + }; + + gmac1m0_rgmii_bus: gmac1m0-rgmii-bus { + rockchip,pins = + /* gmac1_rxd2m0 */ + <3 RK_PA4 3 &pcfg_pull_none_drv_level_15>, + /* gmac1_rxd3m0 */ + <3 RK_PA5 3 &pcfg_pull_none_drv_level_15>, + /* gmac1_txd2m0 */ + <3 RK_PA2 3 &pcfg_pull_none_drv_level_15>, + /* gmac1_txd3m0 */ + <3 RK_PA3 3 &pcfg_pull_none_drv_level_15>; + }; + + gmac1m0_clkinout: gmac1m0-clkinout { + rockchip,pins = + /* gmac1_mclkinoutm0 */ + <3 RK_PC0 3 &pcfg_pull_none_drv_level_15>; + }; + }; + + leds { + pi_nled_activity: pi-nled-activity { + rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdcard { + sdmmc_pwren: sdmmc-pwren { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_usb30_en_h: vcc5v0-host-en-h { + rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc0 { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_pwren>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb30>; + status = "okay"; +}; + +&usb2phy1_host { + status = "okay"; +}; + +&usb2phy1_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; From patchwork Fri Feb 17 11:58:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 2720 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pl1-f199.google.com (mail-pl1-f199.google.com [209.85.214.199]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 39E773F07F for ; Fri, 17 Feb 2023 12:59:11 +0100 (CET) Received: by mail-pl1-f199.google.com with SMTP id n1-20020a170902f60100b0019a68e484e1sf639251plg.14 for ; Fri, 17 Feb 2023 03:59:11 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1676635150; cv=pass; d=google.com; s=arc-20160816; b=xEVLCnH/+FSAcoxgoSZw1dndxiLvJuBDIZXFbxYwEZp7FMDz693Xt095z4W8yySi3M 2X2aQ9l36UcvLZJ15gcAblOWrKo5gYn/v2xz7tpCL8JLif9BXoXb8MQZfcdcTKHtTxcM vpOGl7zol19de9gXd7SlKSZ4w8vZ9zMjyyaNiEs59A08S+3FTmq11Bk9Mk8Km0w0YKwM elBr95WDTVqHTKPIutuTA8FMWzi+u0MRa6ksf7kjXHE/raX/BNBXxb0eqZabXDjUVvT1 M8etOr+5A4mK9N+9XkHHrZt/5SEU3AlxEIc5yRH6yGN/ovd5e/0m8Q30otwxqt7NEC5n nVNg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=8a+lF8Xrx9nlTpO3BU+LzsL9pgGxdV8zdFWLZgdCyLY=; b=kbdo+HXCzE+7bly9xU50hWhls75TQObERK1gHIaYZOy95bEYUABBfLg3XaCT+G+Qj7 i4O10jh7Nu14C/TtDmYsS85wvOtkQf4dmogeoqwxGAyDt/WOOLU7XT1qRokskU6wV8Vn ODnHy1INTXQX7XA29SHos6bt2vyLQw47NSgGi4OEK4vZI6YYdKZX38Edx1pPIG9AVd7I J+eQjDntlLBvpVxzNOxAX6+pfRZMTpG5Bg9ty+VFM2FfcYTKqclFP0uJeZ1WS9SNu+F9 EdRXXo68OvlG0V8kxjRlMthc4BgZ+oYiIr051gwJbt+TytGeDUoJ/mMGqknWCsfF1pEm uNtw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=VwuEyZx6; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date:message-id:reply-to; bh=8a+lF8Xrx9nlTpO3BU+LzsL9pgGxdV8zdFWLZgdCyLY=; b=RVq8LD2GL66yPUV5EFyIJpcdHmXQt/JfqaKWUF4tldw6t35y7xWEiqjR6/ypyWDUMC KPod2B8Rp/4QklhZaaw/fYnBKIAaVmorMn5KacKvxKlP2FU4CRRfNGzkLMSgu3K0XIA4 hnMiNuWYuQHz4wwGmMxAiq4zjzaGT7d/zO1CU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=8a+lF8Xrx9nlTpO3BU+LzsL9pgGxdV8zdFWLZgdCyLY=; b=khsEMPVgi8VX6Q0Ao9d6zdFyv4oMJss/tmWyPU2aI5H0WqTjKejC2ZV1MTgsmEwW+6 UNhi8wMkegyX9MFBZS+gMvCrbYzG9LR2ugBapjXjQwNJ4ZZO4MsYoLF8LQdKqchNrdUL xRUL2Jrdy8KMXWYyjZ2nXE5UWCmuoLKoTgODNr53287sQ53nVlclAlCDSppPivdvQTag 0yTTFkxrXPA3MUe9tu5Ndgv/Mn+K1AvWIRC+MmpwFNCpCXMYhXST8giAuGEoEDdt5NE1 eh1UvE1RbxnsO8dnpjU+JomTPLBLv7p1PEmc5lG8d2QRXsv9OGJyUaGN3nUK7ViwnE6p o9Ng== X-Gm-Message-State: AO0yUKVkAGBh5RzxVYXn2766zxWYsk/80EW/BsVDgmzfJTlKN4fAante sVn+CUtDMl85jUpyT5NuNSk7m8E/fniuOg== X-Google-Smtp-Source: AK7set8HP4wqmZatLPLVctRl/fwvyoFD7l6LqMPHHHjQvG1Ras0tmlE+qxxglLPuYwBdW1A5TPoCNw== X-Received: by 2002:a17:90b:4d8c:b0:230:87d0:6b with SMTP id oj12-20020a17090b4d8c00b0023087d0006bmr1579233pjb.11.1676635149927; Fri, 17 Feb 2023 03:59:09 -0800 (PST) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:90a:fcb:b0:234:a618:558a with SMTP id 69-20020a17090a0fcb00b00234a618558als1075442pjz.1.-pod-control-gmail; Fri, 17 Feb 2023 03:59:09 -0800 (PST) X-Received: by 2002:a17:902:d4d1:b0:19b:dbf7:f9e4 with SMTP id o17-20020a170902d4d100b0019bdbf7f9e4mr2816860plg.29.1676635149059; Fri, 17 Feb 2023 03:59:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676635149; cv=none; d=google.com; s=arc-20160816; b=wFJHxJ6NV3JnZ4uAEGIwbSt8TKrrcuLHIPJihkFSp4xPy9QHKdWdYN0c7Fl+zoHuv9 A5O3y7fdTW1Wzowik0WgRbTDNJdVeoxjMmyGPEFwySX1RqRB0pwrIfisG1YMkNwuQp61 LP+9LSh0OS2Eepd47lafEzQPSBBRogeQaYKXnfwL8rMoFlS7vgEJPtnCs4tMycUmI+I9 P5/yHW9/EDoWNWXqJA7f2PuBLKFod0ncpUek3h+yUZvrUa0gH3mDrO0vE48fLGcR/mMs nvdE+5QJ/EareuLaXjR5+8iQ6NP93DlKQ9WxmXwQzIh1Da4P0WyluDF4nIQ6JaLUr9Bi 0PLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=ZwMTkLEhcBKnw+uY94vxhHExZJgKmGaCBa+XGRD0uQ0=; b=s56qbtdoPnwiJJdSEDm4V+ZwG+TUsMcdqmVSUTOwV/MFGrNaNySNy9OH+xuI3VJgWK R1hf5pJU6Aphw6i/wgXZ//Q6EUNqXr6LOnlf454Da8bNt17gpSpBnfN2xedE2akvQfmP ooprHshdM2Kun/h1/pXqTlPUay893FefA4NRMQcglCX1zg1jN2RdmbJgNSjiI/1RqgAZ mctyxeSmawj0f4+F+AQmczJaq/IqG92rPrlY9g8yMhA+Majqn03w3GHnjXsqgSrWRkG+ L/ZOXol+4wxGdORic4VJ99OqFg7RisBQ31SZdzyNabl0BUFeROBc0rNYfZ5Hq1aS7sbv zQkQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=VwuEyZx6; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id a7-20020a170902ecc700b0019482352535sor2177287plh.1.2023.02.17.03.59.09 for (Google Transport Security); Fri, 17 Feb 2023 03:59:09 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:902:f682:b0:199:2ee:6238 with SMTP id l2-20020a170902f68200b0019902ee6238mr795988plg.16.1676635148788; Fri, 17 Feb 2023 03:59:08 -0800 (PST) Received: from localhost.localdomain ([183.83.141.79]) by smtp.gmail.com with ESMTPSA id ik15-20020a170902ab0f00b001991d6c6c64sm2989418plb.185.2023.02.17.03.59.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Feb 2023 03:59:07 -0800 (PST) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v4 05/12] board: rockchip: Add Radxa Compute Module 3 IO Board Date: Fri, 17 Feb 2023 17:28:38 +0530 Message-Id: <20230217115845.75303-6-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230217115845.75303-1-jagan@amarulasolutions.com> References: <20230217115845.75303-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=VwuEyZx6; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Radxa Compute Module 3(CM3) IO board an application board from Radxa and is compatible with Raspberry Pi CM4 IO form factor. Radxa CM3 needs to mount on top of this IO board in order to create complete Radxa CM3 IO board platform. Add support for Radxa CM3 IO Board defconfig and -u-boot.dtsi Reviewed-by: Kever Yang Signed-off-by: Jagan Teki --- arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi | 18 ++++++ board/rockchip/evb_rk3568/MAINTAINERS | 5 ++ configs/radxa-cm3-io-rk3566_defconfig | 66 ++++++++++++++++++++ 3 files changed, 89 insertions(+) create mode 100644 arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi create mode 100644 configs/radxa-cm3-io-rk3566_defconfig diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi new file mode 100644 index 0000000000..3c925161d4 --- /dev/null +++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2021 Rockchip Electronics Co., Ltd + */ + +#include "rk356x-u-boot.dtsi" + +/ { + chosen { + stdout-path = &uart2; + }; +}; + +&uart2 { + clock-frequency = <24000000>; + u-boot,dm-spl; + status = "okay"; +}; diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS index b6ea498d2b..88d11f05c2 100644 --- a/board/rockchip/evb_rk3568/MAINTAINERS +++ b/board/rockchip/evb_rk3568/MAINTAINERS @@ -4,3 +4,8 @@ S: Maintained F: board/rockchip/evb_rk3568 F: include/configs/evb_rk3568.h F: configs/evb-rk3568_defconfig + +RADXA-CM3 +M: Jagan Teki +S: Maintained +F: configs/radxa-cm3-io-rk3566_defconfig diff --git a/configs/radxa-cm3-io-rk3566_defconfig b/configs/radxa-cm3-io-rk3566_defconfig new file mode 100644 index 0000000000..a79d9b25e3 --- /dev/null +++ b/configs/radxa-cm3-io-rk3566_defconfig @@ -0,0 +1,66 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3566-radxa-cm3-io" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_EVB_RK3568=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-radxa-cm3-io.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_REGULATOR_PWM=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_ERRNO_STR=y From patchwork Fri Feb 17 11:58:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 2721 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pf1-f197.google.com (mail-pf1-f197.google.com [209.85.210.197]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 5D1CB3F07F for ; Fri, 17 Feb 2023 12:59:14 +0100 (CET) Received: by mail-pf1-f197.google.com with SMTP id c6-20020a62e806000000b005a8ba9365c1sf204211pfi.18 for ; Fri, 17 Feb 2023 03:59:14 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1676635153; cv=pass; d=google.com; s=arc-20160816; b=DwBF91NZ7om79LGl14oPoo/kPSzSqcJAcuOTIvhM6lL5x1KJbjXWntSYbDgWfXm3da U3Mh01Q1a/QHQ+s0TE2P6N9egose05Gvdck4zWqn58BI4vu0O19myXaDrmEjfs5M9Uf7 gudaL+/6gx+r1Tm3nDrUjxyurb0gdcw9QNlpT14i7Wzu9qof5SZIlyT4OkTNwRUiEeTL zk5vOb6fhr3asHARLRX+yQz0LA9UPJFx4N6ihOZLjz0lh5OmH41jR54UbRuafEsaXpKo JOUr1iibhsPBsQ4QKidVcifuDmvVp0bcF8oWH/VLeh/OOOvlqrLHHRCeEzurYtGbqn6Z cIpQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=GZRMRFAKWeBZX2m6v3BufIA6Cl9U2MIk3RQoZV3/wd0=; b=BzqXraKCAl4wa8eLMPvNhMN9uD3+yYxHw+7JlBv8m+7rqL4DLwL12gFhHjQCYAXimK COqdtnX3ftBhBOvvFj0+K4ZCVYFNiPdjET26ZFzYkwxkcIWvGxUZQ+wWASDu0qay1KG/ WOMQFdokhE4YMDu9ZOHPZ8tEZV2rar1w/x7fmY6kGsdH9oF2ye49l1Qkqu4xrevPk3T/ KCLx6hjq10Ai722e8XaFuwwdC/DJoieo+1EHOB9164IlphtVQ74r1atuW0gczq/qFiBA MnCvRgkZ34hbCk0rKNMDJhnA0eCzo5Dk7xXFCVMgFuf/KFL8QOLoTq6GaIvztJKL1Bk4 lJzQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=hOf3UpMl; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date:message-id:reply-to; bh=GZRMRFAKWeBZX2m6v3BufIA6Cl9U2MIk3RQoZV3/wd0=; b=OgBwyoE3Gn3HfXabocKOefvcpJntSJNcRE0E79uQkG7E5VXwe+NsYH75qIgCClkf6X Fpw2+pdcD/Ubw/+KYzIBrth/Ty0gSuPcWAQoH5kyLU8EN7rgFvdmmQob1bco55uK/dMQ gD38+wU7+RWGwVEdvTVE5Xm9J3un1QGotQATE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=GZRMRFAKWeBZX2m6v3BufIA6Cl9U2MIk3RQoZV3/wd0=; b=yTqdeYVT3UiuRVi1INbBV7/NGpqohawAajB+7JTuyKdLoAKV9KnG4amIitAEjtTVjl +GOeb4MXZ99p+L/oowrWWKLbxIuTbNZNta7AsKmivohzQ6ENcfuE4TPlXp531WLvt9JW nS2fNV9TkF8GqBxusk6o3IsqAe3cDtwMuWkWpOUZeQe1J09NTIlIpUrqYjKeh2Dv2Vby M97g/W1A0ix+4xhiNZOmMiU/97Q+yjZiouJBKS5eHyp9Wj2EklinoFVB7cLC6+MLSKw8 Q3/wRaVJSB8HtXbno1I/VCYLrZPZDnkgb5ICJopLXff9ktNzpIQWo/X+GG79JpEtLXJq 42Ng== X-Gm-Message-State: AO0yUKUfkNfer3FIfTJyygOTSY01Pvo9wNw8dVuoXezgLfU3/uP7VIJk 98fZAB6rIDqpoaopi7Zv6lXRtyEy X-Google-Smtp-Source: AK7set88qao1zrfgUCiDFu+muy0bjsqUbmd5Vv9dOF2IzwWhLQP8iM8iqSZrGF/jAlJGGGtuDhpNXw== X-Received: by 2002:a05:6a00:98a:b0:5a8:5c7d:e4db with SMTP id u10-20020a056a00098a00b005a85c7de4dbmr413688pfg.3.1676635153121; Fri, 17 Feb 2023 03:59:13 -0800 (PST) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:90a:e54a:b0:233:e65f:ffb9 with SMTP id ei10-20020a17090ae54a00b00233e65fffb9ls1457208pjb.3.-pod-canary-gmail; Fri, 17 Feb 2023 03:59:12 -0800 (PST) X-Received: by 2002:a17:902:ce82:b0:19a:59a5:e88e with SMTP id f2-20020a170902ce8200b0019a59a5e88emr10630368plg.59.1676635152235; Fri, 17 Feb 2023 03:59:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676635152; cv=none; d=google.com; s=arc-20160816; b=0G6WIaizk3vvDxDQHJlHlujn3WUaqh9DSrw0AeBlii6OprUNAk7bJngOOfIeoBCEYU qyKShm6EXoPUnvnjz0AJqKsFEaVZ4aIWvYohgXjnx2cog2GG1QfxzSuxMo6a2N6VGlj0 mKRMfETzU9lGUS3HDPyHoByWha6lZ9C+FD7ArKMvYJQeg5kaBci44vmYMbRYKMZKwS2f XytMB5dU7nBB9721HPlKJwijQUqrFUDrOxRD4XinwNd7ZVoqppXNLnUsK+zwyFMhGO5I 8Xk1DRqpQy5KOU1Zd+zaTc8BaDpsqTpP53/ihtZndAis117KZzP9n2MdtjggetjX6ccI 012A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Vrxbb/3kk6uouYGyo1ZvlY/hJbFYigXlDsHcgLMFg/k=; b=fuj/Pip4cE8LqahbqVF4DQFnmwKON8SP4xOzzEwrga5mMD455AGlehgcnG1KXMBfb6 cxzxFuAgTfShWDLPd2Kwzzs50JV2zUrsVzpFJhE0YWh848deFcH93wsCe0tRUnCQSEp1 T5SsjWXQv33qfAk5C051/6SOyPrmB4mW7aUBOcvfiTwYS8Q4x4SeRl/DRWDIMEztKq9B lauejVKAGRWrn1O3b+NJWoaA8zeh7ylB6pLufm4Hi6HrdGeNs/KSUEmgqr9rgach9kca NpNF+FSgxgmm49Ih5jeToeXdkE8JTMmqzmsoyMtEA6KNV1IjmKiwH3IKr6/gKzBJgkc4 dEWw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=hOf3UpMl; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id jh19-20020a170903329300b0019ac7319ee7sor2260607plb.57.2023.02.17.03.59.12 for (Google Transport Security); Fri, 17 Feb 2023 03:59:12 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:902:ea0c:b0:199:2e77:fe56 with SMTP id s12-20020a170902ea0c00b001992e77fe56mr11911675plg.52.1676635151917; Fri, 17 Feb 2023 03:59:11 -0800 (PST) Received: from localhost.localdomain ([183.83.141.79]) by smtp.gmail.com with ESMTPSA id ik15-20020a170902ab0f00b001991d6c6c64sm2989418plb.185.2023.02.17.03.59.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Feb 2023 03:59:11 -0800 (PST) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com, Jagan Teki , Manoj Sai Subject: [PATCH v4 06/12] phy: rockchip: inno-usb2: Add support #address_cells = 2 Date: Fri, 17 Feb 2023 17:28:39 +0530 Message-Id: <20230217115845.75303-7-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230217115845.75303-1-jagan@amarulasolutions.com> References: <20230217115845.75303-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=hOf3UpMl; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , New Rockchip devices have the usb phy nodes as standalone devices. These nodes have register nodes with #address_cells = 2, but only use 32 bit addresses. Adjust the driver to check if the returned address is "0", and adjust the index in that case. Derived and adjusted the similar change from linux-next with below commit <9c19c531dc98> ("phy: phy-rockchip-inno-usb2: support #address_cells = 2") Co-developed-by: Manoj Sai Signed-off-by: Manoj Sai Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index b32a498ea7..a01148db22 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -179,12 +179,21 @@ static int rockchip_usb2phy_probe(struct udevice *dev) if (IS_ERR(priv->reg_base)) return PTR_ERR(priv->reg_base); - ret = ofnode_read_u32(dev_ofnode(dev), "reg", ®); + ret = ofnode_read_u32_index(dev_ofnode(dev), "reg", 0, ®); if (ret) { dev_err(dev, "failed to read reg property (ret = %d)\n", ret); return ret; } + /* support address_cells=2 */ + if (reg == 0) { + if (ofnode_read_u32_index(dev_ofnode(dev), "reg", 1, ®)) { + dev_err(dev, "%s must have reg[1]\n", + ofnode_get_name(dev_ofnode(dev))); + return -EINVAL; + } + } + phy_cfgs = (const struct rockchip_usb2phy_cfg *) dev_get_driver_data(dev); if (!phy_cfgs) From patchwork Fri Feb 17 11:58:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 2722 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pj1-f72.google.com (mail-pj1-f72.google.com [209.85.216.72]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id D519A3F07F for ; Fri, 17 Feb 2023 12:59:17 +0100 (CET) Received: by mail-pj1-f72.google.com with SMTP id s15-20020a17090a1c0f00b0022646263abfsf345936pjs.6 for ; Fri, 17 Feb 2023 03:59:17 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1676635156; cv=pass; d=google.com; s=arc-20160816; b=hacAjnZ+bARHONvpDx5wm90f2XiKKerA5UNpTf2axzvzu2IREidax+4QSuewRHNv7z gUDpqmEKFo8kB6is/BFrVER6EMSJKrKRuGWNP59Gz5lILKZhoVR5TKYYpqsv4swGKDM5 zCrRBLcCrJjZ4aas7NwakOQPFdTb0Rh+hTz+59NcoKIqVV97f2q6of7FdEqNq94W4t3O tIOli3Ovupj7ETwSBQYQIoVplXYEC6KpAlCtTPzwX+aQr2SCOyKD1/p3DyuvwygrfOv/ 1ON5bM/sziw1IQS7eQVa+O/xiD13s78F7snndvlAFJQzxRCFFJx8ydcnlrQfsvO5kaKR rsxw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=IkiRE8lDa9ci0l6zU56cZdtxIE8tkAXvj/jIvQP2bzI=; b=e0fTZjGM8RzBSOsVgQWGRCxKKGAMxiBFZEmQKvWHJ4oXk43fX9yLWiOIDk2JpmaL9t 1DcxFgMd9jHLLK6RJJhLdyMaCYltg2ienbRziWm/OHkbXPXZUFEcYWWdRaBH0RjYKjzq 8rO0mL5HnrN+iHq9FjCDNGJEtxdJy92sJLnDcnnvzQHkH4Hmsbia47MlEB3kbmon765p oc3t1bObepPPmuCB6eCL+x0sqUHYvvKcl9ZBg0aDjIbdTW9HKl8qdPZT9ePZKMQ4qEVu OJ9Bxw8EZJtNM8XYhbcnqmEFDs+VW+eDqRlMvels/pg1iaZXAXFRThRAjUgraeE6wKYL cQXQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=P4mvZHaf; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:content-transfer-encoding:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:from:to:cc:subject :date:message-id:reply-to; bh=IkiRE8lDa9ci0l6zU56cZdtxIE8tkAXvj/jIvQP2bzI=; b=UEfOIRNBI2pRgFzdh/xleQue7KXgNccdMWhxSfXKLRH801ny4xpvHllZak4uS6mB1h Bafx3m/iqkMDH04ij6bKr/gJsyABv/mbpkWMWAtL7rqyHZAlMZVkhEXZ12d+YzISUdr7 a4c8WVCq1Dm96nos3rN0HoxIs3rGq5QB83G/E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IkiRE8lDa9ci0l6zU56cZdtxIE8tkAXvj/jIvQP2bzI=; b=044wZvd++gb9SThT+GGriNCsbzR5RFTP1M9BquGMIZuOOXZErdCR13e2AP3QE7uDlP 7zv4eP93ITTVsG5bZXUVfqJPhDGn+XOgkCwFLLEB1mIvb5QuDeJRJRs8y3L/6PkAfgv0 eR5rDqL1Em10KsKgt3hiPaXHVzk80S/WzKkf6GSCIwqkLndi6HFBkWrEFRqAHzRWceDd TksknI5PbucjadduDif53p0RUrTLDEy02n5Fvpvd1p7svF/Q+i2SqmbRl4Q8ruh5CqMA 2PNeUMHql7WUGbujSfg1VbyUtB4AUEjLusfX+R4FXfubyULgrI+XP3dz98bERAE4yPdo j7XA== X-Gm-Message-State: AO0yUKUELP4Sswaz5AS7YXBMGF4N0xb/WKJrbIxW35LVOjtE0B7REqUw fNPjK1BIuoKcabwKv6qDOTiH1xOWAM3UaA== X-Google-Smtp-Source: AK7set8k2HQJSfrPPq1z81jxSic9TQm/uN/cfkjwKUC/E4ynI56toXqChuzH88jWhjz7fSTyMq+1vA== X-Received: by 2002:a17:90b:42:b0:233:c7d1:384f with SMTP id d2-20020a17090b004200b00233c7d1384fmr1447260pjt.48.1676635156679; Fri, 17 Feb 2023 03:59:16 -0800 (PST) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:902:d48e:b0:19c:2b1c:4d75 with SMTP id c14-20020a170902d48e00b0019c2b1c4d75ls95794plg.0.-pod-prod-gmail; Fri, 17 Feb 2023 03:59:16 -0800 (PST) X-Received: by 2002:a17:902:d505:b0:198:e393:dbf5 with SMTP id b5-20020a170902d50500b00198e393dbf5mr1304479plg.22.1676635155836; Fri, 17 Feb 2023 03:59:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676635155; cv=none; d=google.com; s=arc-20160816; b=HAJZymTkzkCL3asrb/LfmzCxcICd56nAYqeztYd5Xlz/lpezqw4+dHoG14l2GO7u6H mGE5zWBmKkBA2a9cpEBwwST7n2x7jT60PLGVfv32d/YitgrMQsN6XbXJo60E/V+oetGh ZpwXXZ90B5J4CjqFudTcQpalQbAqbGAfdy+nnZfn1pITa7bIeuktSGOgNX/jNjHlU1nz APBSjuJHwp1YesJ3ojlhhn1maS5TLu6Ht+kc1MljWsAVCkuIXkB0/xL9ml0Vf40Zw4b5 XEeO02dwVmfeo5Zwv0V49JFFPWY5AsNmopRGrmlIDVW7aNugreFGCfxjgczGNhYDFlgO IkYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=UpJFPAIkn3DPnokZnwrl0Fhymj4X1XruEP+JGoJNLcw=; b=0eESuMIWTs5Av+19eZ1kDucZTHg2YQZWW/MLbSI6+1KoW8N26OMXsBNMs3p+6OSooy 4dkS/65dNNWncANldvaGIHCXz+U3HKYyPU3HsdLQUA0lMzBLp4cW/LVU4YDEm7WmpW5k WvDh9UPUyV03PMLQg+9/tvOYtJKDGBDjmJxQ4lh7aaryC/lffIDFwDDNRTOmoknbYGvk e9qZjYVMeDdB8wkcN68W+JWS2IZxtv76Yt/m0F5rk4UzGh3SMkYe0drOqF6pSYh1DxsG tLyqXi7YCgHi9NNyKWCjIjg4mT1jK0AGms2QWw3CbodiZlZsOabmJkU57m5IdwKKHMQD TI9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=P4mvZHaf; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id q9-20020a170902bd8900b00195f2461669sor2144226pls.104.2023.02.17.03.59.15 for (Google Transport Security); Fri, 17 Feb 2023 03:59:15 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:903:230f:b0:19a:9890:eac3 with SMTP id d15-20020a170903230f00b0019a9890eac3mr802650plh.39.1676635155144; Fri, 17 Feb 2023 03:59:15 -0800 (PST) Received: from localhost.localdomain ([183.83.141.79]) by smtp.gmail.com with ESMTPSA id ik15-20020a170902ab0f00b001991d6c6c64sm2989418plb.185.2023.02.17.03.59.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Feb 2023 03:59:14 -0800 (PST) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com, Manoj Sai , Ren Jianing , Jagan Teki Subject: [PATCH v4 07/12] phy: rockchip-inno-usb2: Add USB2 PHY for rk3568 Date: Fri, 17 Feb 2023 17:28:40 +0530 Message-Id: <20230217115845.75303-8-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230217115845.75303-1-jagan@amarulasolutions.com> References: <20230217115845.75303-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=P4mvZHaf; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Manoj Sai RK3568 has two USB 2.0 PHYs, and each PHY has two ports, the OTG port of PHY0 support OTG mode with charging detection function, they are similar to previous Rockchip SoCs. However, there are three different designs for RK3568 USB 2.0 PHY. 1. RK3568 uses independent USB GRF module for each USB 2.0 PHY. 2. RK3568 accesses the registers of USB 2.0 PHY IP directly by APB. 3. The two ports of USB 2.0 PHY share one interrupt. This patch only PHY1 with necessary attributes required to function USBPHY1 on U-Boot. Co-developed-by: Ren Jianing Signed-off-by: Ren Jianing Co-developed-by: Jagan Teki Signed-off-by: Jagan Teki Signed-off-by: Manoj Sai Reviewed-by: Kever Yang --- drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index a01148db22..55e1dbcfef 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -298,11 +298,65 @@ static const struct rockchip_usb2phy_cfg rk3399_usb2phy_cfgs[] = { { /* sentinel */ } }; +static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { + { + .reg = 0xfe8a0000, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x0000, 8, 0, 0x052, 0x1d1 }, + .bvalid_det_en = { 0x0080, 2, 2, 0, 1 }, + .bvalid_det_st = { 0x0084, 2, 2, 0, 1 }, + .bvalid_det_clr = { 0x0088, 2, 2, 0, 1 }, + .ls_det_en = { 0x0080, 0, 0, 0, 1 }, + .ls_det_st = { 0x0084, 0, 0, 0, 1 }, + .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, + .utmi_avalid = { 0x00c0, 10, 10, 0, 1 }, + .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 }, + .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, + .ls_det_en = { 0x0080, 1, 1, 0, 1 }, + .ls_det_st = { 0x0084, 1, 1, 0, 1 }, + .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, + .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, + .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } + } + }, + }, + { + .reg = 0xfe8b0000, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d1 }, + .ls_det_en = { 0x0080, 0, 0, 0, 1 }, + .ls_det_st = { 0x0084, 0, 0, 0, 1 }, + .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, + .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, + .utmi_hstdet = { 0x00c0, 7, 7, 0, 1 } + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, + .ls_det_en = { 0x0080, 1, 1, 0, 1 }, + .ls_det_st = { 0x0084, 1, 1, 0, 1 }, + .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, + .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, + .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } + } + }, + }, + { /* sentinel */ } +}; + static const struct udevice_id rockchip_usb2phy_ids[] = { { .compatible = "rockchip,rk3399-usb2phy", .data = (ulong)&rk3399_usb2phy_cfgs, }, + { + .compatible = "rockchip,rk3568-usb2phy", + .data = (ulong)&rk3568_phy_cfgs, + }, { /* sentinel */ } }; From patchwork Fri Feb 17 11:58:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 2723 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pf1-f198.google.com (mail-pf1-f198.google.com [209.85.210.198]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 080AC3F07F for ; Fri, 17 Feb 2023 12:59:21 +0100 (CET) Received: by mail-pf1-f198.google.com with SMTP id a5-20020a62bd05000000b005a9d0e66a7asf1375021pff.5 for ; Fri, 17 Feb 2023 03:59:20 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1676635159; cv=pass; d=google.com; s=arc-20160816; b=TMW3tsjbSPSuGNPsmV0IxaLDSZuPinBljp81EiLaqO+4kofwXMPePecprIBNAS6+7n IZ2Q7kkM6SbAEIkHHE6YpJ54eFEpmTMuRgjCDsOu3V6xNy2u6DCa8wUuvZHa1sxDBigd ea5hrIPL4gHvW639jo0Kn3aGj3tECOx/wp2UBv9es4ON+njSCAV1qvQB0s2tE3PDl5a7 yiF0o1axIEWpXAKtWL8nQpGeWANb6eSZK+jxakzGTS+jZYWuWGPoz2zrXnW9ERivNlO2 mg0f3fB2D88u2PumZq1vzX50JCbhOBD+btihQlChnxaq2yCdA8byqpf7sHx+Q3k4FfP8 0AJA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=my156gAqobEjM/EF9ab2Zwu3M1ALfXuAXVV1jrLO7Io=; b=s92aFwrRokJppNOFIs0Zv95uIR5PoBC3ZVgHu8cwe7DFuglSzSPsWNYRtrm2/9R7tX B6bRQF2o7/gA0sSnUrLXb9PKa92Merjf0vtqgv+nfISkFzJMvOpVHqyszIpXaQUijly9 C5bPBZ2k/1vz69E8305ql3Etxv/qKhE1mJd8QdTExXcXEgl8QDC2fF7bH8LFczk/Kw+w WuiqfCIqRQDXv8tHujSisJ4jcirirkTOQgNSmUb0xMZ8cNbZs7hMAO0uyNymSQvcbWZg RBK//g5hQ2WBlEk6Xh7iIW3bCBdF+yXOPRAOprkrCgkinIyCJ7QJbvFfxVxNCGV+xRzC UuMQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=P8Slxggs; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date:message-id:reply-to; bh=my156gAqobEjM/EF9ab2Zwu3M1ALfXuAXVV1jrLO7Io=; b=Tbe2e3EWni6wT+UbJD+jPFcpkmru9o2klasUctXTiEApX2ojS/CSor2HFhyM4q7O+i XPqYCDxH4dkqt3W5zI+3P9foK7she+yOPBvfOClo+Eix/ClkmbJfmYr5MVhXauhKPx60 0/9C6yIZV39U4bSJF3vRNWzMAwnESPBScvEso= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=my156gAqobEjM/EF9ab2Zwu3M1ALfXuAXVV1jrLO7Io=; b=LJJO+bBTCESZnAW5L7/+J6lLn3DTkavMa6if8M2v6VoJoM+lucPn/l9lT83gaspJ7e S9lBADY8g4WMWAI3zoVIpnBVKoJt+siv8OuEWzkoKvJPrFTOGjf1GkDjevtiEJZvsQuv 0Xmkzm6XNH2UPqDYExhWvuEJLPTWO0/31YugrHVinnH39sauoammnTRZqeECiC8Jgl1x Di1xfTnybMXQbnhg87Uwglj14BXyM5b2mpjkzSmh2KHsMaqEEacry8eI5TjqCtvYCueX s41wtvzkvZG/xkUTxCa0+H+jt21U80Sypu5B3RPFwosQxumOyzuZ0tc6GS8b1WWRo0t4 tFyQ== X-Gm-Message-State: AO0yUKWjDJPczKQW5yLhJ74Gv4orR0wSeJ31WjLvokB7evQRCol8tXjv JgtBcEEIkEKU9jJ310B+E2mVTN8Ef91RPA== X-Google-Smtp-Source: AK7set85fkqxQFEDKZ7FVZRcsEiwEwm7JBe2hhcyoSEL+j96cFupqP7jKWwcavg1eGDxu3DOFdT0kg== X-Received: by 2002:a62:cd8a:0:b0:5a9:c22e:7764 with SMTP id o132-20020a62cd8a000000b005a9c22e7764mr239533pfg.5.1676635159740; Fri, 17 Feb 2023 03:59:19 -0800 (PST) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:902:e748:b0:19a:a6bf:cc9c with SMTP id p8-20020a170902e74800b0019aa6bfcc9cls1683052plf.4.-pod-prod-gmail; Fri, 17 Feb 2023 03:59:19 -0800 (PST) X-Received: by 2002:a17:903:27c5:b0:196:11b1:101d with SMTP id km5-20020a17090327c500b0019611b1101dmr858414plb.28.1676635158773; Fri, 17 Feb 2023 03:59:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676635158; cv=none; d=google.com; s=arc-20160816; b=plOTE5lGQQU5qeyKXmy+pj294Iq/DDVsV0TfL9qhBQG7y9x1VLplhDDQGGqAMzzlcJ u81Lq+TnMQ2L8bICW4J7qg3qh8hHygVXfG8pGRJT9Zp0DuWwaRVCpIaoheE2CXOSauxa envAR0G4q3GQsTVmJ573cSLH/IU5JRZIRzveNKz2ob7/O+PK/vEbXkJ8mpmySxTJ/o3I yBbvBAME8X8jHqS/wcgIYICLXnyMFH9dO7VSBKsld4ewcU5gm2JePKSGCWSuHIq5gOSU og+BKaP/3GpjtspqGQKhuM3UhVu44NL42q+q8bUYxF5xAeaJbHkjhSPNa8M88fJo75BJ HT9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=69FACXlL1E/QUR5Pg0F/XW7mDfikQSvAQGOfvy5MdE0=; b=SHxJkCzgkc5gOx2AhHoiD7kGTXTpyqCgEeLVqTnE7x4axCvnI0DMVKoFMg8Rt/HiGC 3LRapibIkNp0BeffO0Ey1ezRiHaj0M1DXutuDzcr4+LY0foJ5HIuK9vQHdp+7d2k5zLi 6m5ySRAgkLrTNmjmY3Yyr9m5F2xbhWy9ekXyveueOJXlh8TSCQbrPTvZGnLMuWMphtE3 ue7VnnqQI1Yjerd8XdhIb0p1uAT3HOaFzjC82AraHsUOm12xOuR1XZRg7+t4zSfuvF22 3T6K4bc1qzhbxpP20U6hCLmZAEPseHf4JwmTCehNSIv5ORzrY/CainlSPD+V1oodvQG6 JuOQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=P8Slxggs; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id w21-20020a1709029a9500b0019ab8b84ba5sor2203161plp.50.2023.02.17.03.59.18 for (Google Transport Security); Fri, 17 Feb 2023 03:59:18 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:902:f68b:b0:19a:f02c:a062 with SMTP id l11-20020a170902f68b00b0019af02ca062mr6585713plg.2.1676635158336; Fri, 17 Feb 2023 03:59:18 -0800 (PST) Received: from localhost.localdomain ([183.83.141.79]) by smtp.gmail.com with ESMTPSA id ik15-20020a170902ab0f00b001991d6c6c64sm2989418plb.185.2023.02.17.03.59.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Feb 2023 03:59:17 -0800 (PST) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com, Jagan Teki , Manoj Sai , Yifeng Zhao Subject: [PATCH v4 08/12] drivers: phy: add naneng combphy for rk3568 Date: Fri, 17 Feb 2023 17:28:41 +0530 Message-Id: <20230217115845.75303-9-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230217115845.75303-1-jagan@amarulasolutions.com> References: <20230217115845.75303-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=P8Slxggs; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Jagan Teki RK3568 has three combo phys, and PCIe/USB3/SATA/QSGMII controllers share one pipe interface for each combo phy, here is the diagram of the complex connection. +----------------+ | | +------+ | USB3 OTG CTRL0 |---->| | | | | | +------------+ +----------------+ | PIPE | | | | MUX |---->| Combo PHY0 | +----------------+ | | | | | | | | +------------+ | SATA CTRL0 |---->| | | | +------+ +----------------+ +----------------+ | | +------+ | USB3 HOST CTRL1|---->| | | | | | +------------+ +----------------+ | PIPE | | | | MUX |---->| Combo PHY1 | +----------------+ | | | | | |---->| | +------------+ | SATA CTRL1 | -->| | | | | +------+ +----------------+ | | +----------------+ | | | | +------+ | QSGMII CTRL |---->| | | | | | +------------+ +----------------+ | PIPE | | | | MUX |---->| Combo PHY2 | +----------------+ | | | | | |---->| | +------------+ | SATA CTRL2 | -->| | | | | +------+ +----------------+ | | +----------------+ | | | | | PCIe2 1-Lane |--- | | +----------------+ Co-developed-by: Manoj Sai Signed-off-by: Manoj Sai Co-developed-by: Yifeng Zhao Signed-off-by: Yifeng Zhao Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- drivers/phy/rockchip/Kconfig | 7 + drivers/phy/rockchip/Makefile | 1 + .../rockchip/phy-rockchip-naneng-combphy.c | 441 ++++++++++++++++++ 3 files changed, 449 insertions(+) create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig index e477a6cd9e..1305763940 100644 --- a/drivers/phy/rockchip/Kconfig +++ b/drivers/phy/rockchip/Kconfig @@ -11,6 +11,13 @@ config PHY_ROCKCHIP_INNO_USB2 help Support for Rockchip USB2.0 PHY with Innosilicon IP block. +config PHY_ROCKCHIP_NANENG_COMBOPHY + bool "Support Rockchip NANENG combo PHY Driver" + depends on ARCH_ROCKCHIP + select PHY + help + Enable this to support the Rockchip NANENG combo PHY. + config PHY_ROCKCHIP_PCIE bool "Rockchip PCIe PHY Driver" depends on ARCH_ROCKCHIP diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile index f6ad3bf59a..a236877234 100644 --- a/drivers/phy/rockchip/Makefile +++ b/drivers/phy/rockchip/Makefile @@ -4,6 +4,7 @@ # obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o +obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY) += phy-rockchip-naneng-combphy.o obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c new file mode 100644 index 0000000000..78da5fe797 --- /dev/null +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -0,0 +1,441 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip USB3.0/PCIe Gen2/SATA/SGMII combphy driver + * + * Copyright (C) 2021 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define BIT_WRITEABLE_SHIFT 16 + +struct rockchip_combphy_priv; + +struct combphy_reg { + u16 offset; + u16 bitend; + u16 bitstart; + u16 disable; + u16 enable; +}; + +struct rockchip_combphy_grfcfg { + struct combphy_reg pcie_mode_set; + struct combphy_reg usb_mode_set; + struct combphy_reg sgmii_mode_set; + struct combphy_reg qsgmii_mode_set; + struct combphy_reg pipe_rxterm_set; + struct combphy_reg pipe_txelec_set; + struct combphy_reg pipe_txcomp_set; + struct combphy_reg pipe_clk_25m; + struct combphy_reg pipe_clk_100m; + struct combphy_reg pipe_phymode_sel; + struct combphy_reg pipe_rate_sel; + struct combphy_reg pipe_rxterm_sel; + struct combphy_reg pipe_txelec_sel; + struct combphy_reg pipe_txcomp_sel; + struct combphy_reg pipe_clk_ext; + struct combphy_reg pipe_sel_usb; + struct combphy_reg pipe_sel_qsgmii; + struct combphy_reg pipe_phy_status; + struct combphy_reg con0_for_pcie; + struct combphy_reg con1_for_pcie; + struct combphy_reg con2_for_pcie; + struct combphy_reg con3_for_pcie; + struct combphy_reg con0_for_sata; + struct combphy_reg con1_for_sata; + struct combphy_reg con2_for_sata; + struct combphy_reg con3_for_sata; + struct combphy_reg pipe_con0_for_sata; + struct combphy_reg pipe_sgmii_mac_sel; + struct combphy_reg pipe_xpcs_phy_ready; + struct combphy_reg u3otg0_port_en; + struct combphy_reg u3otg1_port_en; +}; + +struct rockchip_combphy_cfg { + const struct rockchip_combphy_grfcfg *grfcfg; + int (*combphy_cfg)(struct rockchip_combphy_priv *priv); +}; + +struct rockchip_combphy_priv { + u32 mode; + void __iomem *mmio; + struct udevice *dev; + struct regmap *pipe_grf; + struct regmap *phy_grf; + struct phy *phy; + struct reset_ctl phy_rst; + struct clk ref_clk; + const struct rockchip_combphy_cfg *cfg; +}; + +static int param_write(struct regmap *base, + const struct combphy_reg *reg, bool en) +{ + u32 val, mask, tmp; + + tmp = en ? reg->enable : reg->disable; + mask = GENMASK(reg->bitend, reg->bitstart); + val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); + + return regmap_write(base, reg->offset, val); +} + +static int rockchip_combphy_pcie_init(struct rockchip_combphy_priv *priv) +{ + int ret = 0; + + if (priv->cfg->combphy_cfg) { + ret = priv->cfg->combphy_cfg(priv); + if (ret) { + dev_err(priv->dev, "failed to init phy for pcie\n"); + return ret; + } + } + + return ret; +} + +static int rockchip_combphy_usb3_init(struct rockchip_combphy_priv *priv) +{ + int ret = 0; + + if (priv->cfg->combphy_cfg) { + ret = priv->cfg->combphy_cfg(priv); + if (ret) { + dev_err(priv->dev, "failed to init phy for usb3\n"); + return ret; + } + } + + return ret; +} + +static int rockchip_combphy_sata_init(struct rockchip_combphy_priv *priv) +{ + int ret = 0; + + if (priv->cfg->combphy_cfg) { + ret = priv->cfg->combphy_cfg(priv); + if (ret) { + dev_err(priv->dev, "failed to init phy for sata\n"); + return ret; + } + } + + return ret; +} + +static int rockchip_combphy_sgmii_init(struct rockchip_combphy_priv *priv) +{ + int ret = 0; + + if (priv->cfg->combphy_cfg) { + ret = priv->cfg->combphy_cfg(priv); + if (ret) { + dev_err(priv->dev, "failed to init phy for sgmii\n"); + return ret; + } + } + + return ret; +} + +static int rockchip_combphy_set_mode(struct rockchip_combphy_priv *priv) +{ + switch (priv->mode) { + case PHY_TYPE_PCIE: + rockchip_combphy_pcie_init(priv); + break; + case PHY_TYPE_USB3: + rockchip_combphy_usb3_init(priv); + break; + case PHY_TYPE_SATA: + rockchip_combphy_sata_init(priv); + break; + case PHY_TYPE_SGMII: + case PHY_TYPE_QSGMII: + return rockchip_combphy_sgmii_init(priv); + default: + dev_err(priv->dev, "incompatible PHY type\n"); + return -EINVAL; + } + + return 0; +} + +static int rockchip_combphy_init(struct phy *phy) +{ + struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); + int ret; + + ret = clk_enable(&priv->ref_clk); + if (ret < 0 && ret != -ENOSYS) + return ret; + + ret = rockchip_combphy_set_mode(priv); + if (ret) + goto err_clk; + + reset_deassert(&priv->phy_rst); + + return 0; + +err_clk: + clk_disable(&priv->ref_clk); + + return ret; +} + +static int rockchip_combphy_exit(struct phy *phy) +{ + struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); + + clk_disable(&priv->ref_clk); + reset_assert(&priv->phy_rst); + + return 0; +} + +static int rockchip_combphy_xlate(struct phy *phy, struct ofnode_phandle_args *args) +{ + struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); + + if (args->args_count != 1) { + pr_err("invalid number of arguments\n"); + return -EINVAL; + } + + priv->mode = args->args[0]; + + return 0; +} + +static const struct phy_ops rochchip_combphy_ops = { + .init = rockchip_combphy_init, + .exit = rockchip_combphy_exit, + .of_xlate = rockchip_combphy_xlate, +}; + +static int rockchip_combphy_parse_dt(struct udevice *dev, + struct rockchip_combphy_priv *priv) +{ + struct udevice *syscon; + int ret; + + ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-grf", &syscon); + if (ret) { + dev_err(dev, "failed to find peri_ctrl pipe-grf regmap"); + return ret; + } + priv->pipe_grf = syscon_get_regmap(syscon); + + ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-phy-grf", &syscon); + if (ret) { + dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); + return ret; + } + priv->phy_grf = syscon_get_regmap(syscon); + + ret = clk_get_by_index(dev, 0, &priv->ref_clk); + if (ret) { + dev_err(dev, "failed to find ref clock\n"); + return PTR_ERR(&priv->ref_clk); + } + + ret = reset_get_by_index(dev, 0, &priv->phy_rst); + if (ret) { + dev_err(dev, "no phy reset control specified\n"); + return ret; + } + + return 0; +} + +static int rockchip_combphy_probe(struct udevice *udev) +{ + struct rockchip_combphy_priv *priv = dev_get_priv(udev); + const struct rockchip_combphy_cfg *phy_cfg; + + priv->mmio = (void __iomem *)dev_read_addr(udev); + if (IS_ERR(priv->mmio)) + return PTR_ERR(priv->mmio); + + phy_cfg = (const struct rockchip_combphy_cfg *)dev_get_driver_data(udev); + if (!phy_cfg) { + dev_err(udev, "No OF match data provided\n"); + return -EINVAL; + } + + priv->dev = udev; + priv->mode = PHY_TYPE_SATA; + priv->cfg = phy_cfg; + + return rockchip_combphy_parse_dt(udev, priv); +} + +static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) +{ + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; + u32 val; + + switch (priv->mode) { + case PHY_TYPE_PCIE: + /* Set SSC downward spread spectrum */ + val = readl(priv->mmio + (0x1f << 2)); + val &= ~GENMASK(5, 4); + val |= 0x01 << 4; + writel(val, priv->mmio + 0x7c); + + param_write(priv->phy_grf, &cfg->con0_for_pcie, true); + param_write(priv->phy_grf, &cfg->con1_for_pcie, true); + param_write(priv->phy_grf, &cfg->con2_for_pcie, true); + param_write(priv->phy_grf, &cfg->con3_for_pcie, true); + break; + case PHY_TYPE_USB3: + /* Set SSC downward spread spectrum */ + val = readl(priv->mmio + (0x1f << 2)); + val &= ~GENMASK(5, 4); + val |= 0x01 << 4; + writel(val, priv->mmio + 0x7c); + + /* Enable adaptive CTLE for USB3.0 Rx */ + val = readl(priv->mmio + (0x0e << 2)); + val &= ~GENMASK(0, 0); + val |= 0x01; + writel(val, priv->mmio + (0x0e << 2)); + + /* Set PLL KVCO fine tuning signals */ + val = readl(priv->mmio + (0x20 << 2)); + val &= ~(0x7 << 2); + val |= 0x2 << 2; + writel(val, priv->mmio + (0x20 << 2)); + + /* Set PLL LPF R1 to su_trim[10:7]=1001 */ + writel(0x4, priv->mmio + (0xb << 2)); + + /* Set PLL input clock divider 1/2 */ + val = readl(priv->mmio + (0x5 << 2)); + val &= ~(0x3 << 6); + val |= 0x1 << 6; + writel(val, priv->mmio + (0x5 << 2)); + + /* Set PLL loop divider */ + writel(0x32, priv->mmio + (0x11 << 2)); + + /* Set PLL KVCO to min and set PLL charge pump current to max */ + writel(0xf0, priv->mmio + (0xa << 2)); + + param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); + param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); + param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); + param_write(priv->phy_grf, &cfg->usb_mode_set, true); + break; + case PHY_TYPE_SATA: + writel(0x41, priv->mmio + 0x38); + writel(0x8F, priv->mmio + 0x18); + param_write(priv->phy_grf, &cfg->con0_for_sata, true); + param_write(priv->phy_grf, &cfg->con1_for_sata, true); + param_write(priv->phy_grf, &cfg->con2_for_sata, true); + param_write(priv->phy_grf, &cfg->con3_for_sata, true); + param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); + break; + case PHY_TYPE_SGMII: + param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); + param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); + param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); + param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); + break; + case PHY_TYPE_QSGMII: + param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); + param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); + param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); + param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); + param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); + break; + default: + pr_err("%s, phy-type %d\n", __func__, priv->mode); + return -EINVAL; + } + + /* The default ref clock is 25Mhz */ + param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); + + if (dev_read_bool(priv->dev, "rockchip,enable-ssc")) { + val = readl(priv->mmio + (0x7 << 2)); + val |= BIT(4); + writel(val, priv->mmio + (0x7 << 2)); + } + + return 0; +} + +static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = { + /* pipe-phy-grf */ + .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, + .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, + .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 }, + .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 }, + .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, + .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, + .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, + .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, + .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, + .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, + .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, + .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, + .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, + .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, + .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, + .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, + .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 }, + .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, + .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, + .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, + .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, + .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, + .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 }, + .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 }, + .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 }, + .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 }, + /* pipe-grf */ + .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 }, + .pipe_sgmii_mac_sel = { 0x0040, 1, 1, 0x00, 0x01 }, + .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 }, + .u3otg0_port_en = { 0x0104, 15, 0, 0x0181, 0x1100 }, + .u3otg1_port_en = { 0x0144, 15, 0, 0x0181, 0x1100 }, +}; + +static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { + .grfcfg = &rk3568_combphy_grfcfgs, + .combphy_cfg = rk3568_combphy_cfg, +}; + +static const struct udevice_id rockchip_combphy_ids[] = { + { + .compatible = "rockchip,rk3568-naneng-combphy", + .data = (ulong)&rk3568_combphy_cfgs + }, + { } +}; + +U_BOOT_DRIVER(rockchip_naneng_combphy) = { + .name = "naneng-combphy", + .id = UCLASS_PHY, + .of_match = rockchip_combphy_ids, + .ops = &rochchip_combphy_ops, + .probe = rockchip_combphy_probe, + .priv_auto = sizeof(struct rockchip_combphy_priv), +}; From patchwork Fri Feb 17 11:58:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 2724 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pl1-f199.google.com (mail-pl1-f199.google.com [209.85.214.199]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id BF3583F07F for ; Fri, 17 Feb 2023 12:59:22 +0100 (CET) Received: by mail-pl1-f199.google.com with SMTP id n1-20020a170902f60100b0019a68e484e1sf639444plg.14 for ; Fri, 17 Feb 2023 03:59:22 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1676635162; cv=pass; d=google.com; s=arc-20160816; b=LqNLG3jSfk7u3O8swoYLFJSTyVgulTodsQc1HpD3t7VHUS4eFEfVKciMs1i8qCm85s 456t97l8SB3r383AmWDwdV/qXIr3yh57pQAlPdwNeWMM8dUZxsFbDj/TXZCAhKbaBedO V6PRig+7GEYWdn1h4ayJAFsDbN6vrNOmlgZvr2m541C3WVT2S/KnYUDiksvxBWJ7vUne e+66/HhYRAdcIfDHgw4Z1IHaxLnnF11xZsvg+0OCNdRKQ/8OgxnpQijPqBQ5fGgWyHjk kNMFfAPtMed/wvB7ONHKh1GZ7KWgRBWiVklk3j2AC+Svi2/GegG8lzOABuV3tHVJSFeY Sthg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=moWRsl1JYixP7nFA36QYejolgLYV2NLlFuLe+s68C+Q=; b=X7CPfLCOQvZB+AKERaFXR8N19cgfpSA0DBw4eCpOZW4P54S0aAWXLEVcA2EjQkQLGg a2flPgBzYZH8RCOyjy9DD2K8gyTiUXtR4SHqwzwd5p9IW+Mdmjd2QgQvRSMXARcqeH0t XacEd+d9ckcU1cOd8W9d9GhpK9QwTeZea5TKecOVU2KfgQZ2rDQvkNfzj5iZF22S5rvY Nogq9f4AxnxgHiuKhZJgsn+HlsJAaEtaGaO0TGY+Dun8Svwf5MQxM/ckgQr7hSbjyg+A bYyKs4bOQx/K0Tlb4qVd96wS/+qKZJF2W4XVlup2QUms9OI8snJHsecRNw1upRq1OMKD dLbA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=BIvyjGlH; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date:message-id:reply-to; bh=moWRsl1JYixP7nFA36QYejolgLYV2NLlFuLe+s68C+Q=; b=Wq1nWjBdLIkmc/+4p+6iEKZmsoHx+f+4NEQ3JXT8mETZhT4MRHN+IeSqHsZoGa9JAn SNjsM3zQPs5QtqGApz4krgXDzShth+8U7tAsW5jmiiB4bQVHZMpuGQrSaeo/ooXpOPsR LMIm9b/ZxTAZisgsOglzQFhXRb6KR10p8V4/E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=moWRsl1JYixP7nFA36QYejolgLYV2NLlFuLe+s68C+Q=; b=zRECL1cgPF4bZzeBAYGRfy8fZE+8BkkznJC0xpFxso34+Yk9n0CiYvG5aeibs6JVjY qbY5vCX6P3Qh+5kfnmS8BsyVfGyGmCnFvK3xWzyz85mro/wQ8t2dCzTs+Fj5TWLOX1FO f0OgNHFebbTSWfK4gtugXoMEqK6F2HwwlY1hWDyeXe31+OYWCJcN+zsoxjN/uk01Ckzs GeQP0L9aOcPFLmMhLcoHxaAKL0C1xP8lPncuspxnk+uYeA/eHMNveqYZiubKA4jHlZus j0/tgXudE6Q0ubDrqJLC2A/b7IOCBJsAYv9MVZ6LWTHxtaz9b9YZI/VXgUu1WQ69Rk+D T3+Q== X-Gm-Message-State: AO0yUKVUZfL6vQtG6PoR+WhK07m8ZqWl+Rnz6vrNU5nrMFWh7V4BxBKP 9W/BXjHsE9o+VBO4DbnZfpeYnSbU X-Google-Smtp-Source: AK7set9xOk4aszAGGvbNXYdJw2FUBXx/LKg1gylbl1HMXGbB7qkwlhch2sV8Gvu/j9nRRo3o54CP4w== X-Received: by 2002:aa7:848d:0:b0:590:3182:9341 with SMTP id u13-20020aa7848d000000b0059031829341mr147454pfn.0.1676635162356; Fri, 17 Feb 2023 03:59:22 -0800 (PST) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:90a:e54a:b0:233:e65f:ffb9 with SMTP id ei10-20020a17090ae54a00b00233e65fffb9ls1457497pjb.3.-pod-canary-gmail; Fri, 17 Feb 2023 03:59:21 -0800 (PST) X-Received: by 2002:a17:902:f990:b0:19a:7ef8:7dd4 with SMTP id ky16-20020a170902f99000b0019a7ef87dd4mr851728plb.56.1676635161482; Fri, 17 Feb 2023 03:59:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676635161; cv=none; d=google.com; s=arc-20160816; b=GA5VH8mJHZ/Y2VNO2IMyKMA3T1OyZ3szX/KUkBEZvv6bmsEpRuFyvDgmdf9b3kdDhE uqxjkS+qnT6nK3eL6IR87jx4Gu80dWj2FMz9InogxUb+QQP0kVqqbC8HQrrieLmp80gg 4kaYgZE66eaqirvvo7ljzRjOkxGo4AQnxIsOM2J6/6joGQREay5vrMDhm26PTqRQw+H5 pxsmRvmq4El3whW7x3SMdeKrzXiJvUSmyC3Vuy8GVRakl8ibN+RKHkLzf/HTJZ0YQqHF jB/v/hDS/dyoUYdlwvFLTN/W0C/PX1jAF2mnAO7nVdNmV7KlWMqFQbDCeC6Te2QiEoTu ZXsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=8VlGp/Dwur0obkweleY0NmOdtuFxw+jaW7GSksY28Zw=; b=Ordqx9QNQnsv1DqpLW9itWYffl8UNazMwPe4d5A29qwHk2jNF9Dv/tkxZ/UxEeRlos hLKcoMXSzb2xwbyTnqcZxGBxTWcWTDyTFnF0XSRRakMw2iDg7VjAsX/8r9rya7V4gtNk EDeJ132aZOoOMv4S2WY7aAG+rEzJzNdNjkqV94w7IE+7rJ2ND8TT/1jR0rDrW+D7IvbG i5ZKQYN/CJJm/cQBwgBi2QrNRHTrqY9rjf4x48EKbRK5J1mRlxsJiSAfQ8keTjS5Mbj6 4e8ezmqnZu+aKI+Qa5nZBA13B5dnQTb35gMGAmAnmqXPTdWKnQO92En2PqBlKfFiGMKM prfw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=BIvyjGlH; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id d14-20020a170902654e00b0019ae40b11cbsor2057751pln.202.2023.02.17.03.59.21 for (Google Transport Security); Fri, 17 Feb 2023 03:59:21 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:902:d485:b0:19a:5939:51dd with SMTP id c5-20020a170902d48500b0019a593951ddmr11357933plg.20.1676635161208; Fri, 17 Feb 2023 03:59:21 -0800 (PST) Received: from localhost.localdomain ([183.83.141.79]) by smtp.gmail.com with ESMTPSA id ik15-20020a170902ab0f00b001991d6c6c64sm2989418plb.185.2023.02.17.03.59.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Feb 2023 03:59:20 -0800 (PST) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v4 09/12] arm64: dts: rk356x-u-boot: Drop combphy1 assigned-clocks/rates Date: Fri, 17 Feb 2023 17:28:42 +0530 Message-Id: <20230217115845.75303-10-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230217115845.75303-1-jagan@amarulasolutions.com> References: <20230217115845.75303-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=BIvyjGlH; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Jagan Teki combphy1 is failing to probe due to unhandled assigned-clocks and assigned-clocks-rates. => usb start starting USB... Bus usb@fd000000: Failed to get PHY1 for usb@fd000000 Port not available. Bus usb@fd800000: USB EHCI 1.00 There is no real requirement for them in U-Boot to handle, hence mark them as deleted-properties for the probe to success Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/rk356x-u-boot.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi index ccb8db0001..4e2d059fcf 100644 --- a/arch/arm/dts/rk356x-u-boot.dtsi +++ b/arch/arm/dts/rk356x-u-boot.dtsi @@ -22,6 +22,11 @@ }; }; +&combphy1 { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-rates; +}; + &cru { u-boot,dm-pre-reloc; status = "okay"; From patchwork Fri Feb 17 11:58:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 2725 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pj1-f71.google.com (mail-pj1-f71.google.com [209.85.216.71]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 3D5103F07F for ; Fri, 17 Feb 2023 12:59:27 +0100 (CET) Received: by mail-pj1-f71.google.com with SMTP id l7-20020a17090b078700b0020a71040b4csf380216pjz.6 for ; Fri, 17 Feb 2023 03:59:27 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1676635166; cv=pass; d=google.com; s=arc-20160816; b=QJVnh3aMIBiBt0lrBnST6DyHi9jL5DAFePz9eKl8TPqg7jHK3X3o0BziDvK68qL9dr q5RTtrYlORMW4JrBVaDxLtcnS80k3Y0wRVF333ZVGHlZrBlfxWHOjp+dXWAm578WvsU+ 7UnZxcFQhvUIBQHpp0cu+PQ+kO4kT6HCD+ZWYw1gEDgh1TZ5l6tkoYIbiBoB44XGRkFT VxjKkAlL7I2+0B8htp37QMIIUDT2Is1dhj6CH5GFVO8QQhWJHiJqDiv2rSC8vJm6Va7L web5oTvbO2m+v7mRJIurIvqtWGEx6rpQdELcS47V0j1trTNF3K3tsPI3/QSfNL0Q9P9p 8hPg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=YcLyEVXmO+lX9S+m1CvEh/nTY/rUzDMVO0aTOW97fEo=; b=0ZQB+8pOeDoPGEd11YTmr+hNY707pL9qjdC6CLT4Pd0FECF4ssKrTku+X++pt7v4Qd QJHKao5u2zldI8t+ZHZDPR7LDx0Z2KRx1+ullbB6qfvUt/GYK7Oi3lPtGVuamI2CjmCv bn9srHI7WgA7p0nFbjU1/YYk4Tks7gF/UROGPc2+BKOa/DjHSxMkD5CJt5JJubYydB0/ YfU5FXh2wTtr0wfJrlFkbC9uB0qZme5jSIddFYxLRKbBFhrfKcozTv8bFwjRM8o7t/aj L2+uFCyq/18p9utVuz3wBjisPsdiYyQMcSeu1UpkIx8EPMfa3XlGb3bO5qIj+UL0AXpo 9ePQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=cijO1CcI; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1676635166; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date:message-id:reply-to; bh=YcLyEVXmO+lX9S+m1CvEh/nTY/rUzDMVO0aTOW97fEo=; b=EkWXz/WEDXJrwlMqhD/nGHXfmER0j40G80iqypNvU3XkLiy0PnXkoDs8qaLdp1sDnL KvBXo8/xz4RRH47vILyU5QTZsKE4jHoY5JI4yTG7XG6OaUdqI+nP8R/gPCzr3XybSOU5 yRU2yK9zywOCUsFw+Bbixf0Mr1F0OAUzvcRJ0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1676635166; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=YcLyEVXmO+lX9S+m1CvEh/nTY/rUzDMVO0aTOW97fEo=; b=wBVwP2+5ATEF6ixC8Mh/omAFEVc+0JkaokIIXQBy7zNxL/OgxZ+PrtfTV60Uhh5jE+ 01Vrv6D/n5648I86aQofLUt2vC7gG6olczrzAxoFHRhL81VTBrN8tJJrkbhpuSHzGW+9 4V9yfphDbBnGqAcJmpBEUxAU9Jh8JqkbuSBRdRzYxMvOJ92mN/rSZbfw/phgku8v2iAu nkRj5KEvn0E+TbvX/9TFDMoyljF4JT069qZm/7mk5UOXBO8Y6Zvk6DbQ1cqSGCFh08Ke MIn5XgO16GLdXXOo69SWhE5Plgetkzv0dlXdQV5OYKxAi69EPJq822ZiLXxJG1j/o6gM /Vpw== X-Gm-Message-State: AO0yUKWu7R4opdGukDb5dYCN6uFE/3I6tcgRwRw7KOKHroADnt7y88a/ zHjVr6U1uzc8fWt7Kq2CdF/8V7zS X-Google-Smtp-Source: AK7set9xoROsvlw16QqZxIxrNZX/1arqbpoBa2FXWU/jEtnLKeSnMUwJ15Z8k233M5KlyWo/bJSKSw== X-Received: by 2002:a62:8101:0:b0:5a8:a56a:c580 with SMTP id t1-20020a628101000000b005a8a56ac580mr209897pfd.2.1676635165886; Fri, 17 Feb 2023 03:59:25 -0800 (PST) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:903:2309:b0:196:f81:2760 with SMTP id d9-20020a170903230900b001960f812760ls1301693plh.2.-pod-prod-gmail; Fri, 17 Feb 2023 03:59:25 -0800 (PST) X-Received: by 2002:a17:902:d54d:b0:199:2b9f:f369 with SMTP id z13-20020a170902d54d00b001992b9ff369mr255468plf.32.1676635164950; Fri, 17 Feb 2023 03:59:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676635164; cv=none; d=google.com; s=arc-20160816; b=jUK0Or9iAgNS5Zk1jxG4CnXQyNvIA1tiZBWBFjxCBtEn7+KTiRsnMgrkp1YZouwQaS F/5vM2sdmo5EWSYh3KlrW5qraSlEYJnwEZH4v0jSdLLZlr134oTwH3idbb+PBScXyzDG AQOzSSqCk8hLy5uMYpX5Jt5Ww9rdCkimALK4wYT2pXLN3jH7ZxBOFhIb6yYJ0tTETrZe 1qSSKwG4iS5hfxWEXNsqoIoOdwpeq7sZfxKqaZL9iLH7nVHNSFM2WV0YA/UKz2CrUdue A9FlH/zSfWSZD3NkMfJygJ+d7B5DI1QPh5s8SXPQxVDeou9kRxLyBqBNj6Tu8iey65DA 91QA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=YG9vrxvyucH4lwBuaRGfTR2uBtr+zv+5iDQl/MDfIcU=; b=0PapjyL0beRBtySx9IPsvtd/4nhbbNTYwguTsH9EADyrZADsFNmvpQ8NGF5MmAtYHK D0MOSPU8lV8quoLcr85CMydNo0c16o9PaXdgXhW/NCOM4jfHso85bnZmABgqkKQNarHq tutA8CUdyyClMCcjzvX87VqGVPAGNTzdVmEKyPeOwRpHML53d9v/3Q6fEyut5jaQ+YNi RiN8gpVYNPKG2Z6Xr/N3QUH65Tr/J0dL3KDOHHiSYwCfAgX76TzK888K6J9/Lb6okAwi zuOZnaBx03RZBhEPulTiajsV4DfgrCcjQ3p3ek7Voux0GwoqV84kYdqj2pxSYslbOnqc fumQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=cijO1CcI; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id j16-20020a170902da9000b00198ee539ca4sor2001583plx.188.2023.02.17.03.59.24 for (Google Transport Security); Fri, 17 Feb 2023 03:59:24 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:903:27ce:b0:195:f3e3:b923 with SMTP id km14-20020a17090327ce00b00195f3e3b923mr7866579plb.8.1676635164482; Fri, 17 Feb 2023 03:59:24 -0800 (PST) Received: from localhost.localdomain ([183.83.141.79]) by smtp.gmail.com with ESMTPSA id ik15-20020a170902ab0f00b001991d6c6c64sm2989418plb.185.2023.02.17.03.59.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Feb 2023 03:59:23 -0800 (PST) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com, Jagan Teki , Manoj Sai , Jianqun Xu Subject: [PATCH v4 10/12] rockchip: rk3568: add rk3568 pinctrl driver Date: Fri, 17 Feb 2023 17:28:43 +0530 Message-Id: <20230217115845.75303-11-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230217115845.75303-1-jagan@amarulasolutions.com> References: <20230217115845.75303-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=cijO1CcI; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Jagan Teki Add driver supporting pin multiplexing on rk3568 platform. Co-developed-by: Manoj Sai Signed-off-by: Manoj Sai Co-developed-by: Jianqun Xu Signed-off-by: Jianqun Xu Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- drivers/pinctrl/rockchip/Makefile | 1 + drivers/pinctrl/rockchip/pinctrl-rk3568.c | 362 ++++++++++++++++++++++ 2 files changed, 363 insertions(+) create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3568.c diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile index 9884355473..90461ae881 100644 --- a/drivers/pinctrl/rockchip/Makefile +++ b/drivers/pinctrl/rockchip/Makefile @@ -14,5 +14,6 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += pinctrl-rk3308.o obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o +obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o obj-$(CONFIG_ROCKCHIP_RV1126) += pinctrl-rv1126.o diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3568.c b/drivers/pinctrl/rockchip/pinctrl-rk3568.c new file mode 100644 index 0000000000..935aed9efc --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl-rk3568.c @@ -0,0 +1,362 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2020 Rockchip Electronics Co., Ltd + */ + +#include +#include +#include +#include +#include +#include + +#include "pinctrl-rockchip.h" + +static struct rockchip_mux_route_data rk3568_mux_route_data[] = { + MR_TOPGRF(RK_GPIO0, RK_PB3, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(0, 0, 0)), /* CAN0 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(0, 0, 1)), /* CAN0 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 0)), /* CAN1 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO4, RK_PC3, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 1)), /* CAN1 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO4, RK_PB5, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(4, 4, 0)), /* CAN2 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO2, RK_PB2, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(4, 4, 1)), /* CAN2 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO4, RK_PC4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(6, 6, 0)), /* EDPDP_HPDIN IO mux selection M0 */ + MR_TOPGRF(RK_GPIO0, RK_PC2, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(6, 6, 1)), /* EDPDP_HPDIN IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PB1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 0)), /* GMAC1 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO4, RK_PA7, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 1)), /* GMAC1 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO4, RK_PD1, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 0)), /* HDMITX IO mux selection M0 */ + MR_TOPGRF(RK_GPIO0, RK_PC7, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 1)), /* HDMITX IO mux selection M1 */ + MR_TOPGRF(RK_GPIO0, RK_PB6, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 0)), /* I2C2 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO4, RK_PB4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 1)), /* I2C2 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO1, RK_PA0, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(0, 0, 0)), /* I2C3 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PB6, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(0, 0, 1)), /* I2C3 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO4, RK_PB2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(2, 2, 0)), /* I2C4 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO2, RK_PB1, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(2, 2, 1)), /* I2C4 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PB4, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(4, 4, 0)), /* I2C5 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO4, RK_PD0, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(4, 4, 1)), /* I2C5 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 0)), /* PWM4 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 1)), /* PWM4 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 0)), /* PWM5 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 1)), /* PWM5 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 0)), /* PWM6 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 1)), /* PWM6 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 0)), /* PWM7 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 1)), /* PWM7 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 0)), /* PWM8 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 1)), /* PWM8 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 0)), /* PWM9 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 1)), /* PWM9 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 0)), /* PWM10 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 1)), /* PWM10 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 0)), /* PWM11 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 1)), /* PWM11 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 0)), /* PWM12 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 1)), /* PWM12 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 0)), /* PWM13 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 1)), /* PWM13 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 0)), /* PWM14 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 1)), /* PWM14 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 0)), /* PWM15 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 1)), /* PWM15 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(14, 14, 0)), /* SDMMC2 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PA5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(14, 14, 1)), /* SDMMC2 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO0, RK_PB5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(0, 0, 0)), /* SPI0 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO2, RK_PD3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(0, 0, 1)), /* SPI0 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO2, RK_PB5, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 0)), /* SPI1 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PC3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 1)), /* SPI1 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(4, 4, 0)), /* SPI2 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(4, 4, 1)), /* SPI2 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO4, RK_PB3, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(6, 6, 0)), /* SPI3 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(6, 6, 1)), /* SPI3 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO2, RK_PB4, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(8, 8, 0)), /* UART1 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(8, 8, 1)), /* UART1 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(10, 10, 0)), /* UART2 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(10, 10, 1)), /* UART2 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(12, 12, 0)), /* UART3 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PB7, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(12, 12, 1)), /* UART3 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(14, 14, 0)), /* UART4 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PB2, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(14, 14, 1)), /* UART4 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO2, RK_PA2, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(0, 0, 0)), /* UART5 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PC2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(0, 0, 1)), /* UART5 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO2, RK_PA4, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 0)), /* UART6 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 1)), /* UART6 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO2, RK_PA6, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(5, 4, 0)), /* UART7 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 1)), /* UART7 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(5, 4, 2)), /* UART7 IO mux selection M2 */ + MR_TOPGRF(RK_GPIO2, RK_PC5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(6, 6, 0)), /* UART8 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO2, RK_PD7, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(6, 6, 1)), /* UART8 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO2, RK_PB0, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(9, 8, 0)), /* UART9 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO4, RK_PC5, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 1)), /* UART9 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO4, RK_PA4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 2)), /* UART9 IO mux selection M2 */ + MR_TOPGRF(RK_GPIO1, RK_PA2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(11, 10, 0)), /* I2S1 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(11, 10, 1)), /* I2S1 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(11, 10, 2)), /* I2S1 IO mux selection M2 */ + MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(12, 12, 0)), /* I2S2 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO4, RK_PB6, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(12, 12, 1)), /* I2S2 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(14, 14, 0)), /* I2S3 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(14, 14, 1)), /* I2S3 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(0, 0, 0)), /* PDM IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(0, 0, 1)), /* PDM IO mux selection M1 */ + MR_TOPGRF(RK_GPIO0, RK_PA5, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(3, 2, 0)), /* PCIE20 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 1)), /* PCIE20 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO1, RK_PB0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 2)), /* PCIE20 IO mux selection M2 */ + MR_TOPGRF(RK_GPIO0, RK_PA4, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO2, RK_PD2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO1, RK_PA5, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux selection M2 */ + MR_TOPGRF(RK_GPIO0, RK_PA6, RK_FUNC_2, 0x0314, RK_GENMASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO2, RK_PD4, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux selection M2 */ +}; + +static int rk3568_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int iomux_num = (pin / 8); + struct regmap *regmap; + int reg, ret, mask; + u8 bit; + u32 data; + + debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); + + if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) + regmap = priv->regmap_pmu; + else + regmap = priv->regmap_base; + + reg = bank->iomux[iomux_num].offset; + if ((pin % 8) >= 4) + reg += 0x4; + bit = (pin % 4) * 4; + mask = 0xf; + + data = (mask << (bit + 16)); + data |= (mux & mask) << bit; + ret = regmap_write(regmap, reg, data); + + return ret; +} + +#define RK3568_PULL_PMU_OFFSET 0x20 +#define RK3568_PULL_GRF_OFFSET 0x80 +#define RK3568_PULL_BITS_PER_PIN 2 +#define RK3568_PULL_PINS_PER_REG 8 +#define RK3568_PULL_BANK_STRIDE 0x10 + +static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *info = bank->priv; + + if (bank->bank_num == 0) { + *regmap = info->regmap_pmu; + *reg = RK3568_PULL_PMU_OFFSET; + *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE; + } else { + *regmap = info->regmap_base; + *reg = RK3568_PULL_GRF_OFFSET; + *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE; + } + + *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4); + *bit = (pin_num % RK3568_PULL_PINS_PER_REG); + *bit *= RK3568_PULL_BITS_PER_PIN; +} + +#define RK3568_DRV_PMU_OFFSET 0x70 +#define RK3568_DRV_GRF_OFFSET 0x200 +#define RK3568_DRV_BITS_PER_PIN 8 +#define RK3568_DRV_PINS_PER_REG 2 +#define RK3568_DRV_BANK_STRIDE 0x40 + +static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *info = bank->priv; + + /* The first 32 pins of the first bank are located in PMU */ + if (bank->bank_num == 0) { + *regmap = info->regmap_pmu; + *reg = RK3568_DRV_PMU_OFFSET; + } else { + *regmap = info->regmap_base; + *reg = RK3568_DRV_GRF_OFFSET; + *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE; + } + + *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4); + *bit = (pin_num % RK3568_DRV_PINS_PER_REG); + *bit *= RK3568_DRV_BITS_PER_PIN; +} + +#define RK3568_SCHMITT_BITS_PER_PIN 2 +#define RK3568_SCHMITT_PINS_PER_REG 8 +#define RK3568_SCHMITT_BANK_STRIDE 0x10 +#define RK3568_SCHMITT_GRF_OFFSET 0xc0 +#define RK3568_SCHMITT_PMUGRF_OFFSET 0x30 + +static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *info = bank->priv; + + if (bank->bank_num == 0) { + *regmap = info->regmap_pmu; + *reg = RK3568_SCHMITT_PMUGRF_OFFSET; + } else { + *regmap = info->regmap_base; + *reg = RK3568_SCHMITT_GRF_OFFSET; + *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE; + } + + *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4); + *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG; + *bit *= RK3568_SCHMITT_BITS_PER_PIN; + + return 0; +} + +static int rk3568_set_pull(struct rockchip_pin_bank *bank, + int pin_num, int pull) +{ + struct regmap *regmap; + int reg, ret; + u8 bit, type; + u32 data; + + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) + return -ENOTSUPP; + + rk3568_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); + type = bank->pull_type[pin_num / 8]; + ret = rockchip_translate_pull_value(type, pull); + if (ret < 0) { + debug("unsupported pull setting %d\n", pull); + return ret; + } + + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); + + data |= (ret << bit); + ret = regmap_write(regmap, reg, data); + + return ret; +} + +static int rk3568_set_drive(struct rockchip_pin_bank *bank, + int pin_num, int strength) +{ + struct regmap *regmap; + int reg; + u32 data; + u8 bit; + int drv = (1 << (strength + 1)) - 1; + int ret = 0; + + rk3568_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); + + /* enable the write to the equivalent lower bits */ + data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << (bit + 16); + data |= (drv << bit); + + ret = regmap_write(regmap, reg, data); + if (ret) + return ret; + + if (bank->bank_num == 1 && pin_num == 21) + reg = 0x0840; + else if (bank->bank_num == 2 && pin_num == 2) + reg = 0x0844; + else if (bank->bank_num == 2 && pin_num == 8) + reg = 0x0848; + else if (bank->bank_num == 3 && pin_num == 0) + reg = 0x084c; + else if (bank->bank_num == 3 && pin_num == 6) + reg = 0x0850; + else if (bank->bank_num == 4 && pin_num == 0) + reg = 0x0854; + else + return 0; + + data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << 16; + data |= drv; + + return regmap_write(regmap, reg, data); +} + +static int rk3568_set_schmitt(struct rockchip_pin_bank *bank, + int pin_num, int enable) +{ + struct regmap *regmap; + int reg; + u32 data; + u8 bit; + + rk3568_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit); + + /* enable the write to the equivalent lower bits */ + data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16); + data |= (enable << bit); + + return regmap_write(regmap, reg, data); +} + +static struct rockchip_pin_bank rk3568_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, + IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, + IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, + IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT), + PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT), + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT), + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT), + PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT), +}; + +static const struct rockchip_pin_ctrl rk3568_pin_ctrl = { + .pin_banks = rk3568_pin_banks, + .nr_banks = ARRAY_SIZE(rk3568_pin_banks), + .nr_pins = 160, + .grf_mux_offset = 0x0, + .pmu_mux_offset = 0x0, + .iomux_routes = rk3568_mux_route_data, + .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data), + .set_mux = rk3568_set_mux, + .set_pull = rk3568_set_pull, + .set_drive = rk3568_set_drive, + .set_schmitt = rk3568_set_schmitt, +}; + +static const struct udevice_id rk3568_pinctrl_ids[] = { + { + .compatible = "rockchip,rk3568-pinctrl", + .data = (ulong)&rk3568_pin_ctrl + }, + { } +}; + +U_BOOT_DRIVER(pinctrl_rk3568) = { + .name = "rockchip_rk3568_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = rk3568_pinctrl_ids, + .priv_auto = sizeof(struct rockchip_pinctrl_priv), + .ops = &rockchip_pinctrl_ops, +#if CONFIG_IS_ENABLED(OF_REAL) + .bind = dm_scan_fdt_dev, +#endif + .probe = rockchip_pinctrl_probe, +}; From patchwork Fri Feb 17 11:58:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 2726 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pj1-f70.google.com (mail-pj1-f70.google.com [209.85.216.70]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id D71F33F07F for ; Fri, 17 Feb 2023 12:59:29 +0100 (CET) Received: by mail-pj1-f70.google.com with SMTP id bf9-20020a17090b0b0900b0022925dd66d3sf558305pjb.4 for ; Fri, 17 Feb 2023 03:59:29 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1676635168; cv=pass; d=google.com; s=arc-20160816; b=hpLMNhUJSoMDbLWdm1Q0n50XWV8BjzCPgEZ1rjQ44Sn36B6TCArCHiFnK3pYZzSwtp o7S+XnGNWnOH1TvOBv0t7UvPSDfvphNMaESCrzwD0KliZjoAZDSPVz31HKt8VWNomAME OHh2oEd4tdzcg9N2YM2UxV/6NhGMvns580IJzOmF2UHACRcvJJkJvcRncrrjFFJlqRqy xE2X2+z7AN8EyTzCOaJGFZRG8hsIkgl91MR9R8Ec++Szyi+v+ljnNtq9EOc9uapF8X/N wTYTLnyQmH5qVXEAhIQdsOgzwUE+70rIQr/M93Stl0QRo1K6xKmuK3If2MWq5LMKczJ6 0Gfg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=cm4iADXEWWK/jhXJxR7bm3iocjrED7carXP1djdrvDg=; b=Kdxm3EWzK7LjtEMziYnQRlsDu0tFl+OFKFh1yDeuqu0Gj4Pok8DZcaq3YbcRIbrAdM eSBVRq60gRGEVA/vpw4/xTSaOKrDCo+IkWiS0/n35wwU9+WGkSobk1z+rzO3tkZMZctj OQwTcPOuhMhhFRAPX+KXcU6pZfcD3bTMR/RmUktC+6hqnpdXtuCMkQn6OTDDx09yaGZu 5U72eUW0llaxsyo+8QlcX+T5U1oCRzNaXDhPlT28J0++oT3vj2J2xLQ3gHBcZom2/mgJ 9V5Qr6zsod5y36ZU0Z0TP6A85aPVpUj3UPsi6dA8c4j6+n7Wqa07OGmuwNQF4kSY7Vf/ 8xOQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=MjnowY2o; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date:message-id:reply-to; bh=cm4iADXEWWK/jhXJxR7bm3iocjrED7carXP1djdrvDg=; b=Y9DvWkapO0RoWb5VeQHMgku16foF9nCy40SeYVVILl0mKU6knsQMR3F1eEVO81X7RR d0WIsUpLd0Ke06l+QgBoeHx/8dZ+6HZUZvlD1s96rw//CBQmQIwA/uC6rbWtN02zLePu PXjCgS5LCMPznm7u7DDDH7cwjvTGEzai9xvxM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=cm4iADXEWWK/jhXJxR7bm3iocjrED7carXP1djdrvDg=; b=OOqvStlp3tu0csNzcsEqhe/BIpAtrboAvVJy9uqmksCxcnhaEgqC8upLX56RumnPmW Ia41XanlqiiQJnWrdBrbPeLim53C6fX2SeEhmp4zrxeLLxdCFzoXS2r0FEu4LLWi9ILp qBO0pabecYtJggLKAQ1xWxfUcUCQj/NH+5oEm2knQqSOEps7Cfkd5r06z7ceAqv5r/Ch ZrWpgo5drI8nZS7hL42l8BMLFUV80r5epp24pwH7MD0b7zraB6oIy92fGdr/E9sWVVUw tdWQoQkkobEe42mCRjcwnVDRuaXcI6dVmCZRQzkpJYm/aBIsyOhYCmP4C8jz7SwD3TOA cfng== X-Gm-Message-State: AO0yUKV04FQXkp5CrmqALsVoiE4ikJ28FoCv39+M3EBYusiHiYKvLPNQ G8sr36hO2EzU7vY+2GZiHkMv90RO X-Google-Smtp-Source: AK7set8QmfBoTKon6h4cuyu+fMg3knEGjIVuHnjzaSLEW82eGVDpqul/Ubju0CwaqAXIehmKbJ89Dg== X-Received: by 2002:aa7:9511:0:b0:5a8:47b4:5fd5 with SMTP id b17-20020aa79511000000b005a847b45fd5mr1439242pfp.32.1676635168601; Fri, 17 Feb 2023 03:59:28 -0800 (PST) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:903:787:b0:196:2e27:844e with SMTP id kn7-20020a170903078700b001962e27844els1191640plb.7.-pod-prod-gmail; Fri, 17 Feb 2023 03:59:28 -0800 (PST) X-Received: by 2002:a17:902:e891:b0:19a:d7d8:a080 with SMTP id w17-20020a170902e89100b0019ad7d8a080mr8012048plg.22.1676635167770; Fri, 17 Feb 2023 03:59:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676635167; cv=none; d=google.com; s=arc-20160816; b=df9oOS1E3PcmccDpq8Dap/qU9wfSkkInagSP/eQynkab1fNqj8f3iEvASZC7fxTTmR 4CLYfCN5YS/Ltvfle7J7AKy1p5RI0ap6WRw45n9CyKaXVMHpvOfb4XPjjTBC98yaiyf1 jfVp6Z/9qQl/PLwfvnUMy0OrpU8DoFGbPZKHtyXbo12UPwQDIU8h06D8wXy62B9EOq6b dafkDm/82c+cUXd+2Wltw1JP6eMLephJyJGqKlmqGkZF1cmBYhobRkqwS2XVLIs9zv/Y xo2Vw/1rx+wvdCY9/0+42sWJyO/M4NMz6PgJ4ILuMIG7hgRnjy2WWnpeK8QzXUfb4zJd M6Iw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=PBL/4+mHbXTLQ3iTRjatKNH9Q4ClDME20QQQQW0U9M4=; b=px8ID5N7c2EX6ag2gDW18dxQKHAjA2tHDbWTEA95JAOxFVtLHePO1KhMWV462q1HtC EMvUpwM4/HOevR8qoGtBqJCovaxNe27bRwBtX5SsIqApgW1xEUrpl2lwCggnxQZQC98y G0qFc7cG3vj4H/9+lEKmmnr+Ul4KwhbJMeLdGiwKVgLbW65a38IgOTEvGkFYE6G5cJV8 vL4Fxw18E5BFNK4PR+4ObDe38/6jMBqexr6ADggeTiix0KR8RV9aE9W74cNpcnmlzDoz 8c6Qo27WRkQFvD3vzf1rziSzWeVP5eItbH3wA4Zxz41rIWc7XCJhwscURdkdmGz99MJY Seig== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=MjnowY2o; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id e6-20020a170902784600b0019aa9c34c90sor2079457pln.115.2023.02.17.03.59.27 for (Google Transport Security); Fri, 17 Feb 2023 03:59:27 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:902:e551:b0:19a:af54:d814 with SMTP id n17-20020a170902e55100b0019aaf54d814mr11087114plf.67.1676635167428; Fri, 17 Feb 2023 03:59:27 -0800 (PST) Received: from localhost.localdomain ([183.83.141.79]) by smtp.gmail.com with ESMTPSA id ik15-20020a170902ab0f00b001991d6c6c64sm2989418plb.185.2023.02.17.03.59.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Feb 2023 03:59:26 -0800 (PST) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com, Manoj Sai , Suniel Mahesh Subject: [PATCH v4 11/12] rockchip: rk3568: Select DM_REGULATOR_FIXED Date: Fri, 17 Feb 2023 17:28:44 +0530 Message-Id: <20230217115845.75303-12-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230217115845.75303-1-jagan@amarulasolutions.com> References: <20230217115845.75303-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=MjnowY2o; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Manoj Sai Select the DM_REGULATOR_FIXED on RK3568 platform. Co-developed-by: Suniel Mahesh Signed-off-by: Suniel Mahesh Signed-off-by: Manoj Sai Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 3dc85df65d..6fa8c050cb 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -286,6 +286,7 @@ config ROCKCHIP_RK3568 select REGMAP select SYSCON select BOARD_LATE_INIT + select DM_REGULATOR_FIXED select DM_RESET imply ROCKCHIP_COMMON_BOARD help From patchwork Fri Feb 17 11:58:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 2727 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pj1-f71.google.com (mail-pj1-f71.google.com [209.85.216.71]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 482CF3F07F for ; Fri, 17 Feb 2023 12:59:32 +0100 (CET) Received: by mail-pj1-f71.google.com with SMTP id l7-20020a17090b078700b0020a71040b4csf380286pjz.6 for ; Fri, 17 Feb 2023 03:59:32 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1676635172; cv=pass; d=google.com; s=arc-20160816; b=KPxbTtgWbyRKhSC4JWNPiEHcChSrFs7NBxQDKP9njN9274ubK+bK3bvMhC9OB3dJjR cFV7Z7+Opi4zP1BkoYiBYqd7NgEMyZIRmA8ixVFPvkYNRaW14xKn2gQdUxpd3abkCVFl WM3RosUDvdK/H8Qlt3/MQk5m28Z3zMrOwDby50ZN9npjEIpNjym7bAko6zZopclBsTWA OfXLytjP+L7BHuJDbfZckTB0oWeHJWhdU2pZ7pJNkgkvmfkvAOtOIk40xaGrL2C5MJa2 mwC2AuCS5LUAghAjxsPhuAzW5Y3EmMO13piX0UJ4IaCOD5ti8ehUbJixPhUQ+1Vq+s77 p+qw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=7gUIu1gjq24DvCp3mr8dd0dLKTdsiBviJhTKGtmXSuA=; b=H/O4TwRVN+sf3g1vTCsm2BAq6tKQiybuUk5F3rqV4P+uGUXsvNB7Fi5g9hfMYh6Mmg aIaKBnErH94uYO4hcj5hYwtJJEbcf61OLJZjvFpK2OH8OXj8teOYCvu/mPNwENdE6VCB 2jWv8fo3BpeU2I6lPJxXHyw9iOZyQM+4zxiwUQvbVEj9ErlHSExZc51fYizJdkxebraQ IEqEq7eOYmtp6bsE94OxEm4t6IHaLp8AChU2x8ZUDcoam7KgSlF2umCMBkACGJ+1iXDd iZITHaa0wh4GsQFPkncfhReFUbGqrv8muU6aOD7ZLWxwFryUpEeCjfEFT8WfgwkFWvDC dsZw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=eq50dYw3; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date:message-id:reply-to; bh=7gUIu1gjq24DvCp3mr8dd0dLKTdsiBviJhTKGtmXSuA=; b=i2YAUp9m+nQmvPSDk+7bkQuaqFtEZiMWa57uiNd/7iUf7yFQtmYtOZXZAPLQhmv9hE bYxTfXakc3N1J+QTnPv9OPAZ9cpbUZM3onhJU6S5VZ+xG6/XOzpjaLE0ujXk3RgNsfJx PtU/kHZlBcZdTxKzyh+DV9r4nt7kgdM1u5Cfc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=7gUIu1gjq24DvCp3mr8dd0dLKTdsiBviJhTKGtmXSuA=; b=R3fBB+u03Phdfy3p7LXgFfApGfY7YUcOdO6UmhgkVoCyM5qfLzD4j4BdGyb5xNt1Ef Wzhq08I6brYYYSzdFuqDxk5G/LZTpKPJOsjp4GXJLymKblt5+iDAFh+W6fQy4bWxvjFL T5ayeO7l0xIa815cGoIv+RbnkG/qqY5epsktQYG4sfcLwECChpsf5Mdm7IcYVEhUyBus DeUF1pt+ciI5/NylF+dfBT3T7goEuFvDgNzCQm3JqZMpIxPlia27ZsVnc31IyVPN8UbR s/XTMNxKbMmSR14JcL0g7NBWWxPd7ccuXK/tOzjCTXnxuAoh8Zun49Ex56XnL1irCde/ 7uew== X-Gm-Message-State: AO0yUKUqH2L5+7bXcOetsPINtL8CyKZaApcrSVGDlBt+DbldlD32MX1g SxbWTkRGBL5KLot+xGuL47uObywJS/wZHQ== X-Google-Smtp-Source: AK7set/Ha2PUZ24DSNVvsEk+bhUHG6tG4u6ZmU3TG3GlIMT2prLJImZ98VqKsJ0xwKcsnc7pip9L6w== X-Received: by 2002:aa7:83d5:0:b0:5a9:d734:7dc with SMTP id j21-20020aa783d5000000b005a9d73407dcmr335245pfn.48.1676635171869; Fri, 17 Feb 2023 03:59:31 -0800 (PST) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:90b:3b86:b0:233:a692:d310 with SMTP id pc6-20020a17090b3b8600b00233a692d310ls1450932pjb.3.-pod-control-gmail; Fri, 17 Feb 2023 03:59:31 -0800 (PST) X-Received: by 2002:a17:903:283:b0:19a:9831:c8d6 with SMTP id j3-20020a170903028300b0019a9831c8d6mr1214297plr.50.1676635171013; Fri, 17 Feb 2023 03:59:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676635170; cv=none; d=google.com; s=arc-20160816; b=udv935Ev2hMUyl6KxQpTfU6r+j0RRRpomwd6yciqknw8gJqiCYYRXEwWpGiqsamFOQ 3bVWH4ur4sJemrzv398zheNwizV6K9ofyHmh7nTwPE8tf/6JYJVPYvXG90oSvVDDxM2O 8xs+9JKcppuU4TtTOotHo7VxBdT9f6MjGpzVN8py4Ocn+jOM9tXitvdqEmYAaIUNM8KS klqZoObY2VL8gCg9xq0j9QwJPRaRYLsUthixwxtdKJkcTU6WgokoFQ7YA8lvPIVX0uGA qUoy7ydWo4E5am2uifyk4zF53HwxQRmbhYYQSt+QgFeMMnZtdsF9JZM46dFWnRz/4MAS Sv0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=R3EKCnwPrrq5r+mZNI6aunWFmi1D6SD4r5/3N7/X6DY=; b=Z60CsjhEvvK+laRcFYQdb9BLxBO8X6wzqXGUpU0seUF2pAgcQrsGUYMnqXfp2kujhs Iafzx3rYgqO6rongxvsVr35kiZB/Q0Cg7N/Qt3vURQEcYqnZaU0Wvcyi8wXUj52WvV6z FJGWAHHefiHSeMsYofTJPoOjTbW1lrcr9Lh4MZaH6W8iW0VaH0zSkotYyhXiU4hlukdE TXp3hn7J3zAEGke0JbKVUjpsbVjJiSQMVM80SQh8EoPFi3ZsGPQl+3Nyerp+E6bDPSUl 8jUv2y1OvqIJDAfJemC34w5gl/kJgH91JpcyGSWRTN8WJlG4C15CUcqS9tuwIH3c9l2Q xiDA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=eq50dYw3; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id jw19-20020a170903279300b0019b0d53997fsor1443886plb.180.2023.02.17.03.59.30 for (Google Transport Security); Fri, 17 Feb 2023 03:59:30 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:902:d50e:b0:196:8292:e879 with SMTP id b14-20020a170902d50e00b001968292e879mr762668plg.1.1676635170684; Fri, 17 Feb 2023 03:59:30 -0800 (PST) Received: from localhost.localdomain ([183.83.141.79]) by smtp.gmail.com with ESMTPSA id ik15-20020a170902ab0f00b001991d6c6c64sm2989418plb.185.2023.02.17.03.59.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Feb 2023 03:59:30 -0800 (PST) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com, Manoj Sai , Suniel Mahesh Subject: [PATCH v4 12/12] rk3566: radxa-cm3: Enable USB2.0, USB3.0 support Date: Fri, 17 Feb 2023 17:28:45 +0530 Message-Id: <20230217115845.75303-13-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230217115845.75303-1-jagan@amarulasolutions.com> References: <20230217115845.75303-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=eq50dYw3; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Manoj Sai => usb start starting USB... Bus usb@fd000000: Register 2000140 NbrPorts 2 Starting the controller USB XHCI 1.10 Bus usb@fd800000: USB EHCI 1.00 scanning bus usb@fd000000 for devices... cannot reset port 1!? 2 USB Device(s) found scanning bus usb@fd800000 for devices... 4 USB Device(s) found scanning usb for storage devices... 2 Storage Device(s) found => usb tree USB device tree: 1 Hub (5 Gb/s, 0mA) | U-Boot XHCI Host Controller | +-2 Mass Storage (5 Gb/s, 224mA) SanDisk Dual Drive 04019c9b2e1a58f24ee318c3c123aa5 1 Hub (480 Mb/s, 0mA) | u-boot EHCI Host Controller | +-2 Hub (480 Mb/s, 100mA) | USB 2.0 Hub | +-3 Mass Storage (480 Mb/s, 500mA) | JetFlash Mass Storage Device 19M7I4ZQFTSC08SU | +-4 Human Interface (12 Mb/s, 98mA) Logitech USB Receiver Co-developed-by: Suniel Mahesh Signed-off-by: Suniel Mahesh Signed-off-by: Manoj Sai Reviewed-by: Kever Yang --- configs/radxa-cm3-io-rk3566_defconfig | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/configs/radxa-cm3-io-rk3566_defconfig b/configs/radxa-cm3-io-rk3566_defconfig index a79d9b25e3..2100cf2cb2 100644 --- a/configs/radxa-cm3-io-rk3566_defconfig +++ b/configs/radxa-cm3-io-rk3566_defconfig @@ -38,6 +38,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y @@ -57,10 +58,20 @@ CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y CONFIG_ERRNO_STR=y