From patchwork Tue Mar 28 07:33:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2816 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f72.google.com (mail-ed1-f72.google.com [209.85.208.72]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 796BD414B2 for ; Tue, 28 Mar 2023 09:33:47 +0200 (CEST) Received: by mail-ed1-f72.google.com with SMTP id k30-20020a50ce5e000000b00500544ebfb1sf16073226edj.7 for ; Tue, 28 Mar 2023 00:33:47 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1679988827; cv=pass; d=google.com; s=arc-20160816; b=RM70v9WvhlVWnKq5bGbq9kLgUDEOoZ3ZgwhgfOQAFepkiwtIACP5ElR8BHB8m58NLf 6rZnaYimBeiPu5eCTGl5FBke32OijgalLEFoHmWUUb/4wlVZHuVRpuUptlL0znQxkrQL OI16p700pbiT2hV3caX1k9jN99dy399Yjya812xUvgBCu9+S2SqHRi+RDiawdl2ibbr5 nNL6Ce/8FHcmN/nEI6tcf6bLtO1bHNdL851lPC6nF4Am8QGiDaGBNyxgKpH6Z3Ck+Bco RVKPH2NcqmdssGY2/KfgR9hh6HtgFNZpzUH87BIvVzF/jXKr+lqJ15X/GP1EkZrf4BT0 zajw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=WgS5WN+3RLa+KLLTZSiUeRPlxPttBqqYTXDW8zBKJdM=; b=KuKffgbBbPQLyRkH1zq1NBlAXy29Y2rO9OErzBuIFsrJaUDYMu+12EEhj6kJ9WebVV qQzfb85v+ogxlRPw+fDFxcJ+1rN2u/4+YdfPltBlXboChoGE0AP9kY7Af6GdW4RVOk36 knDUO8fpbOvaieJsqvzU4j8AjO/dX4Zy0ubuZQUyNm0jl/EdipFK4BU2RDm7DHouVdPp kiw/2zPmct4sLaVEU904BiFPeYudMTiCX7Bbpr6FgTf8+V+5bVb2deDwZhq4BG2G895A sHYlaRTrMBrL8f/S3j7yZQXXsgjhpqZmVF2ptkcamqEasAEU1z/s+5DJr+7lHIs+/J+Y Gr9A== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=IuvzJdDP; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1679988827; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date:message-id:reply-to; bh=WgS5WN+3RLa+KLLTZSiUeRPlxPttBqqYTXDW8zBKJdM=; b=ankoKizNd7GzWdXvIJmbrxV7u9VLyG+9BYsn/CyHGlSoxi7QHDp+5/EnPxO79vNxhq 2L+L73GtiFXWZbgK5UF5jAmx1JKe1Pb1lOPyfMYBbc/28b9FRUe6jcL3Uk2gyhijIrj9 /ZhnKgpkIj7SxI0BdaCDhb6aBwhT7hcEhg0q4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679988827; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=WgS5WN+3RLa+KLLTZSiUeRPlxPttBqqYTXDW8zBKJdM=; b=tt/du0ppWQhlZ0IvILXQQl+6NWVdPdoWFZuVygAQRBDU7Tk24beB27vGBZ511O7gJ1 /4WL42NhW7qFk3TBaLS0YTr24MMK556doM7Q22QNUBX62wjusXtYUPyHZ2MZtNryRx4f miSGpOidqcrz/ltB1dRLnk3SfjXUg1UQ9DkUonZuJkwFl5KInfK0Qs4Ubq1asluyG0La Ej9GrmUEOa+GVv2j9ehFNk+JXg+F0mkHZYoLvE6MyCgFbxYeT8JmOCf+z6/qu/dKH2S8 L9SU9bTj/FwmXqy15Mkds5fVyFnR5dm2B2Y/9ML1RVgb+sj3HTrEb4EuIabOZDMMiEHx 5r3A== X-Gm-Message-State: AAQBX9dIYM0289StDBAe0qW6Y54UEWVACHEoTpdpxpKUgXs0xpqn0+w1 EpTSsN8bL5qiCpY9pdvDd0NH/c3v X-Google-Smtp-Source: AKy350ayAZNZCHEeBujy+0+MU4cx8sq8PIhpdUhVVUI6M9vhHsfGRrEHLp+wyV2zYYvRy4iqBjU66A== X-Received: by 2002:a17:906:4f1a:b0:930:528b:91e5 with SMTP id t26-20020a1709064f1a00b00930528b91e5mr7011215eju.4.1679988826767; Tue, 28 Mar 2023 00:33:46 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a05:6402:4311:b0:4ac:d2bc:e0cb with SMTP id m17-20020a056402431100b004acd2bce0cbls2842447edc.0.-pod-prod-gmail; Tue, 28 Mar 2023 00:33:45 -0700 (PDT) X-Received: by 2002:aa7:c846:0:b0:4fb:8d3c:3b86 with SMTP id g6-20020aa7c846000000b004fb8d3c3b86mr13867078edt.1.1679988824876; Tue, 28 Mar 2023 00:33:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1679988824; cv=none; d=google.com; s=arc-20160816; b=YbyXsDODKjM4+1m+wV7Q+3UEvXawD2aImeaj7LlZkIav3zuDxGahS3EfMKrjZhfGWB jUNVqPtOgNGRIO2KlYGx0QsSZB6moXBHzkN2YXHCt9PgW431vAhbL4rKU5n11xqbxJiN V4l0HmLAyNboDOzk8XLx9hhcemMiLGei3hPpyE0YWvcbZC834tRGQLj6qeSSTEIqn4q9 Xxt0uCnj+F0Jnv/RjcPVjNZEIpc+7VeDn6O0dkctMeWnl3S+4fJnGtRF4Dxt/z+a7yhW OhHFtbaPGkD9a1tasIY0ozv5aUFDwmUqutl+twbbFKFwFJz9qXADnJAD24B2tAMwvBUK 1PmQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=XLJ+jDIrSZvakcXMeiXZPJ9OyuW2iT0qYiAHEyeO2Pk=; b=da0r4SwKEMhV9WXi+X/lYrD7Dqgeo+ok9ChYpp2td7ZZ7c4Vi4BJernCumo5S7QKU1 s7hnCIzw19Ygje6u6yC0MmYtmFEozBnJsw0RwgYz0lXiAQKylMod4fIT243RcMEtm9uU PjH0A+4kMR0N9KtfIyg43Kd3tTaSBW/tUb1qdiVVhwYyX7zt6wh5eSDMBd9Toj4OEwMp 5c8caQl8O01AOmcRlGmsI+KsyuZmwZ9RD3TXihxWbMyb89+3qPERyDk/oJYQ90Jki9TN zOFkKLFlzrY//W3F9+dMrzwStIvihfa+HW5fUfrkaGcRxj1GWTRtPMbwynCPmZV7wk+T zIFQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=IuvzJdDP; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id e2-20020a50d4c2000000b005021f39a5desor5239942edj.33.2023.03.28.00.33.44 for (Google Transport Security); Tue, 28 Mar 2023 00:33:44 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:aa7:cac5:0:b0:500:4a5d:af3f with SMTP id l5-20020aa7cac5000000b005004a5daf3fmr15247146edt.34.1679988824575; Tue, 28 Mar 2023 00:33:44 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-87-0-102-254.retail.telecomitalia.it. [87.0.102.254]) by smtp.gmail.com with ESMTPSA id 15-20020a508e4f000000b004fa99a22c3bsm15478850edx.61.2023.03.28.00.33.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Mar 2023 00:33:44 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Vincent Mailhol , Rob Herring , Amarula patchwork , michael@amarulasolutions.com, Marc Kleine-Budde , Alexandre Torgue , Krzysztof Kozlowski , Dario Binacchi , Christophe Roullier , Dmitry Torokhov , Krzysztof Kozlowski , Mark Brown , Maxime Coquelin , Rob Herring , Viresh Kumar , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v10 1/5] dt-bindings: arm: stm32: add compatible for syscon gcan node Date: Tue, 28 Mar 2023 09:33:24 +0200 Message-Id: <20230328073328.3949796-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20230328073328.3949796-1-dario.binacchi@amarulasolutions.com> References: <20230328073328.3949796-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=IuvzJdDP; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Since commit ad440432d1f9 ("dt-bindings: mfd: Ensure 'syscon' has a more specific compatible") it is required to provide at least 2 compatibles string for syscon node. This patch documents the new compatible for stm32f4 SoC to support global/shared CAN registers access for bxCAN controllers. Signed-off-by: Dario Binacchi Acked-by: Rob Herring --- (no changes since v9) Changes in v9: - Fix commit description formatting. No semantic changes have been made. Changes in v5: - Add Rob Herring's Acked-by tag. .../devicetree/bindings/arm/stm32/st,stm32-syscon.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml index b2b156cc160a..ad8e51aa01b0 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml @@ -20,6 +20,7 @@ properties: - st,stm32-syscfg - st,stm32-power-config - st,stm32-tamp + - st,stm32f4-gcan - const: syscon - items: - const: st,stm32-tamp @@ -42,6 +43,7 @@ if: contains: enum: - st,stm32mp157-syscfg + - st,stm32f4-gcan then: required: - clocks From patchwork Tue Mar 28 07:33:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2817 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f71.google.com (mail-ed1-f71.google.com [209.85.208.71]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 86F2B414B4 for ; Tue, 28 Mar 2023 09:33:48 +0200 (CEST) Received: by mail-ed1-f71.google.com with SMTP id x35-20020a50baa6000000b005021d1b1e9esf16291969ede.13 for ; Tue, 28 Mar 2023 00:33:48 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1679988828; cv=pass; d=google.com; s=arc-20160816; b=EF+ogYfVHyV+WDoBfvIVdQJVTzFAKj+d75COUsWVy6v0/ap1TQGNi1rCiaPtVCWT0c y0FBJ9NfF6rXYjRL06scHVrUPjH2OsggWG6koSTtVq322KUWLdANBUXgip+H2Tie9jNa 6FL2GGUWmcpucQaJO2HSHBsMFIpf+lDRklT6oxwH4pEpSaC71OAxuLC4kFKAu/UpxdTn 1/TiSwEUkrACgsfyVSX3UeuoAo9uKn7cVSX9o2Qg9eK47HPbwd4w3klnMesBKJJ3Anxu Z2W08wZmGh52CqXDE3rsfhZ1WpQJK9WywJw0nvIgYcIxZa/dOPp0xNS4dsHx2KffzhSt 0zHg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=YvFaecF6sOGadVHq0kp5ZkUoYd3jEngKK/y0UTnkptA=; b=ASkvOYGePD2KkxO6EtkTRZXfgt0caNTr3kA4cdGASg+uLzi6UBV1r0ro2rWfbyrPcM uSqONyg+xurvj1azUTJ0Oa9xtAm0gJ7EybO5w5dp55IznXsyNeDXUcTkUrSXLnbcUi2e TAUvH9oOei3KXJNxAZU0lvDMPiHQc2aOd+9c9Gs2Z0oou8pA0POkXMVu5NdUphhOcJ5e +5pURRTwtrRXFIInfz7iH4t/VM616FbqkX/+Ynq0Kq+u2qD6j4JXQZsi9PZUB48ZIwmr elU8OEqpMrpRPh2Lkj2PyEynpZS53WDyg7ru+Cya/peiBCyWx4Peytjh+doiv9741WbV Tx9g== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="fHuz3/Jv"; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1679988828; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date:message-id:reply-to; bh=YvFaecF6sOGadVHq0kp5ZkUoYd3jEngKK/y0UTnkptA=; b=nMMLTfdHTtlavRmUJO/AmbQuDAuqIFKIYbMhrE4r1MzckVxE7k7ktH92aDbXuAZq5/ JL+arsrhAlqkfS/IeIdwoBDT9Jd3k8sfAQ1V2G0exoLkdY49Z0z+6RtO0nCSs97oMyoQ AokY2gxxQKs+5cLwRF6XX991PQ8ittCMIQS9o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679988828; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=YvFaecF6sOGadVHq0kp5ZkUoYd3jEngKK/y0UTnkptA=; b=mLhfjQAv+5CMxSo63oLpz86BAu/h7D7RTPizwRLduL6nlaKmneOeIsOmaC1F+cUsBK B7NqQW/wnje5NDVSbmXRSIebumvps7PFP4Z+R5DPTJV21+iL4E9H7+cFoDhhFXcgOOQt NLkFMu1q4ucPgq7MPemP6MobzdGdFQaq2RcUfI3kcA4GMsb2V0d5enIROmaR0HahRPZ0 xd6azAAj12beTpopjoxJ5XJVkHELe6p9JU3TJFPjugfofF9bWPfgfTXsap43bMUGVrTp 2xaGSADoq8793YVgYOHliiCBbBzmA47OM/m9cPRIioCN4mCgFxkv2HCmYbv+F/AMByXy hscQ== X-Gm-Message-State: AAQBX9eIVH8qxQU5W8pF7j8mePTYwpZ1OkiTjnqWB5jYTw1S2k+xnkV0 AJkClRM71anYy7TOC1CGIG6AOY8uq/cC0d/k X-Google-Smtp-Source: AKy350ZeFHS2hJqNEIWBgSiCtqeijfC1dlLi3Qv2F4j2SZPdXQhLPpbgmywKnk+Rf/Mle0H2mBEV1Q== X-Received: by 2002:a17:906:53ce:b0:931:51c0:7459 with SMTP id p14-20020a17090653ce00b0093151c07459mr7610805ejo.4.1679988828305; Tue, 28 Mar 2023 00:33:48 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a05:6402:4311:b0:4ac:d2bc:e0cb with SMTP id m17-20020a056402431100b004acd2bce0cbls2842522edc.0.-pod-prod-gmail; Tue, 28 Mar 2023 00:33:47 -0700 (PDT) X-Received: by 2002:a05:6402:1a:b0:4fc:9329:bd0c with SMTP id d26-20020a056402001a00b004fc9329bd0cmr13385760edu.12.1679988826741; Tue, 28 Mar 2023 00:33:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1679988826; cv=none; d=google.com; s=arc-20160816; b=Ed8iG03YjZFkbu9kaOSPzUeubAPj22REnwJkXCNgCMa72DHnmRwJihw1w/P71epRI1 easJUJ9ZYvkfpTO79i2/4ZPccCOr2HDNV8P2fJ06BZ//8sAadDci45O7EdYRXKV7+BKV Pc7Ns9+6kZ9v4n0QC5NfARHztlMLRtuQ1dVZovZabLjnPnMYcvtivYQZK+CCQhf+31Bk I3lfk9fXoDhzEnGQu+rVFFQszlTqpM17Gnex+MiWi28HObs9EehUTJe5naswO+92zHiC eMn/VN0lQ9TlGUk1e38exOxX9AzDk8+spZHX+vfn9XEVCo1mhPVDv+8ctemg65273gQm jhIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=81V4WG2Py2oEHuOAf8mFt9n+MMzcYuintrA4k96hyCk=; b=eKnkSiEeLbHrY1/Ma2wBo5+ZX9pM7KvlTOfzu71DNGWrOVwGBBfBJ3aZgBvXsUarDP CHPHwhYkkUXuCQRaCTDqvMg9nVMMtgZTZm+7UcbFJz7ezWRWgO86ELl4EkMvPzLKmlox SYTEt2bz1naTzFMQDg/Ww3aJJ1C4IUW/XN+3P8L3rj+YP/7Hng0MJ275qNU7Hi84rZgh ch281aWp/kCRyOyHsDKA29/dXFsFJlrTVjxJFII8/nnft4FrJYtGTUjdWlVKeJGqN1n4 T/r4yrFxlrUDzkn71V508NQA5V5CCEdf4I5PqG43kWkmtzsuBbDwn5Y19sof2FPQ7iwg JC4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="fHuz3/Jv"; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id v9-20020a509549000000b004c12a990e16sor15349863eda.55.2023.03.28.00.33.46 for (Google Transport Security); Tue, 28 Mar 2023 00:33:46 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a05:6402:712:b0:502:20f0:3ee1 with SMTP id w18-20020a056402071200b0050220f03ee1mr14140124edx.31.1679988826415; Tue, 28 Mar 2023 00:33:46 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-87-0-102-254.retail.telecomitalia.it. [87.0.102.254]) by smtp.gmail.com with ESMTPSA id 15-20020a508e4f000000b004fa99a22c3bsm15478850edx.61.2023.03.28.00.33.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Mar 2023 00:33:46 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Vincent Mailhol , Rob Herring , Amarula patchwork , michael@amarulasolutions.com, Marc Kleine-Budde , Alexandre Torgue , Krzysztof Kozlowski , Dario Binacchi , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Krzysztof Kozlowski , Maxime Coquelin , Paolo Abeni , Rob Herring , Wolfgang Grandegger , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-can@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, netdev@vger.kernel.org Subject: [PATCH v10 2/5] dt-bindings: net: can: add STM32 bxcan DT bindings Date: Tue, 28 Mar 2023 09:33:25 +0200 Message-Id: <20230328073328.3949796-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20230328073328.3949796-1-dario.binacchi@amarulasolutions.com> References: <20230328073328.3949796-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="fHuz3/Jv"; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add documentation of device tree bindings for the STM32 basic extended CAN (bxcan) controller. Signed-off-by: Dario Binacchi Reviewed-by: Rob Herring --- Changes in v10: - Fix errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'. Fix the "st,can-primary" description removing the "Note:" word that caused the failure. Changes in v9: - Replace master/slave terms with primary/secondary. Changes in v5: - Add Rob Herring's Reviewed-by tag. Changes in v4: - Remove "st,stm32f4-bxcan-core" compatible. In this way the can nodes (compatible "st,stm32f4-bxcan") are no longer children of a parent node with compatible "st,stm32f4-bxcan-core". - Add the "st,gcan" property (global can memory) to can nodes which references a "syscon" node containing the shared clock and memory addresses. Changes in v3: - Remove 'Dario Binacchi ' SOB. - Add description to the parent of the two child nodes. - Move "patterProperties:" after "properties: in top level before "required". - Add "clocks" to the "required:" list of the child nodes. Changes in v2: - Change the file name into 'st,stm32-bxcan-core.yaml'. - Rename compatibles: - st,stm32-bxcan-core -> st,stm32f4-bxcan-core - st,stm32-bxcan -> st,stm32f4-bxcan - Rename master property to st,can-master. - Remove the status property from the example. - Put the node child properties as required. .../bindings/net/can/st,stm32-bxcan.yaml | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml diff --git a/Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml b/Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml new file mode 100644 index 000000000000..2bfac2089964 --- /dev/null +++ b/Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/can/st,stm32-bxcan.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics bxCAN controller + +description: STMicroelectronics BxCAN controller for CAN bus + +maintainers: + - Dario Binacchi + +allOf: + - $ref: can-controller.yaml# + +properties: + compatible: + enum: + - st,stm32f4-bxcan + + st,can-primary: + description: + Primary and secondary mode of the bxCAN peripheral is only relevant + if the chip has two CAN peripherals. In that case they share some + of the required logic. + To avoid misunderstandings, it should be noted that ST documentation + uses the terms master/slave instead of primary/secondary. + type: boolean + + reg: + maxItems: 1 + + interrupts: + items: + - description: transmit interrupt + - description: FIFO 0 receive interrupt + - description: FIFO 1 receive interrupt + - description: status change error interrupt + + interrupt-names: + items: + - const: tx + - const: rx0 + - const: rx1 + - const: sce + + resets: + maxItems: 1 + + clocks: + maxItems: 1 + + st,gcan: + $ref: "/schemas/types.yaml#/definitions/phandle-array" + description: + The phandle to the gcan node which allows to access the 512-bytes + SRAM memory shared by the two bxCAN cells (CAN1 primary and CAN2 + secondary) in dual CAN peripheral configuration. + +required: + - compatible + - reg + - interrupts + - resets + - clocks + - st,gcan + +additionalProperties: false + +examples: + - | + #include + #include + + can1: can@40006400 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40006400 0x200>; + interrupts = <19>, <20>, <21>, <22>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F4_APB1_RESET(CAN1)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; + st,can-primary; + st,gcan = <&gcan>; + }; From patchwork Tue Mar 28 07:33:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2818 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f70.google.com (mail-ed1-f70.google.com [209.85.208.70]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 4F3D7414B2 for ; Tue, 28 Mar 2023 09:33:50 +0200 (CEST) Received: by mail-ed1-f70.google.com with SMTP id f15-20020a50a6cf000000b0050050d2326asf16002552edc.18 for ; Tue, 28 Mar 2023 00:33:50 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1679988830; cv=pass; d=google.com; s=arc-20160816; b=b2Lce4sfeNoB5M+rL1O+svFLo8M1U/lVUKG+OjYNY6NwD4RWsaBYrUjVpI+rFeJ8KF Gh8DljPmBwMzFY9sRMpgoW5k8YrWJoA2OTmhP8CGxVQghqWrSdQbsudTJabVGs/nTl+i xb3AnxFHGVI+HT1OU1/TVxJ1ySFnuiF7+nyeddueVTYwcIaUUohovFKzcaYlGVmfRinM l9nagWvhd3VUZqE07WdlG+JU+x5MPl+92H75eKiwSyHsKO8sAHDMtdTkz1NiznrMODCD WV1/H8fna6Kl6sMiscxsTH70kRo4mh8Fci3OXsnSCMZCUttjzq15HoqR5JE7MBmkQBrm mjkA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=zM6XTlemmPpbgqEnCXiwfdu176by6hcaTvwQ7LOjOV4=; b=c02uIHYTsB/SNpGwE9yjuo8kk6R1pqKHeyV26meqqLBefErypnXVIz+dA+ToSLtS6h Cci1pBSD4nI4YBTSFCtAwkcl2InHJEuzWHCIJwfm3xp5tk2URUuqCIGME88X7KflV5tD J633z3oFO5kGE3U4K/38rURK/Q+ZLEer0eVDZ3vLEr1Hz6QrFtg2yX1/ktm25TJqLHQX MAUc/41s55iSKMyTy+UQNQg589N5c0mu2aquW6cJgC+CXL5YOmR3x3Een/xj/XWQ78y8 uNh4/bSotfcwJDZxlnVihQCk1sS1E6CLKjroXuKdY2uH4oBUnmQHsxMszn8Z1tNbyKRY xr+Q== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=Jkq1icJE; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1679988830; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date:message-id:reply-to; bh=zM6XTlemmPpbgqEnCXiwfdu176by6hcaTvwQ7LOjOV4=; b=ZjltoZmsw6wKfdZ+KVULb5gbeTov9rYFmgGgu+7iYcmAaPnQ2QOjT1oBEssErjKVUx 39/jTFblUxhjKQVdN086A90yRudvjEIzWRnuoPRBuEEBDy+ZUA6jqxJPXdJb/n8o4VRo E75CNxqPCgbaDmT6xItVnM/8NU6b6Y6m4tvr0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679988830; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=zM6XTlemmPpbgqEnCXiwfdu176by6hcaTvwQ7LOjOV4=; b=FGrlMTTWOzXbkEXHokbHij0v4pdzPZZOA7fAHvSM4ZAcy48bOXqo7uodA991EBM1JH FSy2IfSu72PrC7z5GmBRX+Uakn8kSGc7Fuy0qvRDFpnjMlvFzbYeYRgGyiE6gY/2bc3m qXCb08RH6uMpuV8kwJ3UAeBljGfa0gObb56olRxoxrBGmlY4uUDgdm7YPks/EjONxQ47 hmWvBcpICR/sFxFm07P0RLE68YGjRN6g7JvwUsHwLr8P8GtrzUt20ECLauoNRIWlXf7+ zGKdTpjJaRwLbgZPjSpmLR2xaXv3Ino28+AAtsUGVvkrjiM5ocWRRixsHskofP1pQLeC Kwrw== X-Gm-Message-State: AAQBX9d6cECTETWmrdVfPFNsxKt40hg5WrwiXOpuN5ql/tls798RlT+l 31/Y5prsTbtkGgAdhzu3ln6CGk2kvOwVfxq1 X-Google-Smtp-Source: AKy350ZSyq00zb5eJUkWdv5DikefUXu6W3eiP9Wnf/p9vgerFCFPk2Lt7JyHyAwkGgQWR1QF3cm1JQ== X-Received: by 2002:a50:d69a:0:b0:4fb:2593:844 with SMTP id r26-20020a50d69a000000b004fb25930844mr7103217edi.2.1679988829859; Tue, 28 Mar 2023 00:33:49 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:906:4718:b0:92b:b0f0:2860 with SMTP id y24-20020a170906471800b0092bb0f02860ls7232044ejq.11.-pod-prod-gmail; Tue, 28 Mar 2023 00:33:48 -0700 (PDT) X-Received: by 2002:a17:907:f90:b0:8fd:2f01:86c0 with SMTP id kb16-20020a1709070f9000b008fd2f0186c0mr16331727ejc.2.1679988828234; Tue, 28 Mar 2023 00:33:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1679988828; cv=none; d=google.com; s=arc-20160816; b=ZECDIeAOc2tHuvwRoxKmrscJQIoSKGD629KNIVVMxEqR2ahN4sY9tvQOlYdW/AzkYM p6etAd6brb0XD20M5pluNJ3pAsimtAMM+Mzwcm3uatawDONTEuMLRMAH4Rqgl8rSHcLT qP/bufThjZSg8vp0/AmLFPm7T/e0xW8lmYRe8RG8hoB5BOn8sYwrbg5anT3LW5cUg6/Z qI8ZHNNudBmBppEaLbdWWFS81KBKmLVyWwO1z/EltjB3eLh2gvu2xYRKWXhGwdukW41X 6PPH6NSvDXcL5T5TTqZ8fjezYh1WMOm0vbOjLvD3zlQXEhQIQNqnhG0zPirPs7Aq1M7O Obag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=2+OmgATyAVN/2E72/iiXhgNbt/jehihFpqYxcu4ydlU=; b=DInKCpe/4xQcCI4pbWLJRzASkq4PBQiYqoi4wutxOWszgK+Mm//Ukx5S/doK77bxOX rzdkYi9s6XZ5c43xfvX7z9osq9L9dlVWjjUqs1vqmafi8QYN+PXIKPNH9u270bLiCBHL S1yOdAwuRYotWmHByIgXjCCRzHZZ1DWdvedTjcb0yGA+Hat7TqNHhW1Z+qCTQ+zsuJmv o4K/zc2hBQE5mFNMPF3Tq0PBQE1L/jue8tBjpYgur1XyrqXpXzPMxu/p2djtX4U1KLU2 b3njI0TpoLtDztntc8H5DwtFc54Ttw174VPxIkDJZkxX36eaDSG3Jz5ZMQFaeelAN5Fz gp7g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=Jkq1icJE; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id sc5-20020a1709078a0500b0093a6b5a6c2fsor11531579ejc.57.2023.03.28.00.33.48 for (Google Transport Security); Tue, 28 Mar 2023 00:33:48 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:906:b351:b0:931:d36f:8965 with SMTP id cd17-20020a170906b35100b00931d36f8965mr16661879ejb.13.1679988828000; Tue, 28 Mar 2023 00:33:48 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-87-0-102-254.retail.telecomitalia.it. [87.0.102.254]) by smtp.gmail.com with ESMTPSA id 15-20020a508e4f000000b004fa99a22c3bsm15478850edx.61.2023.03.28.00.33.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Mar 2023 00:33:47 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Vincent Mailhol , Rob Herring , Amarula patchwork , michael@amarulasolutions.com, Marc Kleine-Budde , Alexandre Torgue , Krzysztof Kozlowski , Dario Binacchi , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v10 3/5] ARM: dts: stm32: add CAN support on stm32f429 Date: Tue, 28 Mar 2023 09:33:26 +0200 Message-Id: <20230328073328.3949796-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20230328073328.3949796-1-dario.binacchi@amarulasolutions.com> References: <20230328073328.3949796-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=Jkq1icJE; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add support for bxcan (Basic eXtended CAN controller) to STM32F429. The chip contains two CAN peripherals, CAN1 the primary and CAN2 the secondary, that share some of the required logic like clock and filters. This means that the secondary CAN can't be used without the primary CAN. Signed-off-by: Dario Binacchi --- (no changes since v9) Changes in v9: - Replace master/slave terms with primary/secondary. Changes in v6: - move can1 node before gcan to keep ordering by address. Changes in v4: - Replace the node can@40006400 (compatible "st,stm32f4-bxcan-core") with the gcan@40006600 node ("sysnode" compatible). The gcan node contains clocks and memory addresses shared by the two can nodes of which it's no longer the parent. - Add to can nodes the "st,gcan" property (global can memory) which references the gcan@40006600 node ("sysnode compatibble). Changes in v3: - Remove 'Dario Binacchi ' SOB. - Add "clocks" to can@0 node. arch/arm/boot/dts/stm32f429.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index c31ceb821231..c9e05e3540d6 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -362,6 +362,35 @@ i2c3: i2c@40005c00 { status = "disabled"; }; + can1: can@40006400 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40006400 0x200>; + interrupts = <19>, <20>, <21>, <22>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F4_APB1_RESET(CAN1)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; + st,can-primary; + st,gcan = <&gcan>; + status = "disabled"; + }; + + gcan: gcan@40006600 { + compatible = "st,stm32f4-gcan", "syscon"; + reg = <0x40006600 0x200>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; + }; + + can2: can@40006800 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40006800 0x200>; + interrupts = <63>, <64>, <65>, <66>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F4_APB1_RESET(CAN2)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>; + st,gcan = <&gcan>; + status = "disabled"; + }; + dac: dac@40007400 { compatible = "st,stm32f4-dac-core"; reg = <0x40007400 0x400>; From patchwork Tue Mar 28 07:33:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2819 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f70.google.com (mail-ed1-f70.google.com [209.85.208.70]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id DEEFD414B4 for ; Tue, 28 Mar 2023 09:33:51 +0200 (CEST) Received: by mail-ed1-f70.google.com with SMTP id t14-20020a056402240e00b004fb36e6d670sf16088413eda.5 for ; Tue, 28 Mar 2023 00:33:51 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1679988831; cv=pass; d=google.com; s=arc-20160816; b=JO5cnjtsy/SWCVwQKBIW/ewzHbVgK6i2Y/HKi7BEUClUkQt6N+XVEr3E9B/LH7ZN2+ iMVWzK9dvlBjH+BubnNPXeQazTBJ0f2JFm9pau2Bvy5yzlkRvHqQLtL0KY7YShrQ3J8r Nu5dDT8/arrjQxMUJiOgqAN8prBjZOqTSYxTz4FELnHcYQj1dpZqQrZk4Ul4s0ecQRdw tGI9hZmJxrq9FECLRuLRpIktqre2XAHIS3EiKkH+g0U8ZzE6j2Dt38zVnjKG5k8VzXrE J20pgBRrjN+3JRKkLBdewlt71ZmJK/yyyzxgt5zsPKTULWtdQHtLdzh9P7VprKaWjiEt E3NQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=SfdrfT03OSwzGLgYfJRpTJI75xsr8u1PQr9DsxijOMI=; b=LAUerJSgMcyPqbZnmX0orMUIi1FkmooZzJB4uDb+H0ir4sr6StIh0j2Z1A+3pLOE5X IG8GHvOoYS5O3ibCEW9zJiN6/de6Vi4C3GzZ5D0d/6hFpQnnSGGr18Qsk3ZbLEdaYE36 o4/XXEZj/PE+cJ7jQcodPiV3YwKWgI/YfVM8NqRxQ/ph4UN2XYQ5tkj6ZVuXNpv8lq/t U8PDbvSl+7zDxQQwYR93/Xteyxlmgl4L/6RW7MdbW3xzIs13O8lUc98cQSMBYBrqEdMu JMgIMgyer9VSEOsrW91VyLFVXy7jUGjMgXYUwzWbZNrbLqqvuPmiO3Wm2bCxaStQgYc5 ZJyA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="fInw/jj9"; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1679988831; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date:message-id:reply-to; bh=SfdrfT03OSwzGLgYfJRpTJI75xsr8u1PQr9DsxijOMI=; b=DJPLoKdDfpOmnNmHtXtPon/fWJ30+/G5bG496cKq7YROeAzXxejvtv7j6GEJ3KhKcA rp2+h14lRj1Y78hHthdzgDQ0Xin7Ym6S/PX/x/hRlYBIyyJWV314Az7/nVNgfm4Hg0Ll lD1wnouVMlW3GUsYMty9LWSooHSlInml3hIqI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679988831; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=SfdrfT03OSwzGLgYfJRpTJI75xsr8u1PQr9DsxijOMI=; b=zwC7iqjNUuoQ8xTNPdLTIqPya47DHRT/nSwSxqRv7yf1lI1BAnurL90LLgvVfco2pc nwofAS45kdD86cW5CZ4na+WfHTTgm/wBrvSNUnOZpYz05lbgcyJcpicjvMBuM0fAI0Gp Y1JjO+AiwXAAw4cb5uM+uGJWZLhZ+aW2xXhZu0VU/XqIrBMO7ovs1u0T1RYtXW7eb9Kj YYow4dBjCzgJ1SoOFymXdo43FduLwQB4gz3qPh6HkH2I2l9uHGtEPVj4aXDYfeYdPiY/ fx+vQ9IJEZkm1ObxSAc52wKphpuE88oCrWyE2w1PQiQOai2zQxaklPvG654c6me+jAL1 ffEA== X-Gm-Message-State: AAQBX9esgIgdLGhDdUvK/0H+a/J4VpNZa2hQXqCqkESMADLeE2cXcaHE eNucnqzO3o4v1CPmV1SIO8Gin8In2hRkV/dR X-Google-Smtp-Source: AKy350YtwMXv3m0/p0fntDynhl5PUbIo3iLH7wN3XN1Gm6U0O5DmPy2/DjTa5qqT64pOfuHvcmEesg== X-Received: by 2002:a50:9f4e:0:b0:4c2:1a44:642e with SMTP id b72-20020a509f4e000000b004c21a44642emr7295684edf.5.1679988831489; Tue, 28 Mar 2023 00:33:51 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a05:6402:4499:b0:502:26b1:64e0 with SMTP id er25-20020a056402449900b0050226b164e0ls2844049edb.1.-pod-prod-gmail; Tue, 28 Mar 2023 00:33:50 -0700 (PDT) X-Received: by 2002:aa7:c906:0:b0:4fd:2aac:d480 with SMTP id b6-20020aa7c906000000b004fd2aacd480mr16786672edt.21.1679988829802; Tue, 28 Mar 2023 00:33:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1679988829; cv=none; d=google.com; s=arc-20160816; b=CY7GPk9tqTjRfWSTKmbg5DpRXsKH6SZ6OEz9gOQWh6bPpS166DiyAm8/Xu1e0MN4a8 1d0WOUz/kW3S9vncqTJf5ETSV05DiU7xEyGpez67J/xgqbtsn87kFbUF4nXk/+sQs9Tc jYryzN3a9h6Ta/W42/lfU7gm5NcLoTTiFn0JCFQdImdxiNkyaZDYHFA7BLn7H9RmTaMG bnj1UGuX37BtWE4lC6lkH7ON/GkiIgFmpkuB8rFW5B9eCI1pTMkH2wCwH8JBu3OvfK8n DIeUKxPMj1bl0osyW6npAEEFfdHxIeYrzHN5cTEMAAXRC60U4a13IcWVTZIGEZTlr6J2 bmwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=QV3iGa8KiUlr1LClhXl1D1BGw0maVF3hcUmABXx2qKM=; b=yRswC36H5cdMZQpC5WIefKiLYKrLtSRy3djmS29PYiGutGsPGq1pG7T08XMu0Wa5+l jT+Dgk/iqpj2zEEkHCpfGl2EDrIWLIDfkJluey0EDpV7GH+5irqnP1brEty03EaUydeE v1BHfNVtGS3wtSZ5AeTVhQx33J7SY5odnhKzKm4BuM90SFJmd52NZf0pkBB59vFGiqIw CGzsHr/tGE1ptYRZcgbFlrE3yD68sviAJmz32ltCadIFIZnwiWymJC7pZQavS/dGd8xz qQ/YKiEc7dfa2HoR5Zfb/R5vCcapyAuEWfWazbcv5zoyNp7YNJI4ZuVCeXEEOayllzKQ 4Fkw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="fInw/jj9"; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id r12-20020a50aacc000000b005021d27bc18sor5364023edc.26.2023.03.28.00.33.49 for (Google Transport Security); Tue, 28 Mar 2023 00:33:49 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:aa7:db92:0:b0:4fd:2346:7225 with SMTP id u18-20020aa7db92000000b004fd23467225mr15202535edt.34.1679988829563; Tue, 28 Mar 2023 00:33:49 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-87-0-102-254.retail.telecomitalia.it. [87.0.102.254]) by smtp.gmail.com with ESMTPSA id 15-20020a508e4f000000b004fa99a22c3bsm15478850edx.61.2023.03.28.00.33.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Mar 2023 00:33:49 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Vincent Mailhol , Rob Herring , Amarula patchwork , michael@amarulasolutions.com, Marc Kleine-Budde , Alexandre Torgue , Krzysztof Kozlowski , Dario Binacchi , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v10 4/5] ARM: dts: stm32: add pin map for CAN controller on stm32f4 Date: Tue, 28 Mar 2023 09:33:27 +0200 Message-Id: <20230328073328.3949796-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20230328073328.3949796-1-dario.binacchi@amarulasolutions.com> References: <20230328073328.3949796-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="fInw/jj9"; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add pin configurations for using CAN controller on stm32f469-disco board. They are located on the Arduino compatible connector CN5 (CAN1) and on the extension connector CN12 (CAN2). Signed-off-by: Dario Binacchi --- (no changes since v3) Changes in v3: - Remove 'Dario Binacchi ' SOB. - Remove a blank line. Changes in v2: - Remove a blank line. arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 30 ++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi index 4523c63475e4..3bb812d6399e 100644 --- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi @@ -447,6 +447,36 @@ pins2 { slew-rate = <2>; }; }; + + can1_pins_a: can1-0 { + pins1 { + pinmux = ; /* CAN1_TX */ + }; + pins2 { + pinmux = ; /* CAN1_RX */ + bias-pull-up; + }; + }; + + can2_pins_a: can2-0 { + pins1 { + pinmux = ; /* CAN2_TX */ + }; + pins2 { + pinmux = ; /* CAN2_RX */ + bias-pull-up; + }; + }; + + can2_pins_b: can2-1 { + pins1 { + pinmux = ; /* CAN2_TX */ + }; + pins2 { + pinmux = ; /* CAN2_RX */ + bias-pull-up; + }; + }; }; }; }; From patchwork Tue Mar 28 07:33:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2820 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f70.google.com (mail-ed1-f70.google.com [209.85.208.70]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id BDB35414B2 for ; Tue, 28 Mar 2023 09:33:53 +0200 (CEST) Received: by mail-ed1-f70.google.com with SMTP id t14-20020a056402240e00b004fb36e6d670sf16088560eda.5 for ; Tue, 28 Mar 2023 00:33:53 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1679988833; cv=pass; d=google.com; s=arc-20160816; b=G3JOD2elv8GsD0LkdnIz1N+AQqHMUqNuSxpokAGga4jG+emWgic5bomWxh/EMmUNuH 4cJcjjABpoa+fFpVB2K6ncxgzRgjSjk4pjePRkOmZX8qrT0BNE/1yeU3sSl2fN06QOBX BJlh20tJeb3UC1hQCHPumJRcZy+t9sgzlIlMrMPBSbgheW2tns76f92VXintHPX/nCfr +jBhLoNHY8YV5sUycMjs2BHAhwK35CEGxNHl2bA3fxFguj7MXPUsXx6iG7j5FuoHqZfw PXQT5pd4MTvaMROD8q0qoEv9/IrdlHGg5dFrDWEVwzyE0uEMZSWX52+bJnkldrOH91Ae k0tw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Fi0BPqH3phZ0ckLtTsRME/VIgxQSk6/y4IBf3g/JrCw=; b=VSLEEei3O4c6Kw6DT6zi9VzSaN7g5NfoN+dY3Bqf5VrOfh6dXrxgCwqvEN2e6toKZb dfCNMb9b5pVidN36q4KikQPxAVBq99WP8tpoiQuDROdZroYkFUNcyVkhbf8hi8m9lqea njHd+a8yxBb4OXfkhcmDiwD9k8Qb3hvJHvNBYBJQ7P6DY1QxVGA4JG6J2+elJHJga0Cz NcXNOX296rioDRwNPxizz+mgiY1m2LfCXsBdHx4TwQEh0SqWLsDBkQpScZGQclHCpZa6 Nsda6hpst1Uk+2iKDIb5e6vLkDklqlwCd4Pu0awRe+d1ISnqJoOTA8WMfNgWHS64G0J5 U1eg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=bVLudKGa; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1679988833; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date:message-id:reply-to; bh=Fi0BPqH3phZ0ckLtTsRME/VIgxQSk6/y4IBf3g/JrCw=; b=J3ejUFOHAV2xwkrgWEIfjvzv0dZBaquxA0v0zpFcnfvlva4AUZDvmNuKLJJk8BlQ4b /5JP/X3TKgD4yRq2zV1j2Mtsv3CGUcPLghiCi9CqOib+fxaJ5VXqo7+UfnCDX2ovo3el MgR9MZr30n4ktCFunBpiER/jd+9P9XTSZWG1A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679988833; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Fi0BPqH3phZ0ckLtTsRME/VIgxQSk6/y4IBf3g/JrCw=; b=BidN04EHK6EV3toEo8QzdJxrBZEOx9Fe6Idspyr/xceu3j8ltLVMn2D2WhnNxv7BA/ GWJfA2aMH8wbbhkdCkt755J67+Bj4+uW4HlA9vt9mkvNH05dni38pHXKVXBVomzg2K1/ 2Gp72S3KxkucKLByaVHNXxhSrW6lHF7q1gKvGeSoLh9PoxrfSTzEMQcJa09f/Q7Q1lR+ yd8L3KZCaiQ+hSW89pkbETEPWF7R5ohuMfdW+IGkUuK2J5/EqUqiMS+sJAG4iIcKJI3d bmuamtSi1E8L07iN7yYr7IWJQ6aJ4JKbMksJlbwT2cwgbdZPCDsL6//YDq3evm2ldDY8 wNBQ== X-Gm-Message-State: AAQBX9drhzmN0dSI634I3PJaKZYSkc0PWqkS4peWCysHbNdidvLuKBEA JypZckcPCE0CrLbXSDnvlPvyUWTo X-Google-Smtp-Source: AKy350ZvIYwoLi8HX+9M+/VEM8cyJ1CciCAwMxRrB1vBAmkbz60aUn7jRHwXXGEUYkZIY9/VSsFJcA== X-Received: by 2002:a17:907:7e95:b0:93e:9362:75fd with SMTP id qb21-20020a1709077e9500b0093e936275fdmr6632806ejc.9.1679988833551; Tue, 28 Mar 2023 00:33:53 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:906:4718:b0:92b:b0f0:2860 with SMTP id y24-20020a170906471800b0092bb0f02860ls7232196ejq.11.-pod-prod-gmail; Tue, 28 Mar 2023 00:33:52 -0700 (PDT) X-Received: by 2002:a17:907:20ee:b0:930:6e31:3c11 with SMTP id rh14-20020a17090720ee00b009306e313c11mr15696311ejb.70.1679988831643; Tue, 28 Mar 2023 00:33:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1679988831; cv=none; d=google.com; s=arc-20160816; b=UjVOila8Gwg454B3dwuJfi86AG5tsl2VJojrSkwLXkO79jteXMoMS5//Yi2NAJBhjl 3WN+RR3Y6xOrdaR57NuSoK2668r5I/z01SZhYkJIP5LL2nEwH56OIZW8RwAnNm4QuEOt HLoUSIrJW1WdYUUsK0yzk94pVO9rwpAmy0peNSRgvQYysGw2/xjXzOGSaXv/QG4F4tsr Wh8OIwf0hsGiCkA5dPj1ST6zIYAmjgUcFIkHYuY/SXiM8kfSDK+kl+YB96lueJScjKhh 3nRy+pr6mge4616FXVJ490xr59UtYocRMucRYgSOgxyHDIC/zn1hd8ji9R8wtV9pLHV4 LGJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=cG47qVDFed7zrRNKrINZ6x/eaO1dWkW9sCm9lnLwmBA=; b=jMONEp3Awb+KQ++XgutB82ekiALeKkNEcrzQoRRsn3BXm4RMPOJAeIuB8Gka/v0awq sQz9e0bBPvkiZoj/u2lrM+FFc7WUIF8g0Ng9a/cBokyVf06rhUGAL+XzZP4fNWUdEXEM jykgwB7Xxv4XpmfFhMDt8X4wWtkiaugKKeEpamtLMdxaGgGUYZ4Dr+ApRu120oU65ICT yR9rJ1oDjoxHFYpSH9gi0t6REkw5l06i+C9GNrgLyY90bcn0I/Ah0NvrM5QQo7sW6ycV qK/aGQRHF1VsdEMMDmf2TTNRt+27zbtFYL1//aqeKOoaejp9caaXXz1NzloD3TSBFoPK LjLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=bVLudKGa; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id nc17-20020a1709071c1100b0093fcc6295f4sor3875970ejc.53.2023.03.28.00.33.51 for (Google Transport Security); Tue, 28 Mar 2023 00:33:51 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:906:3a45:b0:932:8dc:5bf4 with SMTP id a5-20020a1709063a4500b0093208dc5bf4mr15424865ejf.61.1679988831250; Tue, 28 Mar 2023 00:33:51 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-87-0-102-254.retail.telecomitalia.it. [87.0.102.254]) by smtp.gmail.com with ESMTPSA id 15-20020a508e4f000000b004fa99a22c3bsm15478850edx.61.2023.03.28.00.33.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Mar 2023 00:33:50 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Vincent Mailhol , Rob Herring , Amarula patchwork , michael@amarulasolutions.com, Marc Kleine-Budde , Alexandre Torgue , Krzysztof Kozlowski , Dario Binacchi , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Wolfgang Grandegger , linux-can@vger.kernel.org, netdev@vger.kernel.org Subject: [PATCH v10 5/5] can: bxcan: add support for ST bxCAN controller Date: Tue, 28 Mar 2023 09:33:28 +0200 Message-Id: <20230328073328.3949796-6-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20230328073328.3949796-1-dario.binacchi@amarulasolutions.com> References: <20230328073328.3949796-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=bVLudKGa; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add support for the basic extended CAN controller (bxCAN) found in many low- to middle-end STM32 SoCs. It supports the Basic Extended CAN protocol versions 2.0A and B with a maximum bit rate of 1 Mbit/s. The controller supports two channels (CAN1 as primary and CAN2 as secondary) and the driver can enable either or both of the channels. They share some of the required logic (e. g. clocks and filters), and that means you cannot use the secondary CAN without enabling some hardware resources managed by the primary CAN. Each channel has 3 transmit mailboxes, 2 receive FIFOs with 3 stages and 28 scalable filter banks. It also manages 4 dedicated interrupt vectors: - transmit interrupt - FIFO 0 receive interrupt - FIFO 1 receive interrupt - status change error interrupt Driver uses all 3 available mailboxes for transmission and FIFO 0 for reception. Rx filter rules are configured to the minimum. They accept all messages and assign filter 0 to CAN1 and filter 14 to CAN2 in identifier mask mode with 32 bits width. It enables and uses transmit, receive buffers for FIFO 0 and error and status change interrupts. Signed-off-by: Dario Binacchi Reviewed-by: Vincent Mailhol --- Changes in v10: - Slightly change the note text at the top of the driver module. No functional changes. Changes in v9: - Replace master/slave terms with primary/secondary. Changes in v8: - Do not enable the clock in probe and enable/disable it in open/close. - Return IRQ_NONE if no IRQ is active. Changes in v7: - Add Vincent Mailhol's Reviewed-by tag. - Remove all unused macros for reading/writing the controller registers. - Add CAN_ERR_CNT flag to notify availability of error counter. - Move the "break" before the newline in the switch/case statements. - Print the mnemotechnic instead of the error value in each netdev_err(). - Remove the debug print for timings parameter. - Do not copy the data if CAN_RTR_FLAG is set in bxcan_start_xmit(). - Populate ndev->ethtool_ops with the default timestamp info. Changes in v5: - Put static in front of bxcan_enable_filters() definition. Changes in v4: - Add "dt-bindings: arm: stm32: add compatible for syscon gcan node" patch. - Drop the core driver. Thus bxcan-drv.c has been renamed to bxcan.c and moved to the drivers/net/can folder. The drivers/net/can/bxcan directory has therefore been removed. - Use the regmap_*() functions to access the shared memory registers. - Use spinlock to protect bxcan_rmw(). - Use 1 space, instead of tabs, in the macros definition. - Drop clock ref-counting. - Drop unused code. - Drop the _SHIFT macros and use FIELD_GET()/FIELD_PREP() directly. - Add BXCAN_ prefix to lec error codes. - Add the macro BXCAN_RX_MB_NUM. - Enable time triggered mode and use can_rx_offload(). - Use readx_poll_timeout() in function with timeouts. - Loop from tail to head in bxcan_tx_isr(). - Check bits of tsr register instead of pkts variable in bxcan_tx_isr(). - Don't return from bxcan_handle_state_change() if skb/cf are NULL. - Enable/disable the generation of the bus error interrupt depending on can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING. - Don't return from bxcan_handle_bus_err() if skb is NULL. - Drop statistics updating from bxcan_handle_bus_err(). - Add an empty line in front of 'return IRQ_HANDLED;' - Rename bxcan_start() to bxcan_chip_start(). - Rename bxcan_stop() to bxcan_chip_stop(). - Disable all IRQs in bxcan_chip_stop(). - Rename bxcan_close() to bxcan_ndo_stop(). - Use writel instead of bxcan_rmw() to update the dlc register. Changes in v3: - Remove 'Dario Binacchi ' SOB. - Fix the documentation file path in the MAINTAINERS entry. - Do not increment the "stats->rx_bytes" if the frame is remote. - Remove pr_debug() call from bxcan_rmw(). Changes in v2: - Fix sparse errors. - Create a MAINTAINERS entry. - Remove the print of the registers address. - Remove the volatile keyword from bxcan_rmw(). - Use tx ring algorithm to manage tx mailboxes. - Use can_{get|put}_echo_skb(). - Update DT properties. MAINTAINERS | 7 + drivers/net/can/Kconfig | 12 + drivers/net/can/Makefile | 1 + drivers/net/can/bxcan.c | 1098 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 1118 insertions(+) create mode 100644 drivers/net/can/bxcan.c diff --git a/MAINTAINERS b/MAINTAINERS index 1dc8bd26b6cf..4ddad698ed21 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4431,6 +4431,13 @@ S: Maintained F: drivers/scsi/BusLogic.* F: drivers/scsi/FlashPoint.* +BXCAN CAN NETWORK DRIVER +M: Dario Binacchi +L: linux-can@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml +F: drivers/net/can/bxcan.c + C-MEDIA CMI8788 DRIVER M: Clemens Ladisch L: alsa-devel@alsa-project.org (moderated for non-subscribers) diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig index cd34e8dc9394..3ceccafd701b 100644 --- a/drivers/net/can/Kconfig +++ b/drivers/net/can/Kconfig @@ -93,6 +93,18 @@ config CAN_AT91 This is a driver for the SoC CAN controller in Atmel's AT91SAM9263 and AT91SAM9X5 processors. +config CAN_BXCAN + tristate "STM32 Basic Extended CAN (bxCAN) devices" + depends on OF || ARCH_STM32 || COMPILE_TEST + depends on HAS_IOMEM + select CAN_RX_OFFLOAD + help + Say yes here to build support for the STMicroelectronics STM32 basic + extended CAN Controller (bxCAN). + + This driver can also be built as a module. If so, the module + will be called bxcan. + config CAN_CAN327 tristate "Serial / USB serial ELM327 based OBD-II Interfaces (can327)" depends on TTY diff --git a/drivers/net/can/Makefile b/drivers/net/can/Makefile index 52b0f6e10668..ff8f76295d13 100644 --- a/drivers/net/can/Makefile +++ b/drivers/net/can/Makefile @@ -14,6 +14,7 @@ obj-y += usb/ obj-y += softing/ obj-$(CONFIG_CAN_AT91) += at91_can.o +obj-$(CONFIG_CAN_BXCAN) += bxcan.o obj-$(CONFIG_CAN_CAN327) += can327.o obj-$(CONFIG_CAN_CC770) += cc770/ obj-$(CONFIG_CAN_C_CAN) += c_can/ diff --git a/drivers/net/can/bxcan.c b/drivers/net/can/bxcan.c new file mode 100644 index 000000000000..e26ccd41e3cb --- /dev/null +++ b/drivers/net/can/bxcan.c @@ -0,0 +1,1098 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// bxcan.c - STM32 Basic Extended CAN controller driver +// +// Copyright (c) 2022 Dario Binacchi +// +// NOTE: The ST documentation uses the terms master/slave instead of +// primary/secondary. + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define BXCAN_NAPI_WEIGHT 3 +#define BXCAN_TIMEOUT_US 10000 + +#define BXCAN_RX_MB_NUM 2 +#define BXCAN_TX_MB_NUM 3 + +/* Primary control register (MCR) bits */ +#define BXCAN_MCR_RESET BIT(15) +#define BXCAN_MCR_TTCM BIT(7) +#define BXCAN_MCR_ABOM BIT(6) +#define BXCAN_MCR_AWUM BIT(5) +#define BXCAN_MCR_NART BIT(4) +#define BXCAN_MCR_RFLM BIT(3) +#define BXCAN_MCR_TXFP BIT(2) +#define BXCAN_MCR_SLEEP BIT(1) +#define BXCAN_MCR_INRQ BIT(0) + +/* Primary status register (MSR) bits */ +#define BXCAN_MSR_ERRI BIT(2) +#define BXCAN_MSR_SLAK BIT(1) +#define BXCAN_MSR_INAK BIT(0) + +/* Transmit status register (TSR) bits */ +#define BXCAN_TSR_RQCP2 BIT(16) +#define BXCAN_TSR_RQCP1 BIT(8) +#define BXCAN_TSR_RQCP0 BIT(0) + +/* Receive FIFO 0 register (RF0R) bits */ +#define BXCAN_RF0R_RFOM0 BIT(5) +#define BXCAN_RF0R_FMP0_MASK GENMASK(1, 0) + +/* Interrupt enable register (IER) bits */ +#define BXCAN_IER_SLKIE BIT(17) +#define BXCAN_IER_WKUIE BIT(16) +#define BXCAN_IER_ERRIE BIT(15) +#define BXCAN_IER_LECIE BIT(11) +#define BXCAN_IER_BOFIE BIT(10) +#define BXCAN_IER_EPVIE BIT(9) +#define BXCAN_IER_EWGIE BIT(8) +#define BXCAN_IER_FOVIE1 BIT(6) +#define BXCAN_IER_FFIE1 BIT(5) +#define BXCAN_IER_FMPIE1 BIT(4) +#define BXCAN_IER_FOVIE0 BIT(3) +#define BXCAN_IER_FFIE0 BIT(2) +#define BXCAN_IER_FMPIE0 BIT(1) +#define BXCAN_IER_TMEIE BIT(0) + +/* Error status register (ESR) bits */ +#define BXCAN_ESR_REC_MASK GENMASK(31, 24) +#define BXCAN_ESR_TEC_MASK GENMASK(23, 16) +#define BXCAN_ESR_LEC_MASK GENMASK(6, 4) +#define BXCAN_ESR_BOFF BIT(2) +#define BXCAN_ESR_EPVF BIT(1) +#define BXCAN_ESR_EWGF BIT(0) + +/* Bit timing register (BTR) bits */ +#define BXCAN_BTR_SILM BIT(31) +#define BXCAN_BTR_LBKM BIT(30) +#define BXCAN_BTR_SJW_MASK GENMASK(25, 24) +#define BXCAN_BTR_TS2_MASK GENMASK(22, 20) +#define BXCAN_BTR_TS1_MASK GENMASK(19, 16) +#define BXCAN_BTR_BRP_MASK GENMASK(9, 0) + +/* TX mailbox identifier register (TIxR, x = 0..2) bits */ +#define BXCAN_TIxR_STID_MASK GENMASK(31, 21) +#define BXCAN_TIxR_EXID_MASK GENMASK(31, 3) +#define BXCAN_TIxR_IDE BIT(2) +#define BXCAN_TIxR_RTR BIT(1) +#define BXCAN_TIxR_TXRQ BIT(0) + +/* TX mailbox data length and time stamp register (TDTxR, x = 0..2 bits */ +#define BXCAN_TDTxR_DLC_MASK GENMASK(3, 0) + +/* RX FIFO mailbox identifier register (RIxR, x = 0..1 */ +#define BXCAN_RIxR_STID_MASK GENMASK(31, 21) +#define BXCAN_RIxR_EXID_MASK GENMASK(31, 3) +#define BXCAN_RIxR_IDE BIT(2) +#define BXCAN_RIxR_RTR BIT(1) + +/* RX FIFO mailbox data length and timestamp register (RDTxR, x = 0..1) bits */ +#define BXCAN_RDTxR_TIME_MASK GENMASK(31, 16) +#define BXCAN_RDTxR_DLC_MASK GENMASK(3, 0) + +#define BXCAN_FMR_REG 0x00 +#define BXCAN_FM1R_REG 0x04 +#define BXCAN_FS1R_REG 0x0c +#define BXCAN_FFA1R_REG 0x14 +#define BXCAN_FA1R_REG 0x1c +#define BXCAN_FiR1_REG(b) (0x40 + (b) * 8) +#define BXCAN_FiR2_REG(b) (0x44 + (b) * 8) + +#define BXCAN_FILTER_ID(primary) (primary ? 0 : 14) + +/* Filter primary register (FMR) bits */ +#define BXCAN_FMR_CANSB_MASK GENMASK(13, 8) +#define BXCAN_FMR_FINIT BIT(0) + +enum bxcan_lec_code { + BXCAN_LEC_NO_ERROR = 0, + BXCAN_LEC_STUFF_ERROR, + BXCAN_LEC_FORM_ERROR, + BXCAN_LEC_ACK_ERROR, + BXCAN_LEC_BIT1_ERROR, + BXCAN_LEC_BIT0_ERROR, + BXCAN_LEC_CRC_ERROR, + BXCAN_LEC_UNUSED +}; + +/* Structure of the message buffer */ +struct bxcan_mb { + u32 id; /* can identifier */ + u32 dlc; /* data length control and timestamp */ + u32 data[2]; /* data */ +}; + +/* Structure of the hardware registers */ +struct bxcan_regs { + u32 mcr; /* 0x00 - primary control */ + u32 msr; /* 0x04 - primary status */ + u32 tsr; /* 0x08 - transmit status */ + u32 rf0r; /* 0x0c - FIFO 0 */ + u32 rf1r; /* 0x10 - FIFO 1 */ + u32 ier; /* 0x14 - interrupt enable */ + u32 esr; /* 0x18 - error status */ + u32 btr; /* 0x1c - bit timing*/ + u32 reserved0[88]; /* 0x20 */ + struct bxcan_mb tx_mb[BXCAN_TX_MB_NUM]; /* 0x180 - tx mailbox */ + struct bxcan_mb rx_mb[BXCAN_RX_MB_NUM]; /* 0x1b0 - rx mailbox */ +}; + +struct bxcan_priv { + struct can_priv can; + struct can_rx_offload offload; + struct device *dev; + struct net_device *ndev; + + struct bxcan_regs __iomem *regs; + struct regmap *gcan; + int tx_irq; + int sce_irq; + bool primary; + struct clk *clk; + spinlock_t rmw_lock; /* lock for read-modify-write operations */ + unsigned int tx_head; + unsigned int tx_tail; + u32 timestamp; +}; + +static const struct can_bittiming_const bxcan_bittiming_const = { + .name = KBUILD_MODNAME, + .tseg1_min = 1, + .tseg1_max = 16, + .tseg2_min = 1, + .tseg2_max = 8, + .sjw_max = 4, + .brp_min = 1, + .brp_max = 1024, + .brp_inc = 1, +}; + +static inline void bxcan_rmw(struct bxcan_priv *priv, void __iomem *addr, + u32 clear, u32 set) +{ + unsigned long flags; + u32 old, val; + + spin_lock_irqsave(&priv->rmw_lock, flags); + old = readl(addr); + val = (old & ~clear) | set; + if (val != old) + writel(val, addr); + + spin_unlock_irqrestore(&priv->rmw_lock, flags); +} + +static void bxcan_disable_filters(struct bxcan_priv *priv, bool primary) +{ + unsigned int fid = BXCAN_FILTER_ID(primary); + u32 fmask = BIT(fid); + + regmap_update_bits(priv->gcan, BXCAN_FA1R_REG, fmask, 0); +} + +static void bxcan_enable_filters(struct bxcan_priv *priv, bool primary) +{ + unsigned int fid = BXCAN_FILTER_ID(primary); + u32 fmask = BIT(fid); + + /* Filter settings: + * + * Accept all messages. + * Assign filter 0 to CAN1 and filter 14 to CAN2 in identifier + * mask mode with 32 bits width. + */ + + /* Enter filter initialization mode and assing filters to CAN + * controllers. + */ + regmap_update_bits(priv->gcan, BXCAN_FMR_REG, + BXCAN_FMR_CANSB_MASK | BXCAN_FMR_FINIT, + FIELD_PREP(BXCAN_FMR_CANSB_MASK, 14) | + BXCAN_FMR_FINIT); + + /* Deactivate filter */ + regmap_update_bits(priv->gcan, BXCAN_FA1R_REG, fmask, 0); + + /* Two 32-bit registers in identifier mask mode */ + regmap_update_bits(priv->gcan, BXCAN_FM1R_REG, fmask, 0); + + /* Single 32-bit scale configuration */ + regmap_update_bits(priv->gcan, BXCAN_FS1R_REG, fmask, fmask); + + /* Assign filter to FIFO 0 */ + regmap_update_bits(priv->gcan, BXCAN_FFA1R_REG, fmask, 0); + + /* Accept all messages */ + regmap_write(priv->gcan, BXCAN_FiR1_REG(fid), 0); + regmap_write(priv->gcan, BXCAN_FiR2_REG(fid), 0); + + /* Activate filter */ + regmap_update_bits(priv->gcan, BXCAN_FA1R_REG, fmask, fmask); + + /* Exit filter initialization mode */ + regmap_update_bits(priv->gcan, BXCAN_FMR_REG, BXCAN_FMR_FINIT, 0); +} + +static inline u8 bxcan_get_tx_head(const struct bxcan_priv *priv) +{ + return priv->tx_head % BXCAN_TX_MB_NUM; +} + +static inline u8 bxcan_get_tx_tail(const struct bxcan_priv *priv) +{ + return priv->tx_tail % BXCAN_TX_MB_NUM; +} + +static inline u8 bxcan_get_tx_free(const struct bxcan_priv *priv) +{ + return BXCAN_TX_MB_NUM - (priv->tx_head - priv->tx_tail); +} + +static bool bxcan_tx_busy(const struct bxcan_priv *priv) +{ + if (bxcan_get_tx_free(priv) > 0) + return false; + + netif_stop_queue(priv->ndev); + + /* Memory barrier before checking tx_free (head and tail) */ + smp_mb(); + + if (bxcan_get_tx_free(priv) == 0) { + netdev_dbg(priv->ndev, + "Stopping tx-queue (tx_head=0x%08x, tx_tail=0x%08x, len=%d).\n", + priv->tx_head, priv->tx_tail, + priv->tx_head - priv->tx_tail); + + return true; + } + + netif_start_queue(priv->ndev); + + return false; +} + +static int bxcan_chip_softreset(struct bxcan_priv *priv) +{ + struct bxcan_regs __iomem *regs = priv->regs; + u32 value; + + bxcan_rmw(priv, ®s->mcr, 0, BXCAN_MCR_RESET); + return readx_poll_timeout(readl, ®s->msr, value, + value & BXCAN_MSR_SLAK, BXCAN_TIMEOUT_US, + USEC_PER_SEC); +} + +static int bxcan_enter_init_mode(struct bxcan_priv *priv) +{ + struct bxcan_regs __iomem *regs = priv->regs; + u32 value; + + bxcan_rmw(priv, ®s->mcr, 0, BXCAN_MCR_INRQ); + return readx_poll_timeout(readl, ®s->msr, value, + value & BXCAN_MSR_INAK, BXCAN_TIMEOUT_US, + USEC_PER_SEC); +} + +static int bxcan_leave_init_mode(struct bxcan_priv *priv) +{ + struct bxcan_regs __iomem *regs = priv->regs; + u32 value; + + bxcan_rmw(priv, ®s->mcr, BXCAN_MCR_INRQ, 0); + return readx_poll_timeout(readl, ®s->msr, value, + !(value & BXCAN_MSR_INAK), BXCAN_TIMEOUT_US, + USEC_PER_SEC); +} + +static int bxcan_enter_sleep_mode(struct bxcan_priv *priv) +{ + struct bxcan_regs __iomem *regs = priv->regs; + u32 value; + + bxcan_rmw(priv, ®s->mcr, 0, BXCAN_MCR_SLEEP); + return readx_poll_timeout(readl, ®s->msr, value, + value & BXCAN_MSR_SLAK, BXCAN_TIMEOUT_US, + USEC_PER_SEC); +} + +static int bxcan_leave_sleep_mode(struct bxcan_priv *priv) +{ + struct bxcan_regs __iomem *regs = priv->regs; + u32 value; + + bxcan_rmw(priv, ®s->mcr, BXCAN_MCR_SLEEP, 0); + return readx_poll_timeout(readl, ®s->msr, value, + !(value & BXCAN_MSR_SLAK), BXCAN_TIMEOUT_US, + USEC_PER_SEC); +} + +static inline +struct bxcan_priv *rx_offload_to_priv(struct can_rx_offload *offload) +{ + return container_of(offload, struct bxcan_priv, offload); +} + +static struct sk_buff *bxcan_mailbox_read(struct can_rx_offload *offload, + unsigned int mbxno, u32 *timestamp, + bool drop) +{ + struct bxcan_priv *priv = rx_offload_to_priv(offload); + struct bxcan_regs __iomem *regs = priv->regs; + struct bxcan_mb __iomem *mb_regs = ®s->rx_mb[0]; + struct sk_buff *skb = NULL; + struct can_frame *cf; + u32 rf0r, id, dlc; + + rf0r = readl(®s->rf0r); + if (unlikely(drop)) { + skb = ERR_PTR(-ENOBUFS); + goto mark_as_read; + } + + if (!(rf0r & BXCAN_RF0R_FMP0_MASK)) + goto mark_as_read; + + skb = alloc_can_skb(offload->dev, &cf); + if (unlikely(!skb)) { + skb = ERR_PTR(-ENOMEM); + goto mark_as_read; + } + + id = readl(&mb_regs->id); + if (id & BXCAN_RIxR_IDE) + cf->can_id = FIELD_GET(BXCAN_RIxR_EXID_MASK, id) | CAN_EFF_FLAG; + else + cf->can_id = FIELD_GET(BXCAN_RIxR_STID_MASK, id) & CAN_SFF_MASK; + + dlc = readl(&mb_regs->dlc); + priv->timestamp = FIELD_GET(BXCAN_RDTxR_TIME_MASK, dlc); + cf->len = can_cc_dlc2len(FIELD_GET(BXCAN_RDTxR_DLC_MASK, dlc)); + + if (id & BXCAN_RIxR_RTR) { + cf->can_id |= CAN_RTR_FLAG; + } else { + int i, j; + + for (i = 0, j = 0; i < cf->len; i += 4, j++) + *(u32 *)(cf->data + i) = readl(&mb_regs->data[j]); + } + + mark_as_read: + rf0r |= BXCAN_RF0R_RFOM0; + writel(rf0r, ®s->rf0r); + return skb; +} + +static irqreturn_t bxcan_rx_isr(int irq, void *dev_id) +{ + struct net_device *ndev = dev_id; + struct bxcan_priv *priv = netdev_priv(ndev); + struct bxcan_regs __iomem *regs = priv->regs; + u32 rf0r; + + rf0r = readl(®s->rf0r); + if (!(rf0r & BXCAN_RF0R_FMP0_MASK)) + return IRQ_NONE; + + can_rx_offload_irq_offload_fifo(&priv->offload); + can_rx_offload_irq_finish(&priv->offload); + + return IRQ_HANDLED; +} + +static irqreturn_t bxcan_tx_isr(int irq, void *dev_id) +{ + struct net_device *ndev = dev_id; + struct bxcan_priv *priv = netdev_priv(ndev); + struct bxcan_regs __iomem *regs = priv->regs; + struct net_device_stats *stats = &ndev->stats; + u32 tsr, rqcp_bit; + int idx; + + tsr = readl(®s->tsr); + if (!(tsr & (BXCAN_TSR_RQCP0 | BXCAN_TSR_RQCP1 | BXCAN_TSR_RQCP2))) + return IRQ_NONE; + + while (priv->tx_head - priv->tx_tail > 0) { + idx = bxcan_get_tx_tail(priv); + rqcp_bit = BXCAN_TSR_RQCP0 << (idx << 3); + if (!(tsr & rqcp_bit)) + break; + + stats->tx_packets++; + stats->tx_bytes += can_get_echo_skb(ndev, idx, NULL); + priv->tx_tail++; + } + + writel(tsr, ®s->tsr); + + if (bxcan_get_tx_free(priv)) { + /* Make sure that anybody stopping the queue after + * this sees the new tx_ring->tail. + */ + smp_mb(); + netif_wake_queue(ndev); + } + + return IRQ_HANDLED; +} + +static void bxcan_handle_state_change(struct net_device *ndev, u32 esr) +{ + struct bxcan_priv *priv = netdev_priv(ndev); + enum can_state new_state = priv->can.state; + struct can_berr_counter bec; + enum can_state rx_state, tx_state; + struct sk_buff *skb; + struct can_frame *cf; + + /* Early exit if no error flag is set */ + if (!(esr & (BXCAN_ESR_EWGF | BXCAN_ESR_EPVF | BXCAN_ESR_BOFF))) + return; + + bec.txerr = FIELD_GET(BXCAN_ESR_TEC_MASK, esr); + bec.rxerr = FIELD_GET(BXCAN_ESR_REC_MASK, esr); + + if (esr & BXCAN_ESR_BOFF) + new_state = CAN_STATE_BUS_OFF; + else if (esr & BXCAN_ESR_EPVF) + new_state = CAN_STATE_ERROR_PASSIVE; + else if (esr & BXCAN_ESR_EWGF) + new_state = CAN_STATE_ERROR_WARNING; + + /* state hasn't changed */ + if (unlikely(new_state == priv->can.state)) + return; + + skb = alloc_can_err_skb(ndev, &cf); + + tx_state = bec.txerr >= bec.rxerr ? new_state : 0; + rx_state = bec.txerr <= bec.rxerr ? new_state : 0; + can_change_state(ndev, cf, tx_state, rx_state); + + if (new_state == CAN_STATE_BUS_OFF) { + can_bus_off(ndev); + } else if (skb) { + cf->can_id |= CAN_ERR_CNT; + cf->data[6] = bec.txerr; + cf->data[7] = bec.rxerr; + } + + if (skb) { + int err; + + err = can_rx_offload_queue_timestamp(&priv->offload, skb, + priv->timestamp); + if (err) + ndev->stats.rx_fifo_errors++; + } +} + +static void bxcan_handle_bus_err(struct net_device *ndev, u32 esr) +{ + struct bxcan_priv *priv = netdev_priv(ndev); + enum bxcan_lec_code lec_code; + struct can_frame *cf; + struct sk_buff *skb; + + lec_code = FIELD_GET(BXCAN_ESR_LEC_MASK, esr); + + /* Early exit if no lec update or no error. + * No lec update means that no CAN bus event has been detected + * since CPU wrote BXCAN_LEC_UNUSED value to status reg. + */ + if (lec_code == BXCAN_LEC_UNUSED || lec_code == BXCAN_LEC_NO_ERROR) + return; + + /* Common for all type of bus errors */ + priv->can.can_stats.bus_error++; + + /* Propagate the error condition to the CAN stack */ + skb = alloc_can_err_skb(ndev, &cf); + if (skb) + cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; + + switch (lec_code) { + case BXCAN_LEC_STUFF_ERROR: + netdev_dbg(ndev, "Stuff error\n"); + ndev->stats.rx_errors++; + if (skb) + cf->data[2] |= CAN_ERR_PROT_STUFF; + break; + + case BXCAN_LEC_FORM_ERROR: + netdev_dbg(ndev, "Form error\n"); + ndev->stats.rx_errors++; + if (skb) + cf->data[2] |= CAN_ERR_PROT_FORM; + break; + + case BXCAN_LEC_ACK_ERROR: + netdev_dbg(ndev, "Ack error\n"); + ndev->stats.tx_errors++; + if (skb) { + cf->can_id |= CAN_ERR_ACK; + cf->data[3] = CAN_ERR_PROT_LOC_ACK; + } + break; + + case BXCAN_LEC_BIT1_ERROR: + netdev_dbg(ndev, "Bit error (recessive)\n"); + ndev->stats.tx_errors++; + if (skb) + cf->data[2] |= CAN_ERR_PROT_BIT1; + break; + + case BXCAN_LEC_BIT0_ERROR: + netdev_dbg(ndev, "Bit error (dominant)\n"); + ndev->stats.tx_errors++; + if (skb) + cf->data[2] |= CAN_ERR_PROT_BIT0; + break; + + case BXCAN_LEC_CRC_ERROR: + netdev_dbg(ndev, "CRC error\n"); + ndev->stats.rx_errors++; + if (skb) { + cf->data[2] |= CAN_ERR_PROT_BIT; + cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; + } + break; + + default: + break; + } + + if (skb) { + int err; + + err = can_rx_offload_queue_timestamp(&priv->offload, skb, + priv->timestamp); + if (err) + ndev->stats.rx_fifo_errors++; + } +} + +static irqreturn_t bxcan_state_change_isr(int irq, void *dev_id) +{ + struct net_device *ndev = dev_id; + struct bxcan_priv *priv = netdev_priv(ndev); + struct bxcan_regs __iomem *regs = priv->regs; + u32 msr, esr; + + msr = readl(®s->msr); + if (!(msr & BXCAN_MSR_ERRI)) + return IRQ_NONE; + + esr = readl(®s->esr); + bxcan_handle_state_change(ndev, esr); + + if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) + bxcan_handle_bus_err(ndev, esr); + + msr |= BXCAN_MSR_ERRI; + writel(msr, ®s->msr); + can_rx_offload_irq_finish(&priv->offload); + + return IRQ_HANDLED; +} + +static int bxcan_chip_start(struct net_device *ndev) +{ + struct bxcan_priv *priv = netdev_priv(ndev); + struct bxcan_regs __iomem *regs = priv->regs; + struct can_bittiming *bt = &priv->can.bittiming; + u32 clr, set; + int err; + + err = bxcan_chip_softreset(priv); + if (err) { + netdev_err(ndev, "failed to reset chip, error %pe\n", + ERR_PTR(err)); + return err; + } + + err = bxcan_leave_sleep_mode(priv); + if (err) { + netdev_err(ndev, "failed to leave sleep mode, error %pe\n", + ERR_PTR(err)); + goto failed_leave_sleep; + } + + err = bxcan_enter_init_mode(priv); + if (err) { + netdev_err(ndev, "failed to enter init mode, error %pe\n", + ERR_PTR(err)); + goto failed_enter_init; + } + + /* MCR + * + * select request order priority + * enable time triggered mode + * bus-off state left on sw request + * sleep mode left on sw request + * retransmit automatically on error + * do not lock RX FIFO on overrun + */ + bxcan_rmw(priv, ®s->mcr, + BXCAN_MCR_ABOM | BXCAN_MCR_AWUM | BXCAN_MCR_NART | + BXCAN_MCR_RFLM, BXCAN_MCR_TTCM | BXCAN_MCR_TXFP); + + /* Bit timing register settings */ + set = FIELD_PREP(BXCAN_BTR_BRP_MASK, bt->brp - 1) | + FIELD_PREP(BXCAN_BTR_TS1_MASK, bt->phase_seg1 + + bt->prop_seg - 1) | + FIELD_PREP(BXCAN_BTR_TS2_MASK, bt->phase_seg2 - 1) | + FIELD_PREP(BXCAN_BTR_SJW_MASK, bt->sjw - 1); + + /* loopback + silent mode put the controller in test mode, + * useful for hot self-test + */ + if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) + set |= BXCAN_BTR_LBKM; + + if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) + set |= BXCAN_BTR_SILM; + + bxcan_rmw(priv, ®s->btr, BXCAN_BTR_SILM | BXCAN_BTR_LBKM | + BXCAN_BTR_BRP_MASK | BXCAN_BTR_TS1_MASK | BXCAN_BTR_TS2_MASK | + BXCAN_BTR_SJW_MASK, set); + + bxcan_enable_filters(priv, priv->primary); + + /* Clear all internal status */ + priv->tx_head = 0; + priv->tx_tail = 0; + + err = bxcan_leave_init_mode(priv); + if (err) { + netdev_err(ndev, "failed to leave init mode, error %pe\n", + ERR_PTR(err)); + goto failed_leave_init; + } + + /* Set a `lec` value so that we can check for updates later */ + bxcan_rmw(priv, ®s->esr, BXCAN_ESR_LEC_MASK, + FIELD_PREP(BXCAN_ESR_LEC_MASK, BXCAN_LEC_UNUSED)); + + /* IER + * + * Enable interrupt for: + * bus-off + * passive error + * warning error + * last error code + * RX FIFO pending message + * TX mailbox empty + */ + clr = BXCAN_IER_WKUIE | BXCAN_IER_SLKIE | BXCAN_IER_FOVIE1 | + BXCAN_IER_FFIE1 | BXCAN_IER_FMPIE1 | BXCAN_IER_FOVIE0 | + BXCAN_IER_FFIE0; + set = BXCAN_IER_ERRIE | BXCAN_IER_BOFIE | BXCAN_IER_EPVIE | + BXCAN_IER_EWGIE | BXCAN_IER_FMPIE0 | BXCAN_IER_TMEIE; + + if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) + set |= BXCAN_IER_LECIE; + else + clr |= BXCAN_IER_LECIE; + + bxcan_rmw(priv, ®s->ier, clr, set); + + priv->can.state = CAN_STATE_ERROR_ACTIVE; + return 0; + +failed_leave_init: +failed_enter_init: +failed_leave_sleep: + bxcan_chip_softreset(priv); + return err; +} + +static int bxcan_open(struct net_device *ndev) +{ + struct bxcan_priv *priv = netdev_priv(ndev); + int err; + + err = clk_prepare_enable(priv->clk); + if (err) { + netdev_err(ndev, "failed to enable clock, error %pe\n", + ERR_PTR(err)); + return err; + } + + err = open_candev(ndev); + if (err) { + netdev_err(ndev, "open_candev() failed, error %pe\n", + ERR_PTR(err)); + goto out_disable_clock; + } + + can_rx_offload_enable(&priv->offload); + err = request_irq(ndev->irq, bxcan_rx_isr, IRQF_SHARED, ndev->name, + ndev); + if (err) { + netdev_err(ndev, "failed to register rx irq(%d), error %pe\n", + ndev->irq, ERR_PTR(err)); + goto out_close_candev; + } + + err = request_irq(priv->tx_irq, bxcan_tx_isr, IRQF_SHARED, ndev->name, + ndev); + if (err) { + netdev_err(ndev, "failed to register tx irq(%d), error %pe\n", + priv->tx_irq, ERR_PTR(err)); + goto out_free_rx_irq; + } + + err = request_irq(priv->sce_irq, bxcan_state_change_isr, IRQF_SHARED, + ndev->name, ndev); + if (err) { + netdev_err(ndev, "failed to register sce irq(%d), error %pe\n", + priv->sce_irq, ERR_PTR(err)); + goto out_free_tx_irq; + } + + err = bxcan_chip_start(ndev); + if (err) + goto out_free_sce_irq; + + netif_start_queue(ndev); + return 0; + +out_free_sce_irq: + free_irq(priv->sce_irq, ndev); +out_free_tx_irq: + free_irq(priv->tx_irq, ndev); +out_free_rx_irq: + free_irq(ndev->irq, ndev); +out_close_candev: + can_rx_offload_disable(&priv->offload); + close_candev(ndev); +out_disable_clock: + clk_disable_unprepare(priv->clk); + return err; +} + +static void bxcan_chip_stop(struct net_device *ndev) +{ + struct bxcan_priv *priv = netdev_priv(ndev); + struct bxcan_regs __iomem *regs = priv->regs; + + /* disable all interrupts */ + bxcan_rmw(priv, ®s->ier, BXCAN_IER_SLKIE | BXCAN_IER_WKUIE | + BXCAN_IER_ERRIE | BXCAN_IER_LECIE | BXCAN_IER_BOFIE | + BXCAN_IER_EPVIE | BXCAN_IER_EWGIE | BXCAN_IER_FOVIE1 | + BXCAN_IER_FFIE1 | BXCAN_IER_FMPIE1 | BXCAN_IER_FOVIE0 | + BXCAN_IER_FFIE0 | BXCAN_IER_FMPIE0 | BXCAN_IER_TMEIE, 0); + bxcan_disable_filters(priv, priv->primary); + bxcan_enter_sleep_mode(priv); + priv->can.state = CAN_STATE_STOPPED; +} + +static int bxcan_stop(struct net_device *ndev) +{ + struct bxcan_priv *priv = netdev_priv(ndev); + + netif_stop_queue(ndev); + bxcan_chip_stop(ndev); + free_irq(ndev->irq, ndev); + free_irq(priv->tx_irq, ndev); + free_irq(priv->sce_irq, ndev); + can_rx_offload_disable(&priv->offload); + close_candev(ndev); + clk_disable_unprepare(priv->clk); + return 0; +} + +static netdev_tx_t bxcan_start_xmit(struct sk_buff *skb, + struct net_device *ndev) +{ + struct bxcan_priv *priv = netdev_priv(ndev); + struct can_frame *cf = (struct can_frame *)skb->data; + struct bxcan_regs __iomem *regs = priv->regs; + struct bxcan_mb __iomem *mb_regs; + unsigned int idx; + u32 id; + int i, j; + + if (can_dropped_invalid_skb(ndev, skb)) + return NETDEV_TX_OK; + + if (bxcan_tx_busy(priv)) + return NETDEV_TX_BUSY; + + idx = bxcan_get_tx_head(priv); + priv->tx_head++; + if (bxcan_get_tx_free(priv) == 0) + netif_stop_queue(ndev); + + mb_regs = ®s->tx_mb[idx]; + if (cf->can_id & CAN_EFF_FLAG) + id = FIELD_PREP(BXCAN_TIxR_EXID_MASK, cf->can_id) | + BXCAN_TIxR_IDE; + else + id = FIELD_PREP(BXCAN_TIxR_STID_MASK, cf->can_id); + + if (cf->can_id & CAN_RTR_FLAG) { /* Remote transmission request */ + id |= BXCAN_TIxR_RTR; + } else { + for (i = 0, j = 0; i < cf->len; i += 4, j++) + writel(*(u32 *)(cf->data + i), &mb_regs->data[j]); + } + + writel(FIELD_PREP(BXCAN_TDTxR_DLC_MASK, cf->len), &mb_regs->dlc); + + can_put_echo_skb(skb, ndev, idx, 0); + + /* Start transmission */ + writel(id | BXCAN_TIxR_TXRQ, &mb_regs->id); + + return NETDEV_TX_OK; +} + +static const struct net_device_ops bxcan_netdev_ops = { + .ndo_open = bxcan_open, + .ndo_stop = bxcan_stop, + .ndo_start_xmit = bxcan_start_xmit, + .ndo_change_mtu = can_change_mtu, +}; + +static const struct ethtool_ops bxcan_ethtool_ops = { + .get_ts_info = ethtool_op_get_ts_info, +}; + +static int bxcan_do_set_mode(struct net_device *ndev, enum can_mode mode) +{ + int err; + + switch (mode) { + case CAN_MODE_START: + err = bxcan_chip_start(ndev); + if (err) + return err; + + netif_wake_queue(ndev); + break; + + default: + return -EOPNOTSUPP; + } + + return 0; +} + +static int bxcan_get_berr_counter(const struct net_device *ndev, + struct can_berr_counter *bec) +{ + struct bxcan_priv *priv = netdev_priv(ndev); + struct bxcan_regs __iomem *regs = priv->regs; + u32 esr; + int err; + + err = clk_prepare_enable(priv->clk); + if (err) + return err; + + esr = readl(®s->esr); + bec->txerr = FIELD_GET(BXCAN_ESR_TEC_MASK, esr); + bec->rxerr = FIELD_GET(BXCAN_ESR_REC_MASK, esr); + clk_disable_unprepare(priv->clk); + return 0; +} + +static int bxcan_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct device *dev = &pdev->dev; + struct net_device *ndev; + struct bxcan_priv *priv; + struct clk *clk = NULL; + void __iomem *regs; + struct regmap *gcan; + bool primary; + int err, rx_irq, tx_irq, sce_irq; + + regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(regs)) { + dev_err(dev, "failed to get base address\n"); + return PTR_ERR(regs); + } + + gcan = syscon_regmap_lookup_by_phandle(np, "st,gcan"); + if (IS_ERR(gcan)) { + dev_err(dev, "failed to get shared memory base address\n"); + return PTR_ERR(gcan); + } + + primary = of_property_read_bool(np, "st,can-primary"); + clk = devm_clk_get(dev, NULL); + if (IS_ERR(clk)) { + dev_err(dev, "failed to get clock\n"); + return PTR_ERR(clk); + } + + rx_irq = platform_get_irq_byname(pdev, "rx0"); + if (rx_irq < 0) { + dev_err(dev, "failed to get rx0 irq\n"); + return rx_irq; + } + + tx_irq = platform_get_irq_byname(pdev, "tx"); + if (tx_irq < 0) { + dev_err(dev, "failed to get tx irq\n"); + return tx_irq; + } + + sce_irq = platform_get_irq_byname(pdev, "sce"); + if (sce_irq < 0) { + dev_err(dev, "failed to get sce irq\n"); + return sce_irq; + } + + ndev = alloc_candev(sizeof(struct bxcan_priv), BXCAN_TX_MB_NUM); + if (!ndev) { + dev_err(dev, "alloc_candev() failed\n"); + return -ENOMEM; + } + + priv = netdev_priv(ndev); + platform_set_drvdata(pdev, ndev); + SET_NETDEV_DEV(ndev, dev); + ndev->netdev_ops = &bxcan_netdev_ops; + ndev->ethtool_ops = &bxcan_ethtool_ops; + ndev->irq = rx_irq; + ndev->flags |= IFF_ECHO; + + priv->dev = dev; + priv->ndev = ndev; + priv->regs = regs; + priv->gcan = gcan; + priv->clk = clk; + priv->tx_irq = tx_irq; + priv->sce_irq = sce_irq; + priv->primary = primary; + priv->can.clock.freq = clk_get_rate(clk); + spin_lock_init(&priv->rmw_lock); + priv->tx_head = 0; + priv->tx_tail = 0; + priv->can.bittiming_const = &bxcan_bittiming_const; + priv->can.do_set_mode = bxcan_do_set_mode; + priv->can.do_get_berr_counter = bxcan_get_berr_counter; + priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | + CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_BERR_REPORTING; + + priv->offload.mailbox_read = bxcan_mailbox_read; + err = can_rx_offload_add_fifo(ndev, &priv->offload, BXCAN_NAPI_WEIGHT); + if (err) { + dev_err(dev, "failed to add FIFO rx_offload\n"); + goto out_free_candev; + } + + err = register_candev(ndev); + if (err) { + dev_err(dev, "failed to register netdev\n"); + goto out_can_rx_offload_del; + } + + dev_info(dev, "clk: %d Hz, IRQs: %d, %d, %d\n", priv->can.clock.freq, + tx_irq, rx_irq, sce_irq); + return 0; + +out_can_rx_offload_del: + can_rx_offload_del(&priv->offload); +out_free_candev: + free_candev(ndev); + return err; +} + +static int bxcan_remove(struct platform_device *pdev) +{ + struct net_device *ndev = platform_get_drvdata(pdev); + struct bxcan_priv *priv = netdev_priv(ndev); + + unregister_candev(ndev); + clk_disable_unprepare(priv->clk); + can_rx_offload_del(&priv->offload); + free_candev(ndev); + return 0; +} + +static int __maybe_unused bxcan_suspend(struct device *dev) +{ + struct net_device *ndev = dev_get_drvdata(dev); + struct bxcan_priv *priv = netdev_priv(ndev); + + if (!netif_running(ndev)) + return 0; + + netif_stop_queue(ndev); + netif_device_detach(ndev); + + bxcan_enter_sleep_mode(priv); + priv->can.state = CAN_STATE_SLEEPING; + clk_disable_unprepare(priv->clk); + return 0; +} + +static int __maybe_unused bxcan_resume(struct device *dev) +{ + struct net_device *ndev = dev_get_drvdata(dev); + struct bxcan_priv *priv = netdev_priv(ndev); + + if (!netif_running(ndev)) + return 0; + + clk_prepare_enable(priv->clk); + bxcan_leave_sleep_mode(priv); + priv->can.state = CAN_STATE_ERROR_ACTIVE; + + netif_device_attach(ndev); + netif_start_queue(ndev); + return 0; +} + +static SIMPLE_DEV_PM_OPS(bxcan_pm_ops, bxcan_suspend, bxcan_resume); + +static const struct of_device_id bxcan_of_match[] = { + {.compatible = "st,stm32f4-bxcan"}, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, bxcan_of_match); + +static struct platform_driver bxcan_driver = { + .driver = { + .name = KBUILD_MODNAME, + .pm = &bxcan_pm_ops, + .of_match_table = bxcan_of_match, + }, + .probe = bxcan_probe, + .remove = bxcan_remove, +}; + +module_platform_driver(bxcan_driver); + +MODULE_AUTHOR("Dario Binacchi "); +MODULE_DESCRIPTION("STMicroelectronics Basic Extended CAN controller driver"); +MODULE_LICENSE("GPL");