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[79.54.71.141]) by smtp.gmail.com with ESMTPSA id v22-20020aa7d9d6000000b0052568bf9411sm4850232eds.68.2023.09.03.13.57.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Sep 2023 13:57:06 -0700 (PDT) From: Dario Binacchi To: u-boot@lists.denx.de Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Patrice Chotard , Patrick Delaunay , Tom Rini , uboot-stm32@st-md-mailman.stormreply.com Subject: [RFC PATCH 1/5] ARM: dts: stm32f469-disco: sync with Linux 6.5 Date: Sun, 3 Sep 2023 22:56:59 +0200 Message-Id: <20230903205703.662080-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230903205703.662080-1-dario.binacchi@amarulasolutions.com> References: <20230903205703.662080-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=byjA4Gg9; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Sync the devicetree with linux 6.5 for stm32f746-disco board. Signed-off-by: Dario Binacchi Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32f469-disco.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/stm32f469-disco.dts b/arch/arm/dts/stm32f469-disco.dts index 6e0ffc1903be..c9acabf0f530 100644 --- a/arch/arm/dts/stm32f469-disco.dts +++ b/arch/arm/dts/stm32f469-disco.dts @@ -119,7 +119,7 @@ }; }; - panel-dsi@0 { + panel@0 { compatible = "orisetech,otm8009a"; reg = <0>; /* dsi virtual channel (0..3) */ reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>; @@ -138,7 +138,7 @@ status = "okay"; port { - ltdc_out_dsi: endpoint@0 { + ltdc_out_dsi: endpoint { remote-endpoint = <&dsi_in>; }; }; From patchwork Sun Sep 3 20:57:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2978 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-lj1-f199.google.com (mail-lj1-f199.google.com [209.85.208.199]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id C7F5C40F59 for ; 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[79.54.71.141]) by smtp.gmail.com with ESMTPSA id v22-20020aa7d9d6000000b0052568bf9411sm4850232eds.68.2023.09.03.13.57.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Sep 2023 13:57:07 -0700 (PDT) From: Dario Binacchi To: u-boot@lists.denx.de Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Patrice Chotard , Patrick Delaunay , Simon Glass , Tom Rini , uboot-stm32@st-md-mailman.stormreply.com Subject: [RFC PATCH 2/5] ARM: dts: stm32: make the LTDC clock usable by the clock driver Date: Sun, 3 Sep 2023 22:57:00 +0200 Message-Id: <20230903205703.662080-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230903205703.662080-1-dario.binacchi@amarulasolutions.com> References: <20230903205703.662080-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=H4Utc2dY; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , As described in [1], the "clocks" property contains "a phandle to the clock device node, an index selecting between gated clocks (0) and other clocks (1), and an index specifying the clock to use." The current version of the clock driver, unlike the kernel, is currently able to properly handle nodes with "clocks" properties with an index set to 0. This patch is preparatory for future developments that require the use of the LTDC clock. [1] Documentation/devicetree/bindings/clock/st,stm32-rcc.txt Signed-off-by: Dario Binacchi Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32f469-disco-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/stm32f469-disco-u-boot.dtsi b/arch/arm/dts/stm32f469-disco-u-boot.dtsi index c07e2022e4a8..dcc70369cd0d 100644 --- a/arch/arm/dts/stm32f469-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f469-disco-u-boot.dtsi @@ -134,6 +134,10 @@ bootph-all; }; +<dc { + clocks = <&rcc 0 STM32F4_APB2_CLOCK(LTDC)>; +}; + &pinctrl { bootph-all; From patchwork Sun Sep 3 20:57:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2979 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-lf1-f72.google.com (mail-lf1-f72.google.com [209.85.167.72]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 35233414AC for ; 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[79.54.71.141]) by smtp.gmail.com with ESMTPSA id v22-20020aa7d9d6000000b0052568bf9411sm4850232eds.68.2023.09.03.13.57.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Sep 2023 13:57:09 -0700 (PDT) From: Dario Binacchi To: u-boot@lists.denx.de Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Patrice Chotard , Patrick Delaunay , Simon Glass , Tom Rini , uboot-stm32@st-md-mailman.stormreply.com Subject: [RFC PATCH 3/5] ARM: dts: stm32: make the DSI clock usable by the clock driver Date: Sun, 3 Sep 2023 22:57:01 +0200 Message-Id: <20230903205703.662080-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230903205703.662080-1-dario.binacchi@amarulasolutions.com> References: <20230903205703.662080-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=Ecu16wh2; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , As described in [1], the "clocks" property contains "a phandle to the clock device node, an index selecting between gated clocks (0) and other clocks (1), and an index specifying the clock to use." The current version of the clock driver, unlike the kernel, is currently able to properly handle nodes with "clocks" properties with an index set to 0. This patch is preparatory for future developments that require the use of the DSI clock. [1] Documentation/devicetree/bindings/clock/st,stm32-rcc.txt Signed-off-by: Dario Binacchi Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32f469-disco-u-boot.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/dts/stm32f469-disco-u-boot.dtsi b/arch/arm/dts/stm32f469-disco-u-boot.dtsi index dcc70369cd0d..8e781c5a7b23 100644 --- a/arch/arm/dts/stm32f469-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f469-disco-u-boot.dtsi @@ -90,6 +90,11 @@ bootph-all; }; +&dsi { + clocks = <&rcc 0 STM32F4_APB2_CLOCK(DSI)>, + <&clk_hse>; +}; + &gpioa { bootph-all; }; From patchwork Sun Sep 3 20:57:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2981 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-lf1-f70.google.com (mail-lf1-f70.google.com [209.85.167.70]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id A9EA74211D for ; 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It was necessary to retrieve the framebuffer address from the device tree because the address returned by the video-uclass driver pointed to a memory area that was not usable. Furthermore, unlike Linux, the DSI driver requires the LTDC clock to be properly probed. Hence, the changes made to the DSI node in stm32f469-disco-u-boot.dtsi. Signed-off-by: Dario Binacchi --- arch/arm/dts/stm32f469-disco-u-boot.dtsi | 4 +++ configs/stm32f469-discovery_defconfig | 13 +++++++++ drivers/video/stm32/stm32_ltdc.c | 37 +++++++++++++++++++++++- 3 files changed, 53 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/stm32f469-disco-u-boot.dtsi b/arch/arm/dts/stm32f469-disco-u-boot.dtsi index 8e781c5a7b23..47ba9fa4a783 100644 --- a/arch/arm/dts/stm32f469-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f469-disco-u-boot.dtsi @@ -92,7 +92,9 @@ &dsi { clocks = <&rcc 0 STM32F4_APB2_CLOCK(DSI)>, + <&rcc 0 STM32F4_APB2_CLOCK(LTDC)>, <&clk_hse>; + clock-names = "pclk", "px_clk", "ref"; }; &gpioa { @@ -140,6 +142,8 @@ }; <dc { + bootph-all; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(LTDC)>; }; diff --git a/configs/stm32f469-discovery_defconfig b/configs/stm32f469-discovery_defconfig index 35d18d58be6f..9796b8f2d9a5 100644 --- a/configs/stm32f469-discovery_defconfig +++ b/configs/stm32f469-discovery_defconfig @@ -21,6 +21,7 @@ CONFIG_CMD_GPT=y # CONFIG_RANDOM_UUID is not set CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIMER=y # CONFIG_ISO_PARTITION is not set @@ -40,3 +41,15 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_STM32_QSPI=y +CONFIG_VIDEO=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y +CONFIG_VIDEO_STM32=y +CONFIG_VIDEO_STM32_DSI=y +CONFIG_VIDEO_STM32_MAX_XRES=480 +CONFIG_VIDEO_STM32_MAX_YRES=800 +CONFIG_BMP_16BPP=y +CONFIG_BMP_24BPP=y +CONFIG_BMP_32BPP=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c index f48badc517a8..428b0addc43c 100644 --- a/drivers/video/stm32/stm32_ltdc.c +++ b/drivers/video/stm32/stm32_ltdc.c @@ -494,6 +494,34 @@ static void stm32_ltdc_set_layer1(struct stm32_ltdc_priv *priv, ulong fb_addr) setbits_le32(priv->regs + LTDC_L1CR, LXCR_LEN); } +#if IS_ENABLED(CONFIG_TARGET_STM32F469_DISCOVERY) +static int stm32_ltdc_get_fb_addr(struct udevice *dev, ulong *base, uint size, + uint align) +{ + phys_addr_t cpu; + dma_addr_t bus; + u64 dma_size; + int ret; + + ret = dev_get_dma_range(dev, &cpu, &bus, &dma_size); + if (ret) { + dev_err(dev, "failed to get dma address\n"); + return ret; + } + + *base = bus + 0x1000000 - ALIGN(size, align); + return 0; +} +#else +static int stm32_ltdc_get_fb_addr(struct udevice *dev, ulong *base, uint size, + uint align) +{ + /* Delegate framebuffer allocation to video-uclass */ + *base = 0; + return 0; +} +#endif + static int stm32_ltdc_probe(struct udevice *dev) { struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev); @@ -504,7 +532,7 @@ static int stm32_ltdc_probe(struct udevice *dev) struct display_timing timings; struct clk pclk; struct reset_ctl rst; - ulong rate; + ulong rate, fb_base; int ret; priv->regs = dev_read_addr_ptr(dev); @@ -604,6 +632,13 @@ static int stm32_ltdc_probe(struct udevice *dev) priv->crop_h = timings.vactive.typ; priv->alpha = 0xFF; + ret = stm32_ltdc_get_fb_addr(dev, &fb_base, uc_plat->size, + uc_plat->align); + if (ret) + return ret; + + uc_plat->base = fb_base; + dev_dbg(dev, "%dx%d %dbpp frame buffer at 0x%lx\n", timings.hactive.typ, timings.vactive.typ, VNBITS(priv->l2bpp), uc_plat->base); From patchwork Sun Sep 3 20:57:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2980 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-lf1-f72.google.com (mail-lf1-f72.google.com [209.85.167.72]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 5F38D3F1DA for ; Sun, 3 Sep 2023 22:57:14 +0200 (CEST) Received: by mail-lf1-f72.google.com with SMTP id 2adb3069b0e04-4fe565bca92sf861826e87.0 for ; Sun, 03 Sep 2023 13:57:14 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1693774633; cv=pass; d=google.com; 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[79.54.71.141]) by smtp.gmail.com with ESMTPSA id v22-20020aa7d9d6000000b0052568bf9411sm4850232eds.68.2023.09.03.13.57.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Sep 2023 13:57:11 -0700 (PDT) From: Dario Binacchi To: u-boot@lists.denx.de Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Patrice Chotard , Patrick Delaunay , uboot-stm32@st-md-mailman.stormreply.com Subject: [RFC PATCH 5/5] board: stm32f469-disco: add splash screen with stmicroelectronics logo Date: Sun, 3 Sep 2023 22:57:03 +0200 Message-Id: <20230903205703.662080-6-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230903205703.662080-1-dario.binacchi@amarulasolutions.com> References: <20230903205703.662080-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=VPj7LRVh; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Display the STMicroelectronics logo with features VIDEO_LOGO and SPLASH_SCREEN on stm32f469-disco board. Signed-off-by: Dario Binacchi --- configs/stm32f469-discovery_defconfig | 3 +++ include/configs/stm32f469-discovery.h | 2 ++ tools/logos/stm32f469-discovery.bmp | Bin 0 -> 18532 bytes 3 files changed, 5 insertions(+) create mode 100644 tools/logos/stm32f469-discovery.bmp diff --git a/tools/logos/stm32f469-discovery.bmp b/tools/logos/stm32f469-discovery.bmp new file mode 100644 index 0000000000000000000000000000000000000000..ecc8d984218fb13fddf0ba9cf68f2cfad829e289 GIT binary patch literal 18532 zcmeI4cXZX&w(r;65wa7qNk~Y5gbqmv5Fw!j5+O7xl9*5>^j-qed+)tS@6wBaRB3{M zG^rvTq<29PJ?imP-e<18^`MV)eL3Teaql13aUl7vHRoJ&eP> z%wT@IEylFuj~FL^jJa0Tn0Xc4f9!w`nis$P&puSCQMcE$Pk$_ux+`yR-Z4+5RH;%y z?c2AH;7{iH^XL1#;d|MuNYiPtO8m=zEccuLUc7i=rj8tL{`t>;n(v=~XLfJfVn+4u zWiDU5VCn>CGXMC;KTO@od?q<8o7uN>r}_EkpUhwX`d8EO?IiP$zyIB&6v$~VpTA)K z_P4*8AHM&S`O9DaV*d2q_oiOaLS|rxcIM{w>!w$Wrlvu35%ZUye>UrvFE{t^-Zg)P zu4|(P=Bvk#%nv{OV3y6BV{UwT&0M>3*|d4Hs`=*YZ%mJ-Y39#A{bas<_O1Ey>Q&RP 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