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[209.85.220.41]) by mx.google.com with SMTPS id ffacd0b85a97d-368787bb29dsor3958912f8f.3.2024.07.24.00.34.14 for (Google Transport Security); Wed, 24 Jul 2024 00:34:14 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a5d:69cc:0:b0:366:ee01:30d6 with SMTP id ffacd0b85a97d-369f0a7c90cmr1570960f8f.49.1721806454066; Wed, 24 Jul 2024 00:34:14 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.40.97]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-368787ced05sm13474613f8f.67.2024.07.24.00.34.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jul 2024 00:34:13 -0700 (PDT) From: Dario Binacchi To: michael@amarulasolutions.com Cc: linux-amarula@amarulasolutions.com, Dario Binacchi Subject: [PATCH 1/2] fix(imx8m): set uart domain permission Date: Wed, 24 Jul 2024 09:34:00 +0200 Message-ID: <20240724073401.1587434-1-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="qhJ/d8rZ"; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The commit d76f012ea8fc0 ("refactor(imx8m): replace magic number with enum type") also hardcodes the domain permissions for the UARTs, without considering that read/write rights for domain 0 must be enabled for the boot UART. This creates a regression. Indeed, previously, the RDC_PDAP_UARTn registers were set to the reset value (0xff), meaning all domains were enabled for read and write access. The patch fixes this issue by assigning read/write rights for domain 0 to the boot UART. Signed-off-by: Dario Binacchi --- plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c | 5 +++-- plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c | 5 +++-- plat/imx/imx8m/include/imx8m_uart.h | 15 +++++++++++++++ plat/imx/imx8m/include/imx_rdc.h | 3 +++ 4 files changed, 24 insertions(+), 4 deletions(-) create mode 100644 plat/imx/imx8m/include/imx8m_uart.h diff --git a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c index dc9dd5949798..7f7319392b1d 100644 --- a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c +++ b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c @@ -30,6 +30,7 @@ #include #include #include + #include #define TRUSTY_PARAMS_LEN_BYTES (4096*2) @@ -66,8 +67,8 @@ static const struct imx_rdc_cfg rdc[] = { RDC_MDAn(RDC_MDA_M4, DID1), /* peripherals domain permission */ - RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W), - RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), + RDC_PDAPn(RDC_PDAP_UART4, PDAPn_UART_DOMAIN(UART4_BASE_ADDR, D1R | D1W)), + RDC_PDAPn(RDC_PDAP_UART2, PDAPn_UART_DOMAIN(UART2_BASE_ADDR, D1R | D1W)), /* memory region */ diff --git a/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c b/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c index f9e430bf964a..0b6e9c979efd 100644 --- a/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c +++ b/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include @@ -52,8 +53,8 @@ static const struct imx_rdc_cfg rdc[] = { RDC_MDAn(RDC_MDA_M7, DID1), /* peripherals domain permission */ - RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W), - RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), + RDC_PDAPn(RDC_PDAP_UART4, PDAPn_UART_DOMAIN(UART4_BASE_ADDR, D1R | D1W)), + RDC_PDAPn(RDC_PDAP_UART2, PDAPn_UART_DOMAIN(UART2_BASE_ADDR, D1R | D1W)), /* memory region */ RDC_MEM_REGIONn(16, 0x0, 0x0, 0xff), diff --git a/plat/imx/imx8m/include/imx8m_uart.h b/plat/imx/imx8m/include/imx8m_uart.h new file mode 100644 index 000000000000..46e32f30bc97 --- /dev/null +++ b/plat/imx/imx8m/include/imx8m_uart.h @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2024, Amarula Solutions B.V. + * + * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause + */ + +#ifndef IMX8M_UART_H +#define IMX8M_UART_H + +#define UART1_BASE_ADDR 0x30860000 +#define UART2_BASE_ADDR 0x30890000 +#define UART3_BASE_ADDR 0x30880000 +#define UART4_BASE_ADDR 0x30A60000 + +#endif /*IMX8M_UART_H */ diff --git a/plat/imx/imx8m/include/imx_rdc.h b/plat/imx/imx8m/include/imx_rdc.h index a6e10a7b7529..f1a40cea3eed 100644 --- a/plat/imx/imx8m/include/imx_rdc.h +++ b/plat/imx/imx8m/include/imx_rdc.h @@ -36,6 +36,9 @@ #define D0R BIT(1) #define D0W BIT(0) +#define PDAPn_UART_DOMAIN(base, def_domain) \ + (IMX_BOOT_UART_BASE == base ? D0R | D0W : def_domain) + union rdc_setting { uint32_t rdc_mda; /* Master Domain Assignment */ uint32_t rdc_pdap; /* Peripheral Domain Access Permissions */ From patchwork Wed Jul 24 07:34:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 3318 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-wm1-f71.google.com (mail-wm1-f71.google.com [209.85.128.71]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 477443F18D for ; Wed, 24 Jul 2024 09:34:20 +0200 (CEST) Received: by mail-wm1-f71.google.com with SMTP id 5b1f17b1804b1-42671a6fb9dsf43700195e9.3 for ; Wed, 24 Jul 2024 00:34:20 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1721806460; cv=pass; d=google.com; s=arc-20160816; b=u5lFKEHyshMoVtMwtSG5iEx/Egx/J33uSBZxjl8fXD/Y0WwUYktTdN62RU2Yw3Av6H ZQNEWoF6svUiP76xcMJl+nIh90dZ60GFaO0jFOsdhNKqxSLf5JZL2rb9i12gPFzhhztl Qu6G5Q6h7Dj1aB9XWMSklLf/Ka6i/STSWqEJB+ntildBpLZatmDdp8qXm/QPtDZDzbsw K258MEZZw4Xa7iZX8CC7rEj0NBWAe3sY7tGEFkvZUjfHx2UaoLk+a1LZ2dXUsh2ApHVC gKvdLDMEBbF+If/ERJIwO0lYQhJOrmJ9CYrHcyb/oFlWCB8gacJarNIMin3k70TxGHK7 sd8Q== ARC-Message-Signature: i=2; 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([2.196.40.97]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-368787ced05sm13474613f8f.67.2024.07.24.00.34.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jul 2024 00:34:17 -0700 (PDT) From: Dario Binacchi To: michael@amarulasolutions.com Cc: linux-amarula@amarulasolutions.com, Dario Binacchi Subject: [PATCH 2/2] refactor(imx8m): replace magic number with macros Date: Wed, 24 Jul 2024 09:34:01 +0200 Message-ID: <20240724073401.1587434-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240724073401.1587434-1-dario.binacchi@amarulasolutions.com> References: <20240724073401.1587434-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=AzzhTtgj; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Replace the UARTs base addresses with the appropriate constants previously defined in the file "imx8m_uart.h". Fammi sapere se hai altre richieste di traduzione o altre domande! Replace the uart base address using ose RDC config related magic numbers with enum type Signed-off-by: Dario Binacchi --- plat/imx/imx8m/imx8m_ccm.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/plat/imx/imx8m/imx8m_ccm.c b/plat/imx/imx8m/imx8m_ccm.c index 10a00c990031..96b38e2712e1 100644 --- a/plat/imx/imx8m/imx8m_ccm.c +++ b/plat/imx/imx8m/imx8m_ccm.c @@ -5,6 +5,7 @@ */ #include +#include #include #define UCR1 0x80 @@ -17,16 +18,16 @@ static struct imx_uart { } imx8m_uart_info[] = { { /* UART 1 */ .ccm_reg = 0x4490, - .uart_base = 0x30860000, + .uart_base = UART1_BASE_ADDR, }, { /* UART 2 */ .ccm_reg = 0x44a0, - .uart_base = 0x30890000, + .uart_base = UART2_BASE_ADDR, }, { /* UART 3 */ .ccm_reg = 0x44b0, - .uart_base = 0x30880000, + .uart_base = UART3_BASE_ADDR, }, { /* UART 4 */ .ccm_reg = 0x44c0, - .uart_base = 0x30a60000, + .uart_base = UART4_BASE_ADDR, } };