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[209.85.220.65]) by mx.google.com with SMTPS id g188sor1737400pgc.84.2019.05.03.04.59.48 for (Google Transport Security); Fri, 03 May 2019 04:59:48 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a63:1604:: with SMTP id w4mr9850811pgl.148.1556884787760; Fri, 03 May 2019 04:59:47 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.165]) by smtp.gmail.com with ESMTPSA id f5sm2235940pgo.75.2019.05.03.04.59.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 May 2019 04:59:47 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Chen-Yu Tsai , Rob Herring , Mark Rutland Cc: Michael Trimarchi , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-amarula@amarulasolutions.com, linux-sunxi@googlegroups.com, Jagan Teki Subject: [PATCH v2] arm64: allwinner: h6: orangepi-one-plus: Add Ethernet support Date: Fri, 3 May 2019 17:29:28 +0530 Message-Id: <20190503115928.27662-1-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=I7fOhnOZ; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add Ethernet support for orangepi-one-plus board, - Ethernet port connected via RTL8211E PHY - PHY suppiled with GMAC-2V5, fixed regulator with GMAC_EN pin via PD6 GMAC-3V, which is supplied by VCC3V3-MAC via aldo2 - RGMII-RESET pin connected via PD14 Signed-off-by: Jagan Teki --- Changes for v2: - emac changes on top of https://patchwork.kernel.org/cover/10899529/ series .../allwinner/sun50i-h6-orangepi-one-plus.dts | 8 ++++ .../dts/allwinner/sun50i-h6-orangepi.dtsi | 42 +++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts index 12e17567ab56..9e8ed1053715 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts @@ -9,4 +9,12 @@ / { model = "OrangePi One Plus"; compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6"; + + aliases { + ethernet0 = &emac; + }; +}; + +&emac { + status = "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi index 62e27948a3fa..c48e24acaf8a 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi @@ -45,6 +45,48 @@ regulator-max-microvolt = <5000000>; regulator-always-on; }; + + /* + * The board uses 2.5V RGMII signalling. Power sequence to enable + * the phy is to enable GMAC-2V5 and GMAC-3V (aldo2) power rails + * at the same time and to wait 100ms. + */ + reg_gmac_2v5: gmac-2v5 { + compatible = "regulator-fixed"; + regulator-name = "gmac-2v5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* GMAC_EN: PD6 */ + + /* The real parent of gmac-2v5 is reg_vcc5v, but we need to + * enable two regulators to power the phy. This is one way + * to achieve that. + */ + vin-supply = <®_aldo2>; /* VCC3V3-MAC: GMAC-3V */ + }; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&ext_rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + phy-supply = <®_gmac_2v5>; + allwinner,rx-delay-ps = <1500>; + allwinner,tx-delay-ps = <700>; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + + reset-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* RGMII-RESET: PD14 */ + reset-assert-us = <15000>; + reset-deassert-us = <40000>; + }; }; &ehci0 {