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([151.37.190.149]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa51a449c24sm537671966b.178.2024.11.26.01.46.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:46:38 -0800 (PST) From: Patrick Barsanti To: linux-amarula@amarulasolutions.com Cc: dario.binacchi@amarulasolutions.com, patrick.barsanti@amarulasolutions.com Subject: [PATCH 01/11] dt-bindings: arm: fsl: Add engicam,icore-mx8mp family Date: Tue, 26 Nov 2024 10:46:25 +0100 Message-ID: <20241126094635.881134-2-patrick.barsanti@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241126094635.881134-1-patrick.barsanti@amarulasolutions.com> References: <20241126094635.881134-1-patrick.barsanti@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: patrick.barsanti@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=ePG70zNT; spf=pass (google.com: domain of patrick.barsanti@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=patrick.barsanti@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add Engicam i.Core MX8M Plus, i.Core MX8M Plus 2GbE, and i.Core MX8M Plus Fast Ethernet compatible strings. Rename `engicam,icore-mx8mp` to `engicam,icore-mx8mp-base`, as it is the common compatible for all boards by Engicam based on NXP's IMX8MP. Signed-off-by: Patrick Barsanti --- Documentation/devicetree/bindings/arm/fsl.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 6e0dcf4307f1..da3989b16804 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1132,8 +1132,12 @@ properties: - description: Engicam i.Core MX8M Plus SoM based boards items: - enum: - - engicam,icore-mx8mp-edimm2.2 # i.MX8MP Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit - - const: engicam,icore-mx8mp # i.MX8MP Engicam i.Core MX8M Plus SoM + - engicam,icore-mx8mp-edimm2.2 # i.MX8MP Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit + - enum: + - engicam,icore-mx8mp # i.MX8MP Engicam i.Core MX8M Plus SoM + - engicam,icore-mx8mp-2gbe # i.MX8MP Engicam i.Core MX8M Plus 2GbE SoM + - engicam,icore-mx8mp-fasteth # i.MX8MP Engicam i.Core MX8M Plus Fast Ethernet SoM + - const: engicam,icore-mx8mp-base - const: fsl,imx8mp - description: Kontron i.MX8MP OSM-S SoM based Boards From patchwork Tue Nov 26 09:46:26 2024 Content-Type: text/plain; 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Signed-off-by: Patrick Barsanti --- arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts | 1 - arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi | 2 ++ 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts index a02b31c42db4..5eb1af1b0bf8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts @@ -7,7 +7,6 @@ /dts-v1/; -#include "imx8mp.dtsi" #include "imx8mp-icore-mx8mp.dtsi" #include diff --git a/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi index a6319824ea2e..bced63a5f0b3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi @@ -5,6 +5,8 @@ * Copyright (c) 2020 Amarula Solutions(India) */ +#include "imx8mp.dtsi" + / { compatible = "engicam,icore-mx8mp", "fsl,imx8mp"; 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In this way the hexadecimal values are properly aligned. Signed-off-by: Patrick Barsanti --- arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi index bced63a5f0b3..3630928e8602 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi @@ -134,7 +134,7 @@ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 pinctrl_pmic: pmicgrp { fsl,pins = < - MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x41 + MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x41 >; }; From patchwork Tue Nov 26 09:46:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick Barsanti X-Patchwork-Id: 3663 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-lf1-f69.google.com (mail-lf1-f69.google.com [209.85.167.69]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id BF8A83F214 for ; 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Signed-off-by: Patrick Barsanti --- .../boot/dts/freescale/imx8mp-icore-2gbe.dtsi | 17 +++++++ .../dts/freescale/imx8mp-icore-fasteth.dtsi | 45 +++++++++++++++++++ .../boot/dts/freescale/imx8mp-icore.dtsi | 38 ++++++++++++++++ 3 files changed, 100 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-icore-2gbe.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-icore-fasteth.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-icore.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8mp-icore-2gbe.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-icore-2gbe.dtsi new file mode 100644 index 000000000000..65928988b758 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-icore-2gbe.dtsi @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 NXP + * Copyright (c) 2019 Engicam srl + * Copyright (c) 2024 Amarula Solutions + */ + +/dts-v1/; + +#include "imx8mp-icore-mx8mp.dtsi" + +/ { + model = "Engicam i.Core MX8M Plus 2GbE"; + compatible = "engicam,icore-mx8mp-2gbe", + "engicam,icore-mx8mp-base", + "fsl,imx8mp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-icore-fasteth.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-icore-fasteth.dtsi new file mode 100644 index 000000000000..7e4024288851 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-icore-fasteth.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 NXP + * Copyright (c) 2019 Engicam srl + * Copyright (c) 2024 Amarula Solutions + */ + +/dts-v1/; + +#include "imx8mp-icore-mx8mp.dtsi" + +/ { + model = "Engicam i.Core MX8M Plus Fast Ethernet"; + compatible = "engicam,icore-mx8mp-fasteth", + "engicam,icore-mx8mp-base", + "fsl,imx8mp"; +}; + +/* Ethernet */ +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-handle = <ðphy0>; + phy-mode = "rmii"; + snps,rmii_refclk_ext; + snps,force_thresh_dma_mode; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + pinctrl-0 = <&pinctrl_ethphy0>; + pinctrl-names = "default"; + reg = <0>; + reset-assert-us = <500>; + reset-deassert-us = <500>; + reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; + smsc,disable-energy-detect; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-icore.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-icore.dtsi new file mode 100644 index 000000000000..eda9a84a5d91 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-icore.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 NXP + * Copyright (c) 2019 Engicam srl + * Copyright (c) 2024 Amarula Solutions + */ + +/dts-v1/; + +#include "imx8mp-icore-mx8mp.dtsi" + +/ { + model = "Engicam i.Core MX8M Plus"; + compatible = "engicam,icore-mx8mp", + "engicam,icore-mx8mp-base", + "fsl,imx8mp"; +}; + +/* Ethernet */ +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + micrel,led-mode = <0>; + reg = <7>; + }; + }; +}; From patchwork Tue Nov 26 09:46:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick Barsanti X-Patchwork-Id: 3664 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-lf1-f69.google.com (mail-lf1-f69.google.com [209.85.167.69]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id D55003F214 for ; Tue, 26 Nov 2024 10:46:47 +0100 (CET) Received: by mail-lf1-f69.google.com with SMTP id 2adb3069b0e04-53dd6caa49bsf2928251e87.1 for ; Tue, 26 Nov 2024 01:46:47 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1732614407; cv=pass; d=google.com; s=arc-20240605; b=KExxMhZZI9hn7AFXc+uMlpiMtcTH5ZtzbeZsE1snEOds/aQcmmqsCcIonMtDPGU7Bc qGCjp1US8nZ4+cadvHSOVtgY4i1hN9krB1upZNWNWvjLOomFiLQueexj7sotSwUTx133 w2RLvYKFJ1xHkBb8oalS3pk6gDczPxEgdqsBMvmISbyqvk1f9zeUf0Gh8rdTIv2Ll+ZM y7A+I/7LUjbBs+Zim/zbv9W6PMRdypV7qYDx1mMEneBHDh4YdXTsWfAte0eASTe+/e8c vko1vJ/Y/YGZ+KEQsk24f3desZq5uyWbVe8QswIxU9MAl4Fin78JCtqMUzPUGRX15H7D +rbw== ARC-Message-Signature: i=2; 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Signed-off-by: Patrick Barsanti --- arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts | 4 +++- arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi | 2 +- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts index 5eb1af1b0bf8..624c54e48081 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts @@ -12,7 +12,9 @@ / { model = "Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit"; - compatible = "engicam,icore-mx8mp-edimm2.2", "engicam,icore-mx8mp", + compatible = "engicam,icore-mx8mp-edimm2.2", + "engicam,icore-mx8mp", + "engicam,icore-mx8mp-base", "fsl,imx8mp"; chosen { diff --git a/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi index 3630928e8602..81a70bd39c92 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi @@ -8,7 +8,7 @@ #include "imx8mp.dtsi" / { - compatible = "engicam,icore-mx8mp", "fsl,imx8mp"; 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([151.37.190.149]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa51a449c24sm537671966b.178.2024.11.26.01.46.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:46:45 -0800 (PST) From: Patrick Barsanti To: linux-amarula@amarulasolutions.com Cc: dario.binacchi@amarulasolutions.com, patrick.barsanti@amarulasolutions.com Subject: [PATCH 06/11] arm64: dts: freescale: Refactor icore-mx8mp-edimm2.2.dts Date: Tue, 26 Nov 2024 10:46:30 +0100 Message-ID: <20241126094635.881134-7-patrick.barsanti@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241126094635.881134-1-patrick.barsanti@amarulasolutions.com> References: <20241126094635.881134-1-patrick.barsanti@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: patrick.barsanti@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=AnQ1+PZe; spf=pass (google.com: domain of patrick.barsanti@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=patrick.barsanti@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Update includes to the new, more specific dtsi file introduced in commit 8b121f1a4aee ("arm64: dts: freescale: Add Engicam i.Core MX8M Plus family"). Remove redundant code which is already present in such files. Signed-off-by: Patrick Barsanti --- .../freescale/imx8mp-icore-mx8mp-edimm2.2.dts | 23 +------------------ 1 file changed, 1 insertion(+), 22 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts index 624c54e48081..ede931e40188 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "imx8mp-icore-mx8mp.dtsi" +#include "imx8mp-icore.dtsi" #include / { @@ -44,27 +44,6 @@ reg_usdhc2_vmmc: regulator-usdhc2 { }; }; -/* Ethernet */ -&eqos { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eqos>; - phy-handle = <ðphy0>; - phy-mode = "rgmii-id"; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@7 { - compatible = "ethernet-phy-ieee802.3-c22"; - micrel,led-mode = <0>; - reg = <7>; - }; - }; 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([151.37.190.149]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa51a449c24sm537671966b.178.2024.11.26.01.46.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:46:46 -0800 (PST) From: Patrick Barsanti To: linux-amarula@amarulasolutions.com Cc: dario.binacchi@amarulasolutions.com, patrick.barsanti@amarulasolutions.com Subject: [PATCH 07/11] arm64: dts: freescale: Rename imx8mp-icore-mx8mp.dtsi Date: Tue, 26 Nov 2024 10:46:31 +0100 Message-ID: <20241126094635.881134-8-patrick.barsanti@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241126094635.881134-1-patrick.barsanti@amarulasolutions.com> References: <20241126094635.881134-1-patrick.barsanti@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: patrick.barsanti@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=ES0SbfBt; spf=pass (google.com: domain of patrick.barsanti@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=patrick.barsanti@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Rename `imx8mp-icore-mx8mp.dtsi` to `imx8mp-icore-base.dtsi`. This is intended to remove redundancy in the file name while at the same time making the file's purpose more clear. It is being named like this because it is the common dtsi file shared by all boards by Engicam based on NXP's IMX8M Plus. Signed-off-by: Patrick Barsanti --- arch/arm64/boot/dts/freescale/imx8mp-icore-2gbe.dtsi | 2 +- .../{imx8mp-icore-mx8mp.dtsi => imx8mp-icore-base.dtsi} | 0 arch/arm64/boot/dts/freescale/imx8mp-icore-fasteth.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mp-icore.dtsi | 2 +- 4 files changed, 3 insertions(+), 3 deletions(-) rename arch/arm64/boot/dts/freescale/{imx8mp-icore-mx8mp.dtsi => imx8mp-icore-base.dtsi} (100%) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-icore-2gbe.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-icore-2gbe.dtsi index 65928988b758..8068fe80392d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-icore-2gbe.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-icore-2gbe.dtsi @@ -7,7 +7,7 @@ /dts-v1/; -#include "imx8mp-icore-mx8mp.dtsi" +#include "imx8mp-icore-base.dtsi" / { model = "Engicam i.Core MX8M Plus 2GbE"; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-icore-base.dtsi similarity index 100% rename from arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi rename to arch/arm64/boot/dts/freescale/imx8mp-icore-base.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8mp-icore-fasteth.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-icore-fasteth.dtsi index 7e4024288851..bdf3e21cd7ef 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-icore-fasteth.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-icore-fasteth.dtsi @@ -7,7 +7,7 @@ /dts-v1/; -#include "imx8mp-icore-mx8mp.dtsi" +#include "imx8mp-icore-base.dtsi" / { model = "Engicam i.Core MX8M Plus Fast Ethernet"; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-icore.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-icore.dtsi index eda9a84a5d91..b85f51cc4891 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-icore.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-icore.dtsi @@ -7,7 +7,7 @@ /dts-v1/; -#include "imx8mp-icore-mx8mp.dtsi" +#include "imx8mp-icore-base.dtsi" / { model = "Engicam i.Core MX8M Plus"; From patchwork Tue Nov 26 09:46:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick Barsanti X-Patchwork-Id: 3667 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-lf1-f70.google.com (mail-lf1-f70.google.com [209.85.167.70]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 7C3033F214 for ; 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Signed-off-by: Patrick Barsanti --- .../devicetree/bindings/display/panel/panel-simple.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml index 18b63f356bb4..a4b717ea5133 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -31,6 +31,8 @@ properties: # Ampire AM-1280800N3TZQW-T00H 10.1" WQVGA TFT LCD panel - ampire,am-1280800n3tzqw-t00h + # Ampire AM-1280800W8TZQW-T00H 10.1" WXGA TFT LCD panel + - ampire,am-1280800w8tzqw-t00h # Ampire AM-480272H3TMQW-T01H 4.3" WQVGA TFT LCD panel - ampire,am-480272h3tmqw-t01h # Ampire AM-800480L1TMQW-T00H 5" WVGA TFT LCD panel From patchwork Tue Nov 26 09:46:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick Barsanti X-Patchwork-Id: 3668 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f69.google.com (mail-ed1-f69.google.com [209.85.208.69]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id C39E73F214 for ; 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([151.37.190.149]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa51a449c24sm537671966b.178.2024.11.26.01.46.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:46:48 -0800 (PST) From: Patrick Barsanti To: linux-amarula@amarulasolutions.com Cc: dario.binacchi@amarulasolutions.com, patrick.barsanti@amarulasolutions.com Subject: [PATCH 09/11] drm/panel: simple: Add AM-1280800W8TZQW-T00H Date: Tue, 26 Nov 2024 10:46:33 +0100 Message-ID: <20241126094635.881134-10-patrick.barsanti@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241126094635.881134-1-patrick.barsanti@amarulasolutions.com> References: <20241126094635.881134-1-patrick.barsanti@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: patrick.barsanti@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=YHxJ7s7P; spf=pass (google.com: domain of patrick.barsanti@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=patrick.barsanti@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Dario Binacchi Add Ampire, AM-1280800W8TZQW-T00H 10.1" TFT LCD panel timings. Co-developed-by: Michael Trimarchi Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi --- drivers/gpu/drm/panel/panel-simple.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index 06381c628209..d011127cc636 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -759,6 +759,31 @@ static void panel_simple_remove(struct device *dev) put_device(&panel->ddc->dev); } +static const struct drm_display_mode ampire_am_1280800w8tzqw_t00h_mode = { + .clock = 72400, + .hdisplay = 1280, + .hsync_start = 1280 + 40, + .hsync_end = 1280 + 40 + 80, + .htotal = 1280 + 40 + 80 + 40, + .vdisplay = 800, + .vsync_start = 800 + 10, + .vsync_end = 800 + 10 + 18, + .vtotal = 800 + 10 + 18 + 10, +}; + +static const struct panel_desc ampire_am_1280800w8tzqw_t00h = { + .modes = &ire_am_1280800w8tzqw_t00h_mode, + .num_modes = 1, + .bpc = 8, + .size = { + .width = 217, + .height = 136, + }, + .bus_flags = DRM_BUS_FLAG_DE_HIGH, + .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, + .connector_type = DRM_MODE_CONNECTOR_LVDS, +}; + static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { .clock = 71100, .hdisplay = 1280, @@ -4620,6 +4645,9 @@ static const struct of_device_id platform_of_match[] = { { .compatible = "ampire,am-1280800n3tzqw-t00h", .data = &ire_am_1280800n3tzqw_t00h, + }, { + .compatible = "ampire,am-1280800w8tzqw-t00h", + .data = &ire_am_1280800w8tzqw_t00h, }, { .compatible = "ampire,am-480272h3tmqw-t01h", .data = &ire_am_480272h3tmqw_t01h, From patchwork Tue Nov 26 09:46:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick Barsanti X-Patchwork-Id: 3669 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-lj1-f197.google.com (mail-lj1-f197.google.com [209.85.208.197]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 23ED73F214 for ; Tue, 26 Nov 2024 10:46:55 +0100 (CET) Received: by mail-lj1-f197.google.com with SMTP id 38308e7fff4ca-2ffbd3dffe9sf14854701fa.3 for ; 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([151.37.190.149]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa51a449c24sm537671966b.178.2024.11.26.01.46.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:46:50 -0800 (PST) From: Patrick Barsanti To: linux-amarula@amarulasolutions.com Cc: dario.binacchi@amarulasolutions.com, patrick.barsanti@amarulasolutions.com Subject: [PATCH 10/11] dt-bindings: arm: fsl: Add Engicam i.Core MX8M Plus C.TOUCH 2.0 10.1" OF Date: Tue, 26 Nov 2024 10:46:34 +0100 Message-ID: <20241126094635.881134-11-patrick.barsanti@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241126094635.881134-1-patrick.barsanti@amarulasolutions.com> References: <20241126094635.881134-1-patrick.barsanti@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: patrick.barsanti@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=aEKltWx0; spf=pass (google.com: domain of patrick.barsanti@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=patrick.barsanti@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Manoj Sai i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus from Engicam. C.TOUCH 2.0 is a general purpose carrier board with capacitive touch interface support. 10.1" OF is a capacitive touch 10.1" Open Frame panel solutions. i.Core MX8M Plus needs to mount on top of C.TOUCH 2.0 carrier with pluged 10.1" OF for creating complete i.Core MX8M Plus C.TOUCH 2.0 10.1" Open Frame. Signed-off-by: Patrick Barsanti Signed-off-by: Manoj Sai --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index da3989b16804..125081c78fa0 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1133,6 +1133,7 @@ properties: items: - enum: - engicam,icore-mx8mp-edimm2.2 # i.MX8MP Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit + - engicam,icore-mx8mp-ctouch2-of10 # i.MX8MM Engicam i.Core MX8M Plus C.TOUCH 2.0 10.1" OF - enum: - engicam,icore-mx8mp # i.MX8MP Engicam i.Core MX8M Plus SoM - engicam,icore-mx8mp-2gbe # i.MX8MP Engicam i.Core MX8M Plus 2GbE SoM From patchwork Tue Nov 26 09:46:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick Barsanti X-Patchwork-Id: 3670 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f70.google.com (mail-ed1-f70.google.com [209.85.208.70]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 2A9953F214 for ; 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([151.37.190.149]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa51a449c24sm537671966b.178.2024.11.26.01.46.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:46:51 -0800 (PST) From: Patrick Barsanti To: linux-amarula@amarulasolutions.com Cc: dario.binacchi@amarulasolutions.com, patrick.barsanti@amarulasolutions.com Subject: [PATCH 11/11] arm64: dts: freescale: Add Engicam i.Core MX8M Plus C.TOUCH 2.0 10.1" OF Date: Tue, 26 Nov 2024 10:46:35 +0100 Message-ID: <20241126094635.881134-12-patrick.barsanti@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241126094635.881134-1-patrick.barsanti@amarulasolutions.com> References: <20241126094635.881134-1-patrick.barsanti@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: patrick.barsanti@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=Tzck4YZt; spf=pass (google.com: domain of patrick.barsanti@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=patrick.barsanti@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Manoj Sai Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier board. Genaral features: - Ethernet 10/100 - Wifi/BT - USB Type A/OTG - Audio Out - CAN - LVDS panel connector i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus from Engicam. 10.1" OF is a capacitive touch 10.1" Open Frame panel solutions. i.Core MX8M Plus needs to mount on top of C.TOUCH 2.0 carrier with pluged 10.1" OF for creating complete Engicam i.Core MX8M Plus C.TOUCH 2.0 10.1" Open Frame. Add support for it. Signed-off-by: Patrick Barsanti Co-developed-by: Dario Binacchi Signed-off-by: Dario Binacchi Co-developed-by: Michael Trimarchi Signed-off-by: Michael Trimarchi Signed-off-by: Manoj Sai --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../imx8mp-icore-mx8mp-ctouch2-of10.dts | 269 ++++++++++++++++++ 2 files changed, 270 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-ctouch2-of10.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 42e6482a31cb..d5b9b1332af9 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -174,6 +174,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-picoitx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-ctouch2-of10.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-iota2-lumpy.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-bl-osm-s.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-ctouch2-of10.dts b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-ctouch2-of10.dts new file mode 100644 index 000000000000..ab0031ee375c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-ctouch2-of10.dts @@ -0,0 +1,269 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 NXP + * Copyright (c) 2019 Engicam srl + * Copyright (c) 2020 Amarula Solutions(India) + */ + +/dts-v1/; + +#include "imx8mp-icore-fasteth.dtsi" +#include + +/ { + model = "Engicam i.Core MX8M Plus CTOUCH 2.0 10.1\" Open Frame"; + compatible = "engicam,icore-mx8mp-ctouch2-of10", + "engicam,icore-mx8mp-fasteth", + "engicam,icore-mx8mp-base", + "fsl,imx8mp"; + + aliases { + rtc1 = &snvs_rtc; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 100000 0>; + status = "okay"; + + brightness-levels = <0 100>; + num-interpolated-steps = <100>; + default-brightness-level = <80>; + + }; + + chosen { + stdout-path = &uart2; + }; + + panel { + compatible = "ampire,am-1280800w8tzqw-t00h"; + backlight = <&backlight>; + data-mapping = "vesa-24"; + status = "okay"; + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&ldb_lvds_ch0>; + }; + }; + }; + + reg_usb1_vbus: regulator-usb1 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb1>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb1_host_vbus"; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VSD_3V3"; + }; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&lcdif2 { + status = "okay"; +}; + +&lvds_bridge { + status = "okay"; + + ports { + port@1 { + ldb_lvds_ch0: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + }; +}; + +&pca9450 { + interrupt-parent = <&gpio3>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +/* console */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "host"; + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +/* SDCARD */ +&usdhc2 { + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + pinctrl-names = "default" ; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12 + MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x12 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x1d0 + MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER 0x91 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x1d0 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x1d0 + >; + }; + + pinctrl_ethphy0: ethphy0-grp { + fsl,pins = < + MX8MP_IOMUXC_ENET_RD3__GPIO1_IO29 0x16 /* Reset */ + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x41 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 + MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x140 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_reg_usb1: regusb1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x10 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; +};