From patchwork Tue Jan 14 09:11:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 3797 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ej1-f71.google.com (mail-ej1-f71.google.com [209.85.218.71]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 146FC3F174 for ; Tue, 14 Jan 2025 10:11:37 +0100 (CET) Received: by mail-ej1-f71.google.com with SMTP id a640c23a62f3a-ab2e44dc9b8sf439443166b.1 for ; Tue, 14 Jan 2025 01:11:37 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1736845897; cv=pass; d=google.com; s=arc-20240605; b=L4PZq36+S0QTqxah3xKVh4R+3Sta8vlLg08BEqJXMhf75NVPneEtpiIrkS+YBI+FS9 nhp2lTwUFRdGJCASePxbYp5n58Y19R1kmRdaRCPyu7KFF59/Pv2q1vnEP39KFiPpjLmy DfQhujwBOgzye5a9ikIm/6KlQekBcS5G7hY/soK1UDmGghl8AVfnEdxQrvgBnjQyWkbA 04R9vD8KVPjrFiE2Wkd0xOOVf62Ti0IzsO6w9Ts99SG+/Puw7xQ3jkO/gAM57NXscQa7 b9MqXXf4vHAstm4h1zUw5qAN+ie4Xpdtmdq8DKFQI16NBfMNCm7r0T1cF1MtgSriMFXz CC5g== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=6S5PH9sJVsAgnspXh/syAg4l95u6mTZ8i8L3ssxkcv0=; fh=UYqasfdnpc1uY5PXYssg2bWcKQ7vnS1s8V6w0fX9RfI=; b=fx+vVKCgNr0MrwNeZxteEgBELI4hsSVAEENh1FQLYiGO+R9t9ogiHOfQXmlqgpoZde HCt4nFx5yfOfVgpzWcF0TPJgSI99Z93UOyP3erg4J7HE3iWI3bLq4h7+Zxj8dPHwK2ty xLG26GSwmfvN334+S5Tu38oAgYSMWMDkDgnnL06PXvKH/7a2HMx2HrVGcCG1wIpsMpjf D5Kweua2oWnLLguqR27uuFPTNbdPNSiVezda5FBAiPpxzcmfgx9fiv/OVcdpJdLzG5Mg 0TjGt9Hv98A2crOKFlGoseLxq0/YxXKqCKcyizlAgW9eBNE4MyuXlVyNQWCHOyPEcrdD NMkg==; darn=patchwork.amarulasolutions.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="Nn3vc/Rw"; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1736845897; x=1737450697; darn=patchwork.amarulasolutions.com; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date:message-id:reply-to; bh=6S5PH9sJVsAgnspXh/syAg4l95u6mTZ8i8L3ssxkcv0=; b=Vytab7bml9uDipUDPCU+KdYJgIzlaf29PlZa4uK76/jp9QO79ldajJEavYXjeWPR0d nih8n7y9HwEkewa8lO8WlVsH9bNbSFQimyu7i3nZ1tC84q2WPg0r6NxsOPoGOVfneaQM 6L6kfZZW2smLEo/Np3AcpKPRLyQty9XkHRsVk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736845897; x=1737450697; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :x-beenthere:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=6S5PH9sJVsAgnspXh/syAg4l95u6mTZ8i8L3ssxkcv0=; b=SQpVyHuNo2YbEpc918OYY2SatYAw42xFi1e6kUYy9XYP+sVlobBFTPrZDdEZKvtbA0 ZLBRJHNw+GsVphq0WDCFSDLDeDorhOECVYfQuEsokISFPUqSQKeP1LyOQQbbsyfl3/YX /EEeU9szDcstBrLjSHGA2rZ8Zzs54KTpyEUSGyo76DrBLCH8grEaHMIFk1u4+c2iWlVE KKDO/+sXxs6s4n/wP30RoBtW3zbLRlXLyLqHk1UmVlPfH1z9K4IrxDGeHE2ghXQ0q2F5 AwffbejO1L91+R4ylCWpZL+jNBTpNJ4hQYkj7o/CxoKjJGL6JTpv6iWPdXcaypgWUX7k ZgBQ== X-Forwarded-Encrypted: i=2; AJvYcCUElBh74udYLvKyWhcqw4LYeOs32bIrrOXnF5eqtRCWwBsbdDiU0XeyPqLuTW6/NMR8Ire+/k61THy1anBj@patchwork.amarulasolutions.com X-Gm-Message-State: AOJu0YwtQzI13aQVklTZfcUh3ncbcjK3JIMzH6E4mE7oMoxGVMrhfFQW vegwyJDK4g1rNn8E3Ye8pcXjAwY8nArGhj8I2YgSRJLS0siFPTOZyelktl6m8d/nvA== X-Google-Smtp-Source: AGHT+IGh0jXxNJcy9tyyImWasypL9cbplOJRQTIHwvZfBzqfpcp6KqyCXieqZi1ci1uNiUv+btNw9Q== X-Received: by 2002:a17:907:7daa:b0:ab2:bfbe:d09b with SMTP id a640c23a62f3a-ab2c3c79b10mr1923748766b.15.1736845896390; Tue, 14 Jan 2025 01:11:36 -0800 (PST) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a50:99de:0:b0:5d0:acf2:b111 with SMTP id 4fb4d7f45d1cf-5d9c1f2568els6365a12.1.-pod-prod-00-eu; Tue, 14 Jan 2025 01:11:34 -0800 (PST) X-Received: by 2002:a17:907:1b17:b0:aa4:cd1e:c91b with SMTP id a640c23a62f3a-ab2c3c451a3mr1898347566b.7.1736845894532; Tue, 14 Jan 2025 01:11:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1736845894; cv=none; d=google.com; s=arc-20240605; b=Bd/s1snmMnxBYhM6nnUPBSuuaujYaxsJULBcrjmVn7ONzVn3zOx8iKXLNj1KTQNytK MgdtDUYiCB36HVs70CLvJniCTtuA0lKRJIwIJxkRpLtIu9eLpvWBWCrs2deWyhz0fnN3 APvleWl+nCZfTIUYNL88rtjiLpYACGE7OskvU3JQ+cykefiUq/lkNDuiNIwunAaIk/9D 22HekShe/LvdAc/1xUnHR3FkNtVbe/XNAvjJuwkCKeS0PEXfsQ7CIGsJdkC0Ll2TeUDr XgRQv6Z8g4Kn96nQxFPeRXqEZ5mhi1fJBmzs9mY8Lq2NXcCduBlBU8Rpm1AKqovWugQc wZQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=v9KwAAGNxMQMDrQelNKuHl4qwYBQ6VHpn5SteWa63o0=; fh=R4QVkUy9N9G52dU21yOoSm0E7xk8rYofFC9cRclwBHs=; b=Sus4jXj3cuk8/qI99HgkXcxi/NPK8cNLRVCNMvgnuRo3phVylt9hKJj2HM4aujENFl n2M1w00RNnkNW1/PFk09YlWm0jGutZi3J7SZOSUq4avwDO6Lsi3FJJEDyIvxypRJZSy9 z1CXvTxRwjyTSJSVyKV0SnHU4IT9bQC7YAah5m6fdUmQfowetaZYgV6yVA0U0sEl2IaW l2sY3fNsXdCgoMcd00xn0XX+NLMHS/W3i99+ac6L7MFYEOf+WKqFBWmhYSeTwoblkLEc wAOl2KskkWmSHaNwnI3xMQ/aRRD03tGF08ILmG/lH3uHN7GH7J/3jaDCGLfwFaAcM38d 0cxQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="Nn3vc/Rw"; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id a640c23a62f3a-ab33c8a5ac1sor35580766b.0.2025.01.14.01.11.34 for (Google Transport Security); Tue, 14 Jan 2025 01:11:34 -0800 (PST) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Gm-Gg: ASbGncutBB9g3dEfCjxG/YE2VoTrt4OuYiVIpNNyYfcWu7e9gSAOdavJBNOYCZpO6/R FbNzXNe4FmwhHa0BOw4ggYlNlqp2ZKGeCMk6S5vty6vLdtMyyJ49AOiYbxyVzUcMGEi/sSWMGyW 6Ta8qL8LYjtPyarifIrYrvg2Puq1RLBV/rhS6CpsoX0BBIHj7xYowudovN2YQXeRgA8x2sgYo45 gatg4+6KkOOJs/QnmZ5SwkNDJBu397BiH8FAabKqipdBozB1K+4SSsE2dNUrQqa9poGMyWD34BR XKWtx/+kLBlC0W4YORt1CQ== X-Received: by 2002:a17:907:7b86:b0:aa6:8dcb:365b with SMTP id a640c23a62f3a-ab2c3c5c979mr1750106066b.5.1736845893984; Tue, 14 Jan 2025 01:11:33 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.42.147]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab2c95b7317sm599640766b.154.2025.01.14.01.11.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jan 2025 01:11:33 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Krzysztof Kozlowski , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Michael Turquette , Philipp Zabel , Rob Herring , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v3 1/4] dt-bindings: clock: convert stm32 rcc bindings to json-schema Date: Tue, 14 Jan 2025 10:11:13 +0100 Message-ID: <20250114091128.528757-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250114091128.528757-1-dario.binacchi@amarulasolutions.com> References: <20250114091128.528757-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="Nn3vc/Rw"; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The patch converts st,stm32-rcc.txt to the JSON schema, but it does more than that. The old bindings, in fact, only covered the stm32f{4,7} platforms and not the stm32h7. Therefore, to avoid patch submission tests failing, it was necessary to add the corresponding compatible (i. e. st,stm32h743-rcc) and specify that, in this case, 3 are the clocks instead of the 2 required for the stm32f{4,7} platforms. Additionally, the old bindings made no mention of the st,syscfg property, which is used by both the stm32f{4,7} and the stm32h7 platforms. The patch also fixes the files referencing to the old st,stm32-rcc.txt. Signed-off-by: Dario Binacchi Reviewed-by: Krzysztof Kozlowski --- Changes in v3: - Add 'Reviewed-by' tag of Krzysztof Kozlowski Changes in v2: - Fixup patches: 2/6 dt-bindings: reset: st,stm32-rcc: update reference due to rename 3/6 dt-bindings: clock: stm32fx: update reference due to rename - Update the commit message - Reduce the description section of the yaml file - List the items with description for the clocks property - Use only one example - Rename rcc to clock-controller@58024400 for the node of the example .../bindings/clock/st,stm32-rcc.txt | 138 ------------------ .../bindings/clock/st,stm32-rcc.yaml | 111 ++++++++++++++ .../bindings/reset/st,stm32-rcc.txt | 2 +- include/dt-bindings/clock/stm32fx-clock.h | 2 +- 4 files changed, 113 insertions(+), 140 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/st,stm32-rcc.txt create mode 100644 Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml diff --git a/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt deleted file mode 100644 index cfa04b614d8a..000000000000 --- a/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt +++ /dev/null @@ -1,138 +0,0 @@ -STMicroelectronics STM32 Reset and Clock Controller -=================================================== - -The RCC IP is both a reset and a clock controller. - -Please refer to clock-bindings.txt for common clock controller binding usage. -Please also refer to reset.txt for common reset controller binding usage. - -Required properties: -- compatible: Should be: - "st,stm32f42xx-rcc" - "st,stm32f469-rcc" - "st,stm32f746-rcc" - "st,stm32f769-rcc" - -- reg: should be register base and length as documented in the - datasheet -- #reset-cells: 1, see below -- #clock-cells: 2, device nodes should specify the clock in their "clocks" - property, containing a phandle to the clock device node, an index selecting - between gated clocks and other clocks and an index specifying the clock to - use. -- clocks: External oscillator clock phandle - - high speed external clock signal (HSE) - - external I2S clock (I2S_CKIN) - -Example: - - rcc: rcc@40023800 { - #reset-cells = <1>; - #clock-cells = <2> - compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; - reg = <0x40023800 0x400>; - clocks = <&clk_hse>, <&clk_i2s_ckin>; - }; - -Specifying gated clocks -======================= - -The primary index must be set to 0. - -The secondary index is the bit number within the RCC register bank, starting -from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30). - -It is calculated as: index = register_offset / 4 * 32 + bit_offset. -Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31). - -To simplify the usage and to share bit definition with the reset and clock -drivers of the RCC IP, macros are available to generate the index in -human-readble format. - -For STM32F4 series, the macro are available here: - - include/dt-bindings/mfd/stm32f4-rcc.h - -Example: - - /* Gated clock, AHB1 bit 0 (GPIOA) */ - ... { - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)> - }; - - /* Gated clock, AHB2 bit 4 (CRYP) */ - ... { - clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)> - }; - -Specifying other clocks -======================= - -The primary index must be set to 1. - -The secondary index is bound with the following magic numbers: - - 0 SYSTICK - 1 FCLK - 2 CLK_LSI (low-power clock source) - 3 CLK_LSE (generated from a 32.768 kHz low-speed external - crystal or ceramic resonator) - 4 CLK_HSE_RTC (HSE division factor for RTC clock) - 5 CLK_RTC (real-time clock) - 6 PLL_VCO_I2S (vco frequency of I2S pll) - 7 PLL_VCO_SAI (vco frequency of SAI pll) - 8 CLK_LCD (LCD-TFT) - 9 CLK_I2S (I2S clocks) - 10 CLK_SAI1 (audio clocks) - 11 CLK_SAI2 - 12 CLK_I2SQ_PDIV (post divisor of pll i2s q divisor) - 13 CLK_SAIQ_PDIV (post divisor of pll sai q divisor) - - 14 CLK_HSI (Internal ocscillator clock) - 15 CLK_SYSCLK (System Clock) - 16 CLK_HDMI_CEC (HDMI-CEC clock) - 17 CLK_SPDIF (SPDIF-Rx clock) - 18 CLK_USART1 (U(s)arts clocks) - 19 CLK_USART2 - 20 CLK_USART3 - 21 CLK_UART4 - 22 CLK_UART5 - 23 CLK_USART6 - 24 CLK_UART7 - 25 CLK_UART8 - 26 CLK_I2C1 (I2S clocks) - 27 CLK_I2C2 - 28 CLK_I2C3 - 29 CLK_I2C4 - 30 CLK_LPTIMER (LPTimer1 clock) - 31 CLK_PLL_SRC - 32 CLK_DFSDM1 - 33 CLK_ADFSDM1 - 34 CLK_F769_DSI -) - -Example: - - /* Misc clock, FCLK */ - ... { - clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)> - }; - - -Specifying softreset control of devices -======================================= - -Device nodes should specify the reset channel required in their "resets" -property, containing a phandle to the reset device node and an index specifying -which channel to use. -The index is the bit number within the RCC registers bank, starting from RCC -base address. -It is calculated as: index = register_offset / 4 * 32 + bit_offset. -Where bit_offset is the bit offset within the register. -For example, for CRC reset: - crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140 - -example: - - timer2 { - resets = <&rcc STM32F4_APB1_RESET(TIM2)>; - }; diff --git a/Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml b/Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml new file mode 100644 index 000000000000..779e547700be --- /dev/null +++ b/Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/st,stm32-rcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 Reset Clock Controller + +maintainers: + - Dario Binacchi + +description: | + The RCC IP is both a reset and a clock controller. + The reset phandle argument is the bit number within the RCC registers bank, + starting from RCC base address. + +properties: + compatible: + oneOf: + - items: + - const: st,stm32f42xx-rcc + - const: st,stm32-rcc + - items: + - enum: + - st,stm32f469-rcc + - const: st,stm32f42xx-rcc + - const: st,stm32-rcc + - items: + - const: st,stm32f746-rcc + - const: st,stm32-rcc + - items: + - enum: + - st,stm32f769-rcc + - const: st,stm32f746-rcc + - const: st,stm32-rcc + - items: + - const: st,stm32h743-rcc + - const: st,stm32-rcc + + reg: + maxItems: 1 + + '#reset-cells': + const: 1 + + '#clock-cells': + enum: [1, 2] + + clocks: + minItems: 2 + maxItems: 3 + + st,syscfg: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to system configuration controller. It can be used to control the + power domain circuitry. + +required: + - compatible + - reg + - '#reset-cells' + - '#clock-cells' + - clocks + - st,syscfg + +allOf: + - if: + properties: + compatible: + contains: + const: st,stm32h743-rcc + then: + properties: + '#clock-cells': + const: 1 + description: | + The clock index for the specified type. + clocks: + items: + - description: high speed external (HSE) clock input + - description: low speed external (LSE) clock input + - description: Inter-IC sound (I2S) clock input + else: + properties: + '#clock-cells': + const: 2 + description: | + - The first cell is the clock type, possible values are 0 for + gated clocks and 1 otherwise. + - The second cell is the clock index for the specified type. + clocks: + items: + - description: high speed external (HSE) clock input + - description: Inter-IC sound (I2S) clock input + +additionalProperties: false + +examples: + # Reset and Clock Control Module node: + - | + clock-controller@58024400 { + compatible = "st,stm32h743-rcc", "st,stm32-rcc"; + reg = <0x58024400 0x400>; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>; + st,syscfg = <&pwrcfg>; + }; + +... diff --git a/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt b/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt index 01db34375192..384035e8e60b 100644 --- a/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt +++ b/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt @@ -3,4 +3,4 @@ STMicroelectronics STM32 Peripheral Reset Controller The RCC IP is both a reset and a clock controller. -Please see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt +Please see Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h index e5dad050d518..b6ff9c68cb3f 100644 --- a/include/dt-bindings/clock/stm32fx-clock.h +++ b/include/dt-bindings/clock/stm32fx-clock.h @@ -10,7 +10,7 @@ * List of clocks which are not derived from system clock (SYSCLOCK) * * The index of these clocks is the secondary index of DT bindings - * (see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt) + * (see Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml) * * e.g: ; From patchwork Tue Jan 14 09:11:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 3798 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f70.google.com (mail-ed1-f70.google.com [209.85.208.70]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 5A14E3F174 for ; Tue, 14 Jan 2025 10:11:38 +0100 (CET) Received: by mail-ed1-f70.google.com with SMTP id 4fb4d7f45d1cf-5d09962822bsf5025743a12.1 for ; Tue, 14 Jan 2025 01:11:38 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1736845898; cv=pass; d=google.com; s=arc-20240605; b=FFuNpZ4vRimS8nH1dI2ptRw3RmhmWX183aTtk83u7WvlQxvXbsaE+m/uIcUDHR+NoC /run8BFwJi6DGRKvOZqlHL632h2EirPIijT41n74T6SS6663c+vLQRwW8K0V1fhFvAFG +gnGW8nVZ+B9/YJi9g2FYeDLrkjDjy+j7aRMS4UIiNG4vyDJuoimvZGTE+jp5MJRHwtU jvwpcwB8LpTghWDjta34eahJWSVZZSCmtHhwKfZBjDsfL4ft0Bept+UwXYh2o+UZi0pn HEKIb4ikazhSOPNo7uDOt5/2nP5OV48ir2czKkU8rxg7tVqH++fsMyBONfAH16FXTi5K bZHw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=tfPTQ5RrgKlBw0K3eyTkq2nXKdfcH3v4iarOeTHRdRk=; fh=vXuyk5lMgCiK2W8AMKaGBbmiASZHD4w0hrWcPlOmqV8=; b=OuDBB9uyvCKbRrl3/IHgsnso85ggYzxSZe/LlKjV7GJX+k7EZts8Gml3Dq6mURjkdM yEQyhc7ejPm1l8rNC/ZQxZ8793s0PKupkE2Y0rEWuIQEnt5Eg81XnbsObGhFm3KoSdha +b5QZ6Wcerm22yVF0/rof/2qbDTy7WM91AVLU8DxBlI12goYGBtm14VdSYkZmf/77xFL JxRVuZ7l70M1mKr/OoMc9SZ/95YKQ6ZvqTiY5DZK/71YRb3tBCiH7VJQI9hX0ghe2zYf 7fLQ0dUPg2x3aX61bdq2utUOQF6KEKBh0QtlP28OFG1G1fVAL1AzYlq6qdrCv+HbLHE0 J+Dw==; darn=patchwork.amarulasolutions.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=nyYf7OLF; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1736845898; x=1737450698; darn=patchwork.amarulasolutions.com; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date:message-id:reply-to; bh=tfPTQ5RrgKlBw0K3eyTkq2nXKdfcH3v4iarOeTHRdRk=; b=N1IohvtrozREIwTbhGcmcw/Sq2WZhQ8c543vpHRQ3kWhm4B47hELx5V/BD7oXMeU8r /zW6rT5M9HZHtbrOoAMCDRn2LurUcQpeFhjCATcfJ3hD7X1SrUq8lkqvZ5uWm6p5/C6/ PC+beMZcI2fY1y/aNglUpX5gnIlluTfNHTpww= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736845898; x=1737450698; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :x-beenthere:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=tfPTQ5RrgKlBw0K3eyTkq2nXKdfcH3v4iarOeTHRdRk=; b=aYG+goDNGv2zFX+xXamg0zY5y5urfKG652zQZGV/8ofeqSTTm5pCQFGuyY1dkJTB5z b1K1F6uGECE7vZjlZ+D260JK3a+0LORm6ZGrJlukDxx3cc19F4htVKIG0OaG8Hgofg0L ImtNXvdXmUQI0YsH/5vQo4H9FrT2mvxhjh5U5pUf0UgF5H90c2YUPkCIJIvFSu/ADhJL cDLeYz6pcfvvaVSxD5TxuAfh5/bnEa/U8EsY6tBdxtaL0N/fDujXXgJU0zFXpVTclzka qVfXzroAiJQUZTVsRL0iHLkKKQs1O+SJEI6n7rJoJeU46bBpucAeTg1diw/Mm0oHBJ6Q 6yIg== X-Forwarded-Encrypted: i=2; AJvYcCVE+/vHPYqxly1xJ4fvRpMwdsy2pZlExxOFEfGf8L1fJAceW+iuJDqHn/ANU9vZF4V5LQKAxlBK4G38SvOy@patchwork.amarulasolutions.com X-Gm-Message-State: AOJu0Yx2Ju43SbXaO/ITATdDOFhQflN7nw1AT4ey18rT1x/Vkw94n0sR Q/vdktCBxC3POl41y+87gcscCRVLB6osGucRINCmvWhxXksVtOC2PSl6IuKRQalaIQ== X-Google-Smtp-Source: AGHT+IEvbgCKlsuuVmV1gpD5cNOOYWeuvMAoo4Tgkc9ZceKqtjVAhXL0cWQTUZQz+2laDDZAxRLAYA== X-Received: by 2002:a05:6402:5241:b0:5d0:eb2d:db97 with SMTP id 4fb4d7f45d1cf-5d972e64807mr22454414a12.25.1736845897907; Tue, 14 Jan 2025 01:11:37 -0800 (PST) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a50:a41b:0:b0:5d3:e99c:a4c9 with SMTP id 4fb4d7f45d1cf-5d9f17b4043ls88600a12.1.-pod-prod-06-eu; Tue, 14 Jan 2025 01:11:36 -0800 (PST) X-Received: by 2002:a17:906:f59a:b0:aa6:9503:aa73 with SMTP id a640c23a62f3a-ab2abcb1135mr2374130766b.51.1736845896156; Tue, 14 Jan 2025 01:11:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1736845896; cv=none; d=google.com; s=arc-20240605; b=KQZeMEMqVj7M3Sahy3l423ypXQ3wrI2estqe3WezaZxxy+76jCIk1pj+heQZuL/iGj mIcDy+XrhqRaRnRoY3chbvjrp5TubZSO5JeYYTf611aFAUT4dGdIF3TNFXMrhPM6Ty25 YKDb7DSQyXIa1GJCaM/i8GJ1svQ8EMeO4zMTH7h/qqNZXs4RRnJQfyg5psf+Hth7edAU EjFQkqTp/55KU3aKYlzT1say01CRLpBqVRBbAvpFiajwg5JlzR7ABc80S00v5aiBBNt6 P6AGE+3oE8UXH7Ma//iRdLMCNNstx2QPkejvldFirHoRWkPTlrBzc6Z2iXCKL+6ap1wN VIhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=siX7FCTD0wixOLRdc1jnWvPAPiYOmQR7y0biY9ez4Ss=; fh=aLWgEPM+DVTqoB30lVkyyzFDp2H0k8cJSxUm9Og2ZbE=; b=Bo+XzSPkxKYkzEX29RWLz7gy/Tsm+wkUIqv4m8QZMVc4VS5kzaM8Mco0HMfr68Dd4v 56HkQpAc4c/kY/nsUS7kzS2G8IeVPkxIH2WzBY9+eHHVpX98qFpIKQRgIfz6dxvVEW4h a+Hmaa8FVEQGy0TD6FWwGwe6vn96gCmiH5kjdDbeK8wNwWmeI8XKMtEB22BgLeqMvvnu xLIKrTiN87ZmmSdaIDSUKN7kKZwuFhRfToJXPFbMHycmeSZCrfrOhG0rScvIRazObY9k eYweeTpAAs+v3qAEG4Ejp7IAQ8V5SZCP7LZQvfC1frbU6dTF0goH6Jgw3DltQ+VMhltV s5Xg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=nyYf7OLF; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id a640c23a62f3a-ab2c8f5c49csor549932266b.2.2025.01.14.01.11.36 for (Google Transport Security); Tue, 14 Jan 2025 01:11:36 -0800 (PST) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Gm-Gg: ASbGncunHKhH260ScVCtQ08vYN2xybLazdYh8Tah2YTQMmTkvfoMksZs9sUUFh3DY9D 9FLPe5v3/WX0bxnCTvkdEXUZSpgE6YwjSDYUSgFtNl/UlqgcvHg4PhMeSVsAFmgTijqAexUFflJ r4z6ozychJbsC14asjcipjcSyS8xYhCOnsHb3b0zb0QB6qLjcMFtN15vqW1fSEWjb+OauWMCwA1 8Z4LMUo+kcug33yWTVdGe7WF61VwxwZyZW1BdNOWpCdEhXStLtSNpeoEAI6PfoAsPSTTB2e+vRn h57Aqa+g1hUR/elKkH2GHw== X-Received: by 2002:a17:907:704:b0:aa6:a87e:f2e1 with SMTP id a640c23a62f3a-ab2abcb198emr2288992866b.56.1736845895670; Tue, 14 Jan 2025 01:11:35 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.42.147]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab2c95b7317sm599640766b.154.2025.01.14.01.11.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jan 2025 01:11:35 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Krzysztof Kozlowski , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Michael Turquette , Rob Herring , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v3 2/4] dt-bindings: clock: st,stm32-rcc: support spread spectrum clocking Date: Tue, 14 Jan 2025 10:11:14 +0100 Message-ID: <20250114091128.528757-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250114091128.528757-1-dario.binacchi@amarulasolutions.com> References: <20250114091128.528757-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=nyYf7OLF; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The addition of DT bindings for enabling and tuning spread spectrum clocking generation is available only for the main PLL of stm32f{4,7} platforms. Signed-off-by: Dario Binacchi Reviewed-by: Krzysztof Kozlowski --- Changes in v3: - Add 'Reviewed-by' tag of Krzysztof Kozlowski Changes in v2: - Update the commit message - Change st,ssc-modmethod type from non-unique-string-array to string .../bindings/clock/st,stm32-rcc.yaml | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml b/Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml index 779e547700be..628bbbcf2875 100644 --- a/Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml +++ b/Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml @@ -56,6 +56,26 @@ properties: Phandle to system configuration controller. It can be used to control the power domain circuitry. + st,ssc-modfreq-hz: + description: + The modulation frequency for main PLL (in Hz) + + st,ssc-moddepth-permyriad: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The modulation rate for main PLL (in permyriad, i.e. 0.01%) + minimum: 25 + maximum: 200 + + st,ssc-modmethod: + $ref: /schemas/types.yaml#/definitions/string + description: + The modulation techniques for main PLL. + items: + enum: + - center-spread + - down-spread + required: - compatible - reg @@ -81,6 +101,10 @@ allOf: - description: high speed external (HSE) clock input - description: low speed external (LSE) clock input - description: Inter-IC sound (I2S) clock input + st,ssc-modfreq-hz: false + st,ssc-moddepth-permyriad: false + st,ssc-modmethod: false + else: properties: '#clock-cells': @@ -98,6 +122,18 @@ additionalProperties: false examples: # Reset and Clock Control Module node: + - | + clock-controller@40023800 { + compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; + reg = <0x40023800 0x400>; + #clock-cells = <2>; + #reset-cells = <1>; + clocks = <&clk_hse>, <&clk_i2s_ckin>; + st,syscfg = <&pwrcfg>; + st,ssc-modfreq-hz = <10000>; + st,ssc-moddepth-permyriad = <200>; + st,ssc-modmethod = "center-spread"; + }; - | clock-controller@58024400 { compatible = "st,stm32h743-rcc", "st,stm32-rcc"; From patchwork Tue Jan 14 09:11:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 3799 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f70.google.com (mail-ed1-f70.google.com [209.85.208.70]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id D8E693F174 for ; Tue, 14 Jan 2025 10:11:39 +0100 (CET) Received: by mail-ed1-f70.google.com with SMTP id 4fb4d7f45d1cf-5d3d9d6293fsf4580318a12.0 for ; Tue, 14 Jan 2025 01:11:39 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1736845899; cv=pass; d=google.com; s=arc-20240605; b=HQ+bLqviAxXN+Doop7dg1i0r7A/BjTyKjrVojCZWvj+B6LLbDpd5x0ZvLEa+aZW+7Q 3ys5deJBRwQan1OXVlFSXk3D0s2v8UL12lj0J6PAfgOn3YigqZdVKfAYwsxz+9qleI8n dFAbekGO1Dr/TdTxZzIXrM0ZWzhSGFHZwsUFE4ff2/yj+5wWarKGwe+OLPeegtUx9BWo 7lSr+HjLY27WGwPZfneBJNMgC1NAIoRoxwnGaBMpU18Em0mwtaVoJOKJYzDFk2yUunqq qzy91p38qmo6gaKmLLKEEB/GKDfC9jhCIlBrwsT/X82MOBT8qrkTJoHY69VcCxy17bQW ZWfQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=XtbjdETKR/arvBjKY7fm1vE6kJB4kTw5aeYbUgY4Kd0=; fh=zK9fWrrsFFOto7JJZkReofxEC2dpjbeVrB2x2ArWUKU=; b=Ar5eRfdYSEJgAy02ClchE7Pfm0RkYsN3T0iSJZfSMRrEfUUSdGy7ash+XOts5O0FUw zojAB3HKon1hTXEYpmxHdxg7oIcAx1p/MAGEEyhrqyiWVN8fFEOeIfY/4aoNhvSTy1yx 9SDwWCpDoHUlyY1OLVayjCDXDPrfFS6HYAP3r5SLE7eaDx+x7q8F86Wr16If/3w65wAY ef3+exJEEFMJp572t1fexD2GTKCVlBoyd3jM5CJ5OR1tK69EVEz8PvQTTyXW9mIQ1b7C eKAzHtdVAg0d0RCRBobGJGqx1js5gI3NI9geKj9Baj0VXfKFZ7/IxCgjgjzlDnix6No6 ka3A==; darn=patchwork.amarulasolutions.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=HMsljGCg; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1736845899; x=1737450699; darn=patchwork.amarulasolutions.com; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date:message-id:reply-to; bh=XtbjdETKR/arvBjKY7fm1vE6kJB4kTw5aeYbUgY4Kd0=; b=dJ6wWEiLZ+ZJUMy+NPfx8pYcdZiejjIIeu3QjuSGEnLzzE1PpJmG8e6APb5MCdYn1S qsXYsisQiRlqNVs71lCQ3RipC7Jd4HAJDpe2TWWAxjqGrfyIWMha1TxTFJClACK32DIR YjB0ywnCd/s2gB/zWL4xxpgYBIxBXLd5GDkxk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736845899; x=1737450699; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :x-beenthere:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=XtbjdETKR/arvBjKY7fm1vE6kJB4kTw5aeYbUgY4Kd0=; b=wJE8pG8Cf0CIRGxNeDGXRC06rpgZ7hiPOlwekI5GHHXKpTj4yovwABnZ/rK36Pg7Ki 6n44hBxYdUdwQ+9Y/3dFEHynAgsUGW1F6rXBIbhQRF6WPzcDSj1uJ5y4RkuhvOyCeEfX yWCbD/3EUb3EvbaBpOoDhOaOPFOcq6dJUAX+qKYOXvW0u1DoGh9VvTc4BOodqix+ZeDT xmTB/HNIP0brc2p76RMhaKkuln6IQLCCpgxygC9F7mGqToobjN4z27qoBEZxXygxgYXq DRkwIedkl6/WAkVg0l/Lb5OJubE17n+2RtH5SZv6DIrmw+FNj2+nFskHfYYD+b40psYM P3jw== X-Forwarded-Encrypted: i=2; AJvYcCUyJUEpMLEemxpwDKuF958tYw4WWCLhyptHNhIWLINitgcXzY7qKj3SA1fcDMkYunSdzv7Sj5Uxc5il1j0p@patchwork.amarulasolutions.com X-Gm-Message-State: AOJu0YzgiN4ebUHSrf+divMEbHm6R2EyD8f9v0otp3+sqF7D22Z48FaJ Cg0YeEoS1vkZB7THnrjz5067sSbzqgXooAKaQ7IsEUdGl8xaCpZuQG4tytFjUOiy2WlmcLXLKw= = X-Google-Smtp-Source: AGHT+IFAQP4ouRS4ycEzD7VpqBOenrLU2LpfC4uXotai0A+vBRCiQ6WQygeMfvHKYV2YYPOIVPBfrg== X-Received: by 2002:a05:6402:3217:b0:5cf:bcaf:98ec with SMTP id 4fb4d7f45d1cf-5d972e48686mr21394562a12.26.1736845899390; Tue, 14 Jan 2025 01:11:39 -0800 (PST) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a50:8d15:0:b0:5d3:bf89:291f with SMTP id 4fb4d7f45d1cf-5d9851d963fls1855602a12.0.-pod-prod-07-eu; Tue, 14 Jan 2025 01:11:37 -0800 (PST) X-Received: by 2002:a17:906:6a1e:b0:aae:bac6:6659 with SMTP id a640c23a62f3a-ab2ab675c7bmr2234752566b.7.1736845897493; Tue, 14 Jan 2025 01:11:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1736845897; cv=none; d=google.com; s=arc-20240605; b=FC9+TZhEEmXguVZBp2qsj4Z3USWjYL0jR5B2yDTzaiv4ZY5D/+OVh2ZfuFSGN06l1Q iurSwPu6ftODp9h+v4fH+OEVIqP7C/JHUXYqWwGfa9ZbqC8EC+n7qEsCtyxBM//UTzRq aE+mXcVl+YPvbqpJlbMtKxoacw4ojw/d7svefR4P8CkFUdRNamJnC0dorEhN3qLy0gyD lK3874dJ6AwMaf8Gn/04KbPLBm1zSvbkqEojZ5yErl3TOGyhrBi/lRsywq3CX0xTzZSX iYpgKqi90RvdqTr0QoGzjRSTK6SU3UTi0+zLYbcurqKgqS8/jzaFvRBezNio8NfdTjdL mdPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=4PuckIz6TtMrm6FhKB7AMqxRoyDL7dpmszhuAU6edRg=; fh=LKhgYKqW/DH7bOgdnVELRgL+gR1eISg3bEXUN1rI9pA=; b=EBcyyiCr9Y+6B+J0WIM6f9BvdkDGeBTN+GHhCKfgjrx5Y4ujiioMWzQ/rIXUVnEh2i pHSww1oo2MS6sp0tNJQoDm7seA9jx+Rv/jLEXLxXSfBbcqZII4BIq1oSJWAqdlobhjQT SBPSrgrL5PHnO6XaaQprYe3qnf/SxEeXTSufjMIJBxg2qsDtmfuCwvb0GTNq4Oy7J9iJ XNZ0MqiKpNzQhVNzvvCMlFXhNENjPEcpCB6JEjxZJwTmnlp913CSemm+FX6cWZTMFU09 bUKZFufgKeCttJs4hpdbKUlMYn18+W3bEhrUTo4eRV8juiIAcmC4jolkAPRBN8TpPz4v kySQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=HMsljGCg; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id a640c23a62f3a-ab2c93f24b8sor420186966b.14.2025.01.14.01.11.37 for (Google Transport Security); Tue, 14 Jan 2025 01:11:37 -0800 (PST) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Gm-Gg: ASbGncslG86luW9iJoaIv22SttqBSUC3hr/mnQf36LI/otB5sS1IzKA6UzXsYpWwSAv 7cPauVOwqO+gDPIcOgQ/Obob+UNP9HX1PoiJp81E7y72PvaugL3q60dSAOMzg9gtNVmw7/XfZg7 V2zyfxqsibbJ/CScsC7267kKob66sUvBtQkCPqsFoVOwcIhjPAq3Fk8Lnxx1B4ddA84Booq/A6v FRachLH7J5bdHpl7r18x+lMmbM67yu6NPikYEtU/97LFZvAILUkvjjc/sOn0U1j010QMyR7t2CV dGaINppDcdqoLFOtwOY1ZQ== X-Received: by 2002:a17:907:7e95:b0:aaf:c19a:cc1c with SMTP id a640c23a62f3a-ab2ab6c6625mr1898191166b.22.1736845897042; Tue, 14 Jan 2025 01:11:37 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.42.147]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab2c95b7317sm599640766b.154.2025.01.14.01.11.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jan 2025 01:11:36 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Alexandre Torgue , Maxime Coquelin , Michael Turquette , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v3 3/4] clk: stm32f4: use FIELD helpers to access the PLLCFGR fields Date: Tue, 14 Jan 2025 10:11:15 +0100 Message-ID: <20250114091128.528757-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250114091128.528757-1-dario.binacchi@amarulasolutions.com> References: <20250114091128.528757-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=HMsljGCg; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Use GENMASK() along with FIELD_GET() and FIELD_PREP() helpers to access the PLLCFGR fields instead of manually masking and shifting. Signed-off-by: Dario Binacchi --- (no changes since v1) drivers/clk/clk-stm32f4.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c index 07c13ebe327d..db1c56c8d54f 100644 --- a/drivers/clk/clk-stm32f4.c +++ b/drivers/clk/clk-stm32f4.c @@ -5,6 +5,7 @@ * Inspired by clk-asm9260.c . */ +#include #include #include #include @@ -39,6 +40,8 @@ #define STM32F4_RCC_DCKCFGR 0x8c #define STM32F7_RCC_DCKCFGR2 0x90 +#define STM32F4_RCC_PLLCFGR_N_MASK GENMASK(14, 6) + #define NONE -1 #define NO_IDX NONE #define NO_MUX NONE @@ -632,9 +635,11 @@ static unsigned long stm32f4_pll_recalc(struct clk_hw *hw, { struct clk_gate *gate = to_clk_gate(hw); struct stm32f4_pll *pll = to_stm32f4_pll(gate); + unsigned long val; unsigned long n; - n = (readl(base + pll->offset) >> 6) & 0x1ff; + val = readl(base + pll->offset); + n = FIELD_GET(STM32F4_RCC_PLLCFGR_N_MASK, val); return parent_rate * n; } @@ -673,9 +678,10 @@ static int stm32f4_pll_set_rate(struct clk_hw *hw, unsigned long rate, n = rate / parent_rate; - val = readl(base + pll->offset) & ~(0x1ff << 6); + val = readl(base + pll->offset) & ~STM32F4_RCC_PLLCFGR_N_MASK; + val |= FIELD_PREP(STM32F4_RCC_PLLCFGR_N_MASK, n); - writel(val | ((n & 0x1ff) << 6), base + pll->offset); + writel(val, base + pll->offset); if (pll_state) stm32f4_pll_enable(hw); From patchwork Tue Jan 14 09:11:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 3800 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f69.google.com (mail-ed1-f69.google.com [209.85.208.69]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 4E2683F174 for ; Tue, 14 Jan 2025 10:11:41 +0100 (CET) Received: by mail-ed1-f69.google.com with SMTP id 4fb4d7f45d1cf-5d9e4d33f04sf1323154a12.0 for ; Tue, 14 Jan 2025 01:11:41 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1736845901; cv=pass; d=google.com; s=arc-20240605; b=Oe5tP4JgOeDWHUAhEcIgYW/n4oLAmdTSZkNrdtZgaL02Rri4lJwRUTFSOCGUVmeg9u X7+7i2zmy5gbszuMoWps7cbhtifmvSK7RCNW5tRap/q/EAmaDCHJ8cii1YZuHSSE10Hu IxMC9DFBeVZsMHIltJv45YstGi7nSp/+l3zaiO8ntXq9uCVFT6GHOo1N1sjJGRl8nvPM tubqdtjT8yDdlUGXRlnmOi3ugrKhkL3Axs8HLNqCQaZlsvupUkgeZUeueEIPH4MixnOw ZMfD4OeTIvvs+s8ng5Wdf5WrbQMhDjokjYAKx+kFYB5Cp1N/173urlX2c2T5+02WQKCt 3WIg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=XcJqL5FQyd0ZfT26caCSXkH/91/MCtI0HGlaOeFOIN0=; fh=yxRRQfvoSo/5C5Ll+p/lClycCWv310/0LTgmwq9qQDs=; b=YUA1SRFqfC/0WhbVYD+Lr0IPWevDG4Bg5ZCBi7CvmLT9Y84V4KtQHI/0Y7n/e7yWOl 5n0KLaiNKqZALN+0QZFDwcbF3iFf4WIVItVq/SysHTuwId6k3wz7uiqEPk78d8QxvIb+ ehqy3lL1r0JSE5KwF8J1rnoTuXPGgxJTa0IqTb73dwMdWoaMyxBSZcf3EPr/0DZm3gnc l49ZAs7dpWl9sc6H5ost0F1xHCRN99gDrgSae6YeOhuxqtCoLU60UHOMbEc+Lw1TMC70 MQe/Pqtso9lyYSLB7aS4E1gYwTdshpRmx+PMKeuJjoST7Dkj4ssYPdxO8o2u6Y71ahk2 Q6Lg==; darn=patchwork.amarulasolutions.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=dUyz1U1z; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1736845901; x=1737450701; darn=patchwork.amarulasolutions.com; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date:message-id:reply-to; bh=XcJqL5FQyd0ZfT26caCSXkH/91/MCtI0HGlaOeFOIN0=; b=n1i/hhTA/qMghKrLEvHKAtuf3kjkmWewLF9RI2ClGMMW04dkZH4HogchhRXgUoHddZ awV89pMV1YJHsTTW5WlMGlSN/JMod43ttPBQg+1XfZ3HeYvFws4c1g5og6XHaksXSR4E t6Ov061F0zMKrZlaglPSDeuFeJwUMdy07cPB0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736845901; x=1737450701; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :x-beenthere:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=XcJqL5FQyd0ZfT26caCSXkH/91/MCtI0HGlaOeFOIN0=; b=KRRKvA4lV3yoUhbiKPztWxnVcwGztCc2muT/E9nQ//73hoXwnCpT99obrFJVlScPDH qX3CVp918ZlBPGj5lGtpnW2IdkgMg/8/cg3i9Y4IhCiTK/U/Pg9ITuU8oBcPrqRg2z/r 9cbLQBnoED/1V38PSflXAZLBgg3vuhb1kFP9uGqt5jcCqUkmrmWLZclMv2AQo2BymuIY 8CUi3NHnD0AfV5Zk8mDLcgHysAbfOEUl1RcKErTaoqyN7WwQFDWt7V0lysDEwkHg33jj wVXrbZk597oOVlpgaW59kxOCT332y92OyAiJrf52hXXGGz9V4hXmAbBJCX+QlTYe0/uq nDgQ== X-Forwarded-Encrypted: i=2; AJvYcCX8LgVZ+Z5Ntr57xyo8gqc1nXqUjOX3+sAgrfESKqTArVEG0lkTMoJoossr6E2nsqfhKuOA47xOKCsG7H2N@patchwork.amarulasolutions.com X-Gm-Message-State: AOJu0YyTCRlp+wRqEhvxvfc3+hAB1+OGTKUXajaLnZngTWp6QiHIcBTh gYWte+P+v0AeKHNSTBxyjIrxhnfxG7+5uH3dpD6Z2Ja6LnuPX2KWL2tBH4fCT5ufRw== X-Google-Smtp-Source: AGHT+IH9OsW5Xk337IMxhWp55pKvjpgaxUwmrDh6a0RkSQRPPOnadn9XEYd+EsBtVhB7K2yzyPm7gg== X-Received: by 2002:a05:6402:5243:b0:5d9:b84:a01f with SMTP id 4fb4d7f45d1cf-5d972e169a3mr25166801a12.18.1736845900895; Tue, 14 Jan 2025 01:11:40 -0800 (PST) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a50:8a98:0:b0:5d9:6a7e:1514 with SMTP id 4fb4d7f45d1cf-5d9b32d2b46ls905879a12.0.-pod-prod-02-eu; Tue, 14 Jan 2025 01:11:39 -0800 (PST) X-Received: by 2002:a17:906:d555:b0:ab2:fc5d:1795 with SMTP id a640c23a62f3a-ab2fc5d1d7emr1188530166b.37.1736845899010; Tue, 14 Jan 2025 01:11:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1736845899; cv=none; d=google.com; s=arc-20240605; b=SaKYaH5sZR8LPKuRtodEOshx7lmdcziYRCc95Zh8ZWGeyg4Q32w31cLBVQosELmtFt uMXciZuKrRjms8xKaJ7JdNFAUEAH+JvvDjOWTcnflksJJ+yDZq5he/OPFpWQ3cnOT+xN fHdMQXKKVDBz/GVXFmrskO0vLrlk+hC+xjUytuLtRVEv0aw0iJiuTap+1hbuEjGmIyjP Zr0689TXx7RLktvjnGAcGAGuJwNWiydNzXOyJxUYN8aPm44LoMNXWr2k/15M2+Cs7BJH epdvKATW4aZct1MVPLJ/LnPsTHGIueSMZZSK8VyD6rcWlsEZT8L534/WZDNpS5jZrJpY TdlA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=CUkrlqyJMSue4T39ZMAvPFJocT8wJ7xje6FDMMbnAa0=; fh=LKhgYKqW/DH7bOgdnVELRgL+gR1eISg3bEXUN1rI9pA=; b=AzJDTAw/+mHAh0qUBcn/v9zQA6O02Kub3MycziQcIcMjY+HUWDMXCDKStdL26d0r3C BB5HsiG0dLaQjJz/PgbDxidCWANsbssSAPzcXCmt7Rn+/ig+8EGEm6+eZTMvY6GxBsGF t4E9oEP2KIn9C9J0KbP2fD3/pnfe3VghmlptOBbgRYo7TQBquTKhTKDOyoJVYWWsVLQf QlU2atgkjyS1zjqZTVb1jXs0jmf4RoOUZGxo5ExoZmFslPjsEouLu/kDa3NWM7D2n/HA grBNZOgOJTi8mL3AlUn9FR8N/Ps7z4Ve8KAeHEw67yC4Sk0m4xvSvmcy2PtZiEpZTKp9 4tIw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=dUyz1U1z; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id a640c23a62f3a-ab2c939c557sor405095566b.17.2025.01.14.01.11.38 for (Google Transport Security); Tue, 14 Jan 2025 01:11:38 -0800 (PST) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Gm-Gg: ASbGncuwdBZ8jbIDKK7Hy14n8tYBlNQdp/AW7D3MSlaneD+fd+e6pFGx+aL1x4xc07Z L/LrPaoSEyqzpX+Rq+J0R0EhzaX4wGPjA9T2KiDwtlkWKbl7FnkNlMraqYBgcSr9cusatJKjnzl /BUnJxcr6b0gGnuDq2EvwAoMNAERTtGhxrEgwItnNoe5WIRNsAdqHMDkI8K5BEu2h1a1qdReZXW BMdW6d0iL2xJCBP/cjr6T4KUtmLyVnoyXEDGKPpPBWozJFRNfcGxkB5ykKxwvwdjnuE/qEAx8ue iCHeLB78jq8E1zxcU2t9oA== X-Received: by 2002:a17:907:d8e:b0:aae:ea52:3a5 with SMTP id a640c23a62f3a-ab2abdc0bc4mr2261767166b.44.1736845898485; Tue, 14 Jan 2025 01:11:38 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.42.147]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab2c95b7317sm599640766b.154.2025.01.14.01.11.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jan 2025 01:11:38 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Alexandre Torgue , Maxime Coquelin , Michael Turquette , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v3 4/4] clk: stm32f4: support spread spectrum clock generation Date: Tue, 14 Jan 2025 10:11:16 +0100 Message-ID: <20250114091128.528757-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250114091128.528757-1-dario.binacchi@amarulasolutions.com> References: <20250114091128.528757-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=dUyz1U1z; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Support spread spectrum clock generation for the main PLL, the only one for which this functionality is available. Tested on the STM32F469I-DISCO board. Signed-off-by: Dario Binacchi --- Changes in v3: - Changes to patch 4/4 "clk: stm32f4: support spread spectrum clock generation" according to Stephen Boyd's suggestions. - Drop pr_debug() from stm32f4_pll_set_ssc() - Add __init to stm32f4_pll_init_ssc() and stm32f4_pll_ssc_parse_dt(). - Add const to conf parameter of stm32f4_pll_init_ssc(). - Use fwnode_property_match_property_string() to parse the st,ssc-modmethod dts property. Changes in v2: - Fixup patches: 2/6 dt-bindings: reset: st,stm32-rcc: update reference due to rename 3/6 dt-bindings: clock: stm32fx: update reference due to rename to 1/6 dt-bindings: clock: convert stm32 rcc bindings to json-schema - Changes to dt-bindings: clock: convert stm32 rcc bindings to json-schema - Changes to dt-bindings: clock: st,stm32-rcc: support spread spectrum clocking drivers/clk/clk-stm32f4.c | 143 +++++++++++++++++++++++++++++++++++++- 1 file changed, 140 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c index db1c56c8d54f..f476883bc93b 100644 --- a/drivers/clk/clk-stm32f4.c +++ b/drivers/clk/clk-stm32f4.c @@ -35,6 +35,7 @@ #define STM32F4_RCC_APB2ENR 0x44 #define STM32F4_RCC_BDCR 0x70 #define STM32F4_RCC_CSR 0x74 +#define STM32F4_RCC_SSCGR 0x80 #define STM32F4_RCC_PLLI2SCFGR 0x84 #define STM32F4_RCC_PLLSAICFGR 0x88 #define STM32F4_RCC_DCKCFGR 0x8c @@ -42,6 +43,12 @@ #define STM32F4_RCC_PLLCFGR_N_MASK GENMASK(14, 6) +#define STM32F4_RCC_SSCGR_SSCGEN BIT(31) +#define STM32F4_RCC_SSCGR_SPREADSEL BIT(30) +#define STM32F4_RCC_SSCGR_RESERVED_MASK GENMASK(29, 28) +#define STM32F4_RCC_SSCGR_INCSTEP_MASK GENMASK(27, 13) +#define STM32F4_RCC_SSCGR_MODPER_MASK GENMASK(12, 0) + #define NONE -1 #define NO_IDX NONE #define NO_MUX NONE @@ -367,6 +374,16 @@ static const struct stm32f4_gate_data stm32f769_gates[] __initconst = { { STM32F4_RCC_APB2ENR, 30, "mdio", "apb2_div" }, }; +enum stm32f4_pll_ssc_mod_type { + STM32F4_PLL_SSC_CENTER_SPREAD, + STM32F4_PLL_SSC_DOWN_SPREAD, +}; + +static const char * const stm32f4_ssc_mod_methods[] __initconst = { + [STM32F4_PLL_SSC_DOWN_SPREAD] = "down-spread", + [STM32F4_PLL_SSC_CENTER_SPREAD] = "center-spread", +}; + /* * This bitmask tells us which bit offsets (0..192) on STM32F4[23]xxx * have gate bits associated with them. Its combined hweight is 71. @@ -512,6 +529,12 @@ static const struct clk_div_table pll_divr_table[] = { { 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 }, { 0 } }; +struct stm32f4_pll_ssc { + unsigned int mod_freq; + unsigned int mod_depth; + enum stm32f4_pll_ssc_mod_type mod_type; +}; + struct stm32f4_pll { spinlock_t *lock; struct clk_gate gate; @@ -519,6 +542,8 @@ struct stm32f4_pll { u8 bit_rdy_idx; u8 status; u8 n_start; + bool ssc_enable; + struct stm32f4_pll_ssc ssc_conf; }; #define to_stm32f4_pll(_gate) container_of(_gate, struct stm32f4_pll, gate) @@ -541,6 +566,7 @@ struct stm32f4_vco_data { u8 offset; u8 bit_idx; u8 bit_rdy_idx; + bool sscg; }; static const struct stm32f4_vco_data vco_data[] = { @@ -661,6 +687,32 @@ static long stm32f4_pll_round_rate(struct clk_hw *hw, unsigned long rate, return *prate * n; } +static void stm32f4_pll_set_ssc(struct clk_hw *hw, unsigned long parent_rate, + unsigned int ndiv) +{ + struct clk_gate *gate = to_clk_gate(hw); + struct stm32f4_pll *pll = to_stm32f4_pll(gate); + struct stm32f4_pll_ssc *ssc = &pll->ssc_conf; + u32 modeper, incstep; + u32 sscgr; + + sscgr = readl(base + STM32F4_RCC_SSCGR); + /* reserved field must be kept at reset value */ + sscgr &= STM32F4_RCC_SSCGR_RESERVED_MASK; + + modeper = DIV_ROUND_CLOSEST(parent_rate, 4 * ssc->mod_freq); + incstep = DIV_ROUND_CLOSEST(((1 << 15) - 1) * ssc->mod_depth * ndiv, + 5 * 10000 * modeper); + sscgr |= STM32F4_RCC_SSCGR_SSCGEN | + FIELD_PREP(STM32F4_RCC_SSCGR_INCSTEP_MASK, incstep) | + FIELD_PREP(STM32F4_RCC_SSCGR_MODPER_MASK, modeper); + + if (ssc->mod_type) + sscgr |= STM32F4_RCC_SSCGR_SPREADSEL; + + writel(sscgr, base + STM32F4_RCC_SSCGR); +} + static int stm32f4_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { @@ -683,6 +735,9 @@ static int stm32f4_pll_set_rate(struct clk_hw *hw, unsigned long rate, writel(val, base + pll->offset); + if (pll->ssc_enable) + stm32f4_pll_set_ssc(hw, parent_rate, n); + if (pll_state) stm32f4_pll_enable(hw); @@ -788,6 +843,84 @@ static struct clk_hw *clk_register_pll_div(const char *name, return hw; } +static int __init stm32f4_pll_init_ssc(struct clk_hw *hw, + const struct stm32f4_pll_ssc *conf) +{ + struct clk_gate *gate = to_clk_gate(hw); + struct stm32f4_pll *pll = to_stm32f4_pll(gate); + struct clk_hw *parent; + unsigned long parent_rate; + int pll_state; + unsigned long n, val; + + parent = clk_hw_get_parent(hw); + if (!parent) { + pr_err("%s: failed to get clock parent\n", __func__); + return -ENODEV; + } + + parent_rate = clk_hw_get_rate(parent); + + pll->ssc_enable = true; + memcpy(&pll->ssc_conf, conf, sizeof(pll->ssc_conf)); + + pll_state = stm32f4_pll_is_enabled(hw); + + if (pll_state) + stm32f4_pll_disable(hw); + + val = readl(base + pll->offset); + n = FIELD_GET(STM32F4_RCC_PLLCFGR_N_MASK, val); + + pr_debug("%s: pll: %s, parent: %s, parent-rate: %lu, n: %lu\n", + __func__, clk_hw_get_name(hw), clk_hw_get_name(parent), + parent_rate, n); + + stm32f4_pll_set_ssc(hw, parent_rate, n); + + if (pll_state) + stm32f4_pll_enable(hw); + + return 0; +} + +static int __init stm32f4_pll_ssc_parse_dt(struct device_node *np, + struct stm32f4_pll_ssc *conf) +{ + int ret; + const char *s; + + if (!conf) + return -EINVAL; + + ret = of_property_read_u32(np, "st,ssc-modfreq-hz", &conf->mod_freq); + if (ret) + return ret; + + ret = of_property_read_u32(np, "st,ssc-moddepth-permyriad", + &conf->mod_depth); + if (ret) { + pr_err("%pOF: missing st,ssc-moddepth-permyriad\n", np); + return ret; + } + + ret = fwnode_property_match_property_string(of_fwnode_handle(np), + "st,ssc-modmethod", + stm32f4_ssc_mod_methods, + ARRAY_SIZE(stm32f4_ssc_mod_methods)); + if (ret < 0) { + pr_err("%pOF: failed to get st,ssc-modmethod\n", np); + return ret; + } + + conf->mod_type = ret; + + pr_debug("%pOF: SSCG settings: mod_freq: %d, mod_depth: %d mod_method: %s [%d]\n", + np, conf->mod_freq, conf->mod_depth, s, conf->mod_type); + + return 0; +} + static struct clk_hw *stm32f4_rcc_register_pll(const char *pllsrc, const struct stm32f4_pll_data *data, spinlock_t *lock) { @@ -1695,7 +1828,8 @@ static void __init stm32f4_rcc_init(struct device_node *np) const struct of_device_id *match; const struct stm32f4_clk_data *data; unsigned long pllm; - struct clk_hw *pll_src_hw; + struct clk_hw *pll_src_hw, *pll_vco_hw; + struct stm32f4_pll_ssc ssc_conf; base = of_iomap(np, 0); if (!base) { @@ -1754,8 +1888,8 @@ static void __init stm32f4_rcc_init(struct device_node *np) clk_hw_register_fixed_factor(NULL, "vco_in", pll_src, 0, 1, pllm); - stm32f4_rcc_register_pll("vco_in", &data->pll_data[0], - &stm32f4_clk_lock); + pll_vco_hw = stm32f4_rcc_register_pll("vco_in", &data->pll_data[0], + &stm32f4_clk_lock); clks[PLL_VCO_I2S] = stm32f4_rcc_register_pll("vco_in", &data->pll_data[1], &stm32f4_clk_lock); @@ -1900,6 +2034,9 @@ static void __init stm32f4_rcc_init(struct device_node *np) of_clk_add_hw_provider(np, stm32f4_rcc_lookup_clk, NULL); + if (!stm32f4_pll_ssc_parse_dt(np, &ssc_conf)) + stm32f4_pll_init_ssc(pll_vco_hw, &ssc_conf); + return; fail: kfree(clks);