From patchwork Thu May 29 05:10:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Trimarchi X-Patchwork-Id: 4071 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ej1-f70.google.com (mail-ej1-f70.google.com [209.85.218.70]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id AC86C3F0E8 for ; Thu, 29 May 2025 07:10:41 +0200 (CEST) Received: by mail-ej1-f70.google.com with SMTP id a640c23a62f3a-ad55a32b7afsf28633066b.3 for ; Wed, 28 May 2025 22:10:41 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1748495441; cv=pass; d=google.com; s=arc-20240605; b=i5Nq8eyi4bDg//T6CA6znRVvkWd1RHMmkalBawH9XjLIFllJ8oUTcz1e6R47vHNq2o 1WQRrYv43ALTUXSGiz0CFiWFYpXUS/7Hk6/18+J+zY0MxYfMrDjlz3udlxaIs2CFZIy9 zg6k/Q8+kEsQeZH7kMUaXHaLLLy2nzW06Y4cr5RGEgw+1/2t4yTdEdmDPLn+LmxySEuq PWb2ReTOM4sH0OTqWG0DFefZp9wS3RvqlRT+Z4XTCiXM+zOdKOparbmW316ErqbbIy/3 Ra+QUUXJpvjx519I4AtJotsXQKf4efIm9WVnWpcxtbBl1ioFJDNFn7t1I6VOYVnGXVsg 7o9g== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:message-id:date:subject:cc:to :from:dkim-signature; bh=hVsyEohUF++ZDd7ErtSv9873cI2BCgBnozlvlFiU9I8=; fh=UTvqp+EJh31fPfZnvJqYotCbY7PPkX+M2U769eGTask=; b=LJ8gILjNpMIz/g9MC6DoPV9yqQ6OWgsVd3MngKlflKD0Ofk0xfTB3SWT/C6WJxY1bO 1xafbW+VTpQNHcudKmnTyU/bh0nx9gKKdA3oeSx0IEaLEflirhoweg8zKcDg+e1bD8Mw rpt4s6m74c4eUBry2OwgJaW8mtXM/CdF9vHCvyfsjixIwFRCOvESHvWnrL6v8LT3/vre oDuYsvzooyrjWM/FiklNWNC6a+V9WiHupObpV8efzwAPymsoVZWiQjjG+L243gNTUUg2 iYn+5+ZNeNL5oGTcqjo+Cs2JBMHLS9C+EAQGMGYZXdOUzG1dxhpa4VUnyeWRrVnBdXzc S0zg==; darn=patchwork.amarulasolutions.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=du0j5ueQ; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1748495441; x=1749100241; darn=patchwork.amarulasolutions.com; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:message-id:date:subject:cc:to:from :from:to:cc:subject:date:message-id:reply-to; bh=hVsyEohUF++ZDd7ErtSv9873cI2BCgBnozlvlFiU9I8=; b=hKh5vMQJbuGuLvYD+nQK5Mfgg4rFXRGiFrav9Q+GirFWOfqt2QAJ8hONVxs63SJkE6 Lz3rOgkxdsq7Lgu/ES4+Ri3gn0j59MdxS5ka42UljO1C9u4h4EWoIiJqVoMJMvNvKpmC t6SiBMgkwybpjhIDovvkbFPQtXu7lnIqPhsH8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748495441; x=1749100241; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :message-id:date:subject:cc:to:from:x-beenthere:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=hVsyEohUF++ZDd7ErtSv9873cI2BCgBnozlvlFiU9I8=; b=ffgBUUNYQOvbMBabK/rBQVDyTYKE75pY0YuJOkSRHmOQnht/bPwPyzFq3ldzFMnQ+7 6ZPo9ijq6VkeAp08PCCBsYzX+SUcmrmd38apQiTuVjcL3xjXPqiibQxkRIVy1VL/vr4s r1DnR7QVwBXQ4rPHq9G2fdAvQBABi9G/Auh8kgr7FrTFfZI/yXbD4xPYD6Hzihdy/5Bw RO0iC5xyO5bS4VxRwvbND9sfLAIq4mM4lYmdcaCnXj5O3Aj+9bQF5C4JJndwVeEAtkH9 OfP+Ikk/4OK2WrAWi42HVtHVcvea5pzCk3RxTgExCGNdBSW5SHk8ZDeDWZ96cgOo9Y9A St9w== X-Forwarded-Encrypted: i=2; AJvYcCUvye5kaRJ4VK3fkwehjDcdtqfJynO0UsZl+LeDkEViut6HQWxgr84LERlMAXpx2322iQ8rqJiIomf8d+U6@patchwork.amarulasolutions.com X-Gm-Message-State: AOJu0YwOxH54QgqTDER5ozuIeC/pyneqduvxYcfSglvfoRODEKBfimod w7nqtueT7I9WSgvLdK8kX92vdvJVdpC30mUrfggiAEdSqktJDzVdCO3Gp5k79C++LmsSPQ== X-Google-Smtp-Source: AGHT+IGEZfvpjA0aUiiRDP6MLKj0z71n7AhDPyeG8xRFdHSqQClkd2Rj7tZkGD78jZw4prLQTS/h8w== X-Received: by 2002:a05:6402:2694:b0:602:2e1d:5c41 with SMTP id 4fb4d7f45d1cf-602d9069654mr16446936a12.7.1748495441214; Wed, 28 May 2025 22:10:41 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com; h=AZMbMZdcOEWAGlcsVFYkMa4TPa79ExU+aThqHg+tE+sWE5QQiw== Received: by 2002:a05:6402:234d:b0:602:cda:a6ea with SMTP id 4fb4d7f45d1cf-60538d26f5cls373612a12.1.-pod-prod-07-eu; Wed, 28 May 2025 22:10:38 -0700 (PDT) X-Received: by 2002:a17:906:3b5b:b0:ad8:a935:b8e8 with SMTP id a640c23a62f3a-ad8a935b9c8mr274229766b.5.1748495438192; Wed, 28 May 2025 22:10:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1748495438; cv=none; d=google.com; s=arc-20240605; b=A62X0G3Hascl4Y62n9oxzUxOLdzC+UxqcX2zm2jectzexziZl0d+VtE72m6XkwmxbB YsDfiiZhLAbiNDohaG1H93EUAygvavVjcMfbd8kR8RYK5GnsmCnDLAKMDxLtj/2W2lM0 yoJOBBmaLJHwVGtD0mcMo9Jlxknfb5v4nVQwvG8NU7LufIEnSgorLK5g/WyWoE+oVhc5 I1ZQcYzqBLSEiPig9pAB+h1Jx4NH33HeSPXyEEkeI7nMVxJjzmEeKTr92nSSOEg7SZ2Z Rr2/g/Pj4+6gUBUeF5hHTO2pUd0BoKFQktQ0/AQrSPp5TipDBi8TCKUtgpwobxphR22o 1J4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:dkim-signature; bh=zb4aYV45N00iNXiI97BWpcFaBu+md2CP4FmscY/3vPM=; fh=Hfs6kc7NonJliQzL+XI3vpRVkCjQUDso9eobHIGAhXE=; b=FO6rTZ8fygMDvRiZx0VdS+eSf82mzqDXnB+1oJeIEM6vwenjGMqQywxaW2mz4LEA0f fGEm1CsNGJIdfCUpV3HMx7NmA44iLhVBINesKEPEijyjZ14QMU7rqzR2rMXxgMCJGQQ+ yrYNQdnxcR2opQ+FIeoI+XtnJozAqShUBhMDP9AKaGnsV8P5FsexmHkUFJijCrkRTkfz R4ZiG7Tk+WVdhg6QBLXfBtMe6461SmYhwSsZ/HMFMAsnhT5mOEUv+2VrJS8iD2MmGNsx +6upsOAm0T9DZEoXB/bZHJjO3trHkRYWCYI8M2B6b2nnI3MqgoxiAPPSZdrt0Od6+cn2 cHzA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=du0j5ueQ; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id a640c23a62f3a-ada4b688943sor30715866b.0.2025.05.28.22.10.38 for (Google Transport Security); Wed, 28 May 2025 22:10:38 -0700 (PDT) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Gm-Gg: ASbGncvy8lkwP+cisElS+nWgSnd8mwiKpFxG2K0KY8z/ffejbVjR9xxdZpB9XuG/pJ2 Qr9Xw2swbryPDUxE7187VhGlDc5ikgXCqm4ozApKPqNQQXB9djJm+p23f+Uk+V30QuKB829Z1zC zuO7+Ef4rtrkATeUh8B0JF2l5Pfeg1YbFDdOZJgQYl1HA18h6VcoM1Q428togQPX6F59EN0G7hk 0zI9dbGuh5FIYG4di5oT2JXDDp5zOuqMD1lZGkdfnHU8N0E6qXMNhvnD/WdJv6h+oLI8gNTa0dI uue8gS+apLRSibkBaTHW9aERiH3GXn2dcd8xj8lkkLqLQSuVqYJSGmpK5cjVdv+ZHsSxcQI+jmS Q8EnAAGkPAk7mQkt63RuHw7OqhA== X-Received: by 2002:a17:907:8e95:b0:ad2:4eef:d33a with SMTP id a640c23a62f3a-ad85b065bc8mr1726699566b.15.1748495430988; Wed, 28 May 2025 22:10:30 -0700 (PDT) Received: from panicking.amarulasolutions.com ([2001:b07:6467:4426:71fa:236b:ca2b:119e]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ada5d82becbsm70776566b.39.2025.05.28.22.10.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 May 2025 22:10:30 -0700 (PDT) From: Michael Trimarchi To: u-boot@lists.denx.de Cc: linux-amarula@amarulasolutions.com, cniedermaier@dh-electronics.com, Michael Trimarchi , Peng Fan , Adam Ford , Lukasz Majewski , Sean Anderson , Simon Glass , Stefano Babic , Tom Rini Subject: [PATCH v3 1/4] clk: imx: add i.MX6UL clk driver Date: Thu, 29 May 2025 07:10:15 +0200 Message-ID: <20250529051024.42340-1-michael@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=du0j5ueQ; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add i.MX6UL clk driver for i.MX6UL CLK driver model usage Reviewed-by: Peng Fan Signed-off-by: Michael Trimarchi Reviewed-by: Christoph Niedermaier --- Changes in v3: - Add all uarts definition - Move OSC on top suggested - Drop an invalid clock definition - Move some pll before they are referenced Changes in v2: - None drivers/clk/imx/Kconfig | 8 + drivers/clk/imx/Makefile | 1 + drivers/clk/imx/clk-imx6ul.c | 290 +++++++++++++++++++++++++++++++++++ 3 files changed, 299 insertions(+) create mode 100644 drivers/clk/imx/clk-imx6ul.c diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig index d17a54fb9b3..705d4a8e2ac 100644 --- a/drivers/clk/imx/Kconfig +++ b/drivers/clk/imx/Kconfig @@ -14,6 +14,14 @@ config CLK_IMX6Q help This enables DM/DTS support for clock driver in i.MX6Q platforms. +config CLK_IMX6UL + bool "Clock support for i.MXUL" + depends on ARCH_MX6 + select CLK + select CLK_CCF + help + This enables DM/DTS support for clock driver in i.MX6UL platforms. + config CLK_IMX8 bool "Clock support for i.MX8" depends on ARCH_IMX8 diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index a89ee7acb12..b10221a195c 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_$(PHASE_)CLK_CCF) += clk-gate2.o clk-pllv3.o clk-pfd.o obj-$(CONFIG_$(PHASE_)CLK_IMX6Q) += clk-imx6q.o +obj-$(CONFIG_$(PHASE_)CLK_IMX6UL) += clk-imx6ul.o obj-$(CONFIG_CLK_IMX8) += clk-imx8.o ifdef CONFIG_CLK_IMX8 diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c new file mode 100644 index 00000000000..bd52c1d487c --- /dev/null +++ b/drivers/clk/imx/clk-imx6ul.c @@ -0,0 +1,290 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Amarula Solutions Software Engineering + * Michael Trimarchi, Amarula Solutions Software Engineering, michael@amarulasolutions.com + */ + +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +static int imx6ul_clk_request(struct clk *clk) +{ + debug("%s: request clk id %ld\n", __func__, clk->id); + + if (clk->id < IMX6UL_CLK_DUMMY || clk->id >= IMX6UL_CLK_END) { + printf("%s: Invalid clk ID #%lu\n", __func__, clk->id); + return -EINVAL; + } + + return 0; +} + +static struct clk_ops imx6ul_clk_ops = { + .request = imx6ul_clk_request, + .set_rate = ccf_clk_set_rate, + .get_rate = ccf_clk_get_rate, + .enable = ccf_clk_enable, + .disable = ccf_clk_disable, +}; + +static const char *const pll_bypass_src_sels[] = { "osc", "dummy", }; +static const char *const pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", }; +static const char *const bch_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; +static const char *const gpmi_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; + +static const char *const enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", + "pll3_pfd3_454m", "dummy", "dummy", "dummy", }; +static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; +static const char *const periph_sels[] = { "periph_pre", "periph_clk2", }; +static const char *const periph2_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", + "pll4_audio_div", }; +static const char *const periph_clk2_sels[] = { "pll3_usb_otg", "osc", "pll2_bypass_src", }; +static const char *const periph2_clk2_sels[] = { "pll3_usb_otg", "osc", }; +static const char *const perclk_sels[] = { "ipg", "osc", }; + +static const char *const periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", + "pll2_198m", }; +static const char *const uart_sels[] = { "pll3_80m", "osc", }; +static const char *const ecspi_sels[] = { "pll3_60m", "osc", }; + +static int imx6ul_clk_probe(struct udevice *dev) +{ + struct clk osc_clk; + void *base; + int ret; + + /* Anatop clocks */ + base = (void *)ANATOP_BASE_ADDR; + + clk_dm(IMX6UL_CLK_DUMMY, clk_register_fixed_rate(NULL, "dummy", 0)); + + ret = clk_get_by_name(dev, "osc", &osc_clk); + if (ret) + return ret; + + clk_dm(IMX6UL_CLK_OSC, dev_get_clk_ptr(osc_clk.dev)); + + clk_dm(IMX6UL_CLK_PLL2, + imx_clk_pllv3(dev, IMX_PLLV3_GENERIC, "pll2_bus", "osc", + base + 0x30, 0x1)); + clk_dm(IMX6UL_CLK_PLL3, + imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3", "osc", + base + 0x10, 0x3)); + clk_dm(IMX6UL_PLL3_BYPASS_SRC, + imx_clk_mux(dev, "pll3_bypass_src", base + 0x10, 14, 1, + pll_bypass_src_sels, + ARRAY_SIZE(pll_bypass_src_sels))); + clk_dm(IMX6UL_PLL3_BYPASS, + imx_clk_mux_flags(dev, "pll3_bypass", base + 0x10, 16, 1, + pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), + CLK_SET_RATE_PARENT)); + clk_dm(IMX6UL_CLK_PLL3_USB_OTG, + imx_clk_gate(dev, "pll3_usb_otg", "pll3_bypass", base + 0x10, + 13)); + clk_dm(IMX6UL_CLK_PLL3_80M, + imx_clk_fixed_factor(dev, "pll3_80m", "pll3_usb_otg", 1, 6)); + clk_dm(IMX6UL_CLK_PLL3_60M, + imx_clk_fixed_factor(dev, "pll3_60m", "pll3_usb_otg", 1, 8)); + clk_dm(IMX6UL_CLK_PLL2_PFD0, + imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0)); + clk_dm(IMX6UL_CLK_PLL2_PFD1, + imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1)); + clk_dm(IMX6UL_CLK_PLL2_PFD2, + imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2)); + clk_dm(IMX6UL_CLK_PLL2_PFD3, + imx_clk_pfd("pll2_pfd3_396m", "pll2_bus", base + 0x100, 3)); + clk_dm(IMX6UL_CLK_PLL6, + imx_clk_pllv3(dev, IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, + 0x3)); + clk_dm(IMX6UL_CLK_PLL6_ENET, + imx_clk_gate(dev, "pll6_enet", "pll6", base + 0xe0, 13)); + + /* CCM clocks */ + base = dev_read_addr_ptr(dev); + if (!base) + return -EINVAL; + + clk_dm(IMX6UL_CLK_GPMI_SEL, + imx_clk_mux(dev, "gpmi_sel", base + 0x1c, 19, 1, gpmi_sels, + ARRAY_SIZE(gpmi_sels))); + clk_dm(IMX6UL_CLK_BCH_SEL, + imx_clk_mux(dev, "bch_sel", base + 0x1c, 18, 1, bch_sels, + ARRAY_SIZE(bch_sels))); + clk_dm(IMX6UL_CLK_USDHC1_SEL, + imx_clk_mux(dev, "usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, + ARRAY_SIZE(usdhc_sels))); + clk_dm(IMX6UL_CLK_USDHC2_SEL, + imx_clk_mux(dev, "usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, + ARRAY_SIZE(usdhc_sels))); + clk_dm(IMX6UL_CLK_ECSPI_SEL, + imx_clk_mux(dev, "ecspi_sel", base + 0x38, 18, 1, ecspi_sels, + ARRAY_SIZE(ecspi_sels))); + clk_dm(IMX6UL_CLK_UART_SEL, + imx_clk_mux(dev, "uart_sel", base + 0x24, 6, 1, uart_sels, + ARRAY_SIZE(uart_sels))); + clk_dm(IMX6UL_CLK_ENFC_SEL, + imx_clk_mux(dev, "enfc_sel", base + 0x2c, 15, 3, enfc_sels, + ARRAY_SIZE(enfc_sels))); + clk_dm(IMX6UL_CLK_PERCLK_SEL, + imx_clk_mux(dev, "perclk_sel", base + 0x1c, 6, 1, perclk_sels, + ARRAY_SIZE(perclk_sels))); + clk_dm(IMX6UL_CLK_PERIPH_PRE, + imx_clk_mux(dev, "periph_pre", base + 0x18, 18, 2, + periph_pre_sels, ARRAY_SIZE(periph_pre_sels))); + clk_dm(IMX6UL_CLK_PERIPH2_PRE, + imx_clk_mux(dev, "periph2_pre", base + 0x18, 21, 2, + periph2_pre_sels, ARRAY_SIZE(periph2_pre_sels))); + clk_dm(IMX6UL_CLK_PERIPH_CLK2_SEL, + imx_clk_mux(dev, "periph_clk2_sel", base + 0x18, 12, 2, + periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels))); + clk_dm(IMX6UL_CLK_PERIPH2_CLK2_SEL, + imx_clk_mux(dev, "periph2_clk2_sel", base + 0x18, 20, 1, + periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels))); + clk_dm(IMX6UL_CLK_PERIPH, + imx_clk_busy_mux(dev, "periph", base + 0x14, 25, 1, base + 0x48, + 5, periph_sels, ARRAY_SIZE(periph_sels))); + clk_dm(IMX6UL_CLK_AHB, + imx_clk_busy_divider(dev, "ahb", "periph", base + 0x14, 10, 3, + base + 0x48, 1)); + clk_dm(IMX6UL_CLK_PERIPH_CLK2, + imx_clk_divider(dev, "periph_clk2", "periph_clk2_sel", + base + 0x14, 27, 3)); + clk_dm(IMX6UL_CLK_PERIPH2_CLK2, + imx_clk_divider(dev, "periph2_clk2", "periph2_clk2_sel", + base + 0x14, 0, 3)); + clk_dm(IMX6UL_CLK_IPG, + imx_clk_divider(dev, "ipg", "ahb", base + 0x14, 8, 2)); + clk_dm(IMX6UL_CLK_ENFC_PRED, + imx_clk_divider(dev, "enfc_pred", "enfc_sel", base + 0x2c, 18, + 3)); + clk_dm(IMX6UL_CLK_ENFC_PODF, + imx_clk_divider(dev, "enfc_podf", "enfc_pred", base + 0x2c, 21, + 6)); + clk_dm(IMX6UL_CLK_GPMI_PODF, + imx_clk_divider(dev, "gpmi_podf", "gpmi_sel", base + 0x24, 22, + 3)); + clk_dm(IMX6UL_CLK_BCH_PODF, + imx_clk_divider(dev, "bch_podf", "bch_sel", base + 0x24, 19, 3)); + clk_dm(IMX6UL_CLK_PERCLK, + imx_clk_divider(dev, "perclk", "perclk_sel", base + 0x1c, 0, 6)); + clk_dm(IMX6UL_CLK_UART_PODF, + imx_clk_divider(dev, "uart_podf", "uart_sel", base + 0x24, 0, + 6)); + clk_dm(IMX6UL_CLK_USDHC1_PODF, + imx_clk_divider(dev, "usdhc1_podf", "usdhc1_sel", base + 0x24, + 11, 3)); + clk_dm(IMX6UL_CLK_USDHC2_PODF, + imx_clk_divider(dev, "usdhc2_podf", "usdhc2_sel", base + 0x24, + 16, 3)); + clk_dm(IMX6UL_CLK_ECSPI_PODF, + imx_clk_divider(dev, "ecspi_podf", "ecspi_sel", base + 0x38, 19, + 6)); + + clk_dm(IMX6UL_CLK_APBHDMA, + imx_clk_gate2(dev, "apbh_dma", "bch_podf", base + 0x68, 4)); + clk_dm(IMX6UL_CLK_ECSPI1, + imx_clk_gate2(dev, "ecspi1", "ecspi_podf", base + 0x6c, 0)); + clk_dm(IMX6UL_CLK_ECSPI2, + imx_clk_gate2(dev, "ecspi2", "ecspi_podf", base + 0x6c, 2)); + clk_dm(IMX6UL_CLK_ECSPI3, + imx_clk_gate2(dev, "ecspi3", "ecspi_podf", base + 0x6c, 4)); + clk_dm(IMX6UL_CLK_ECSPI4, + imx_clk_gate2(dev, "ecspi4", "ecspi_podf", base + 0x6c, 6)); + + clk_dm(IMX6UL_CLK_USBOH3, + imx_clk_gate2(dev, "usboh3", "ipg", base + 0x80, 0)); + clk_dm(IMX6UL_CLK_USDHC1, + imx_clk_gate2(dev, "usdhc1", "usdhc1_podf", base + 0x80, 2)); + clk_dm(IMX6UL_CLK_USDHC2, + imx_clk_gate2(dev, "usdhc2", "usdhc2_podf", base + 0x80, 4)); + + clk_dm(IMX6UL_CLK_UART1_IPG, + imx_clk_gate2(dev, "uart1_ipg", "ipg", base + 0x7c, 24)); + clk_dm(IMX6UL_CLK_UART1_SERIAL, + imx_clk_gate2(dev, "uart1_serial", "uart_podf", base + 0x7c, 24)); + clk_dm(IMX6UL_CLK_UART2_IPG, + imx_clk_gate2(dev, "uart2_ipg", "ipg", base + 0x68, 28)); + clk_dm(IMX6UL_CLK_UART2_SERIAL, + imx_clk_gate2(dev, "uart2_serial", "uart_podf", base + 0x68, 28)); + clk_dm(IMX6UL_CLK_UART3_IPG, + imx_clk_gate2(dev, "uart3_ipg", "ipg", base + 0x6c, 10)); + clk_dm(IMX6UL_CLK_UART3_SERIAL, + imx_clk_gate2(dev, "uart3_serial", "uart_podf", base + 0x6c, 10)); + clk_dm(IMX6UL_CLK_UART4_IPG, + imx_clk_gate2(dev, "uart4_ipg", "ipg", base + 0x6c, 24)); + clk_dm(IMX6UL_CLK_UART4_SERIAL, + imx_clk_gate2(dev, "uart4_serial", "uart_podf", base + 0x6c, 24)); + clk_dm(IMX6UL_CLK_UART5_IPG, + imx_clk_gate2(dev, "uart5_ipg", "ipg", base + 0x74, 2)); + clk_dm(IMX6UL_CLK_UART5_SERIAL, + imx_clk_gate2(dev, "uart5_serial", "uart_podf", base + 0x74, 2)); + clk_dm(IMX6UL_CLK_UART6_IPG, + imx_clk_gate2(dev, "uart6_ipg", "ipg", base + 0x74, 6)); + clk_dm(IMX6UL_CLK_UART6_SERIAL, + imx_clk_gate2(dev, "uart6_serial", "uart_podf", base + 0x74, 6)); + clk_dm(IMX6UL_CLK_UART7_IPG, + imx_clk_gate2(dev, "uart7_ipg", "ipg", base + 0x7c, 26)); + clk_dm(IMX6UL_CLK_UART7_SERIAL, + imx_clk_gate2(dev, "uart7_serial", "uart_podf", base + 0x7c, 26)); + clk_dm(IMX6UL_CLK_UART8_IPG, + imx_clk_gate2(dev, "uart8_ipg", "ipg", base + 0x80, 14)); + clk_dm(IMX6UL_CLK_UART8_SERIAL, + imx_clk_gate2(dev, "uart8_serial", "uart_podf", base + 0x80, 14)); + +#if CONFIG_IS_ENABLED(NAND_MXS) + clk_dm(IMX6UL_CLK_PER_BCH, + imx_clk_gate2(dev, "per_bch", "bch_podf", base + 0x78, 12)); + clk_dm(IMX6UL_CLK_GPMI_BCH_APB, + imx_clk_gate2(dev, "gpmi_bch_apb", "bch_podf", base + 0x78, 24)); + clk_dm(IMX6UL_CLK_GPMI_BCH, + imx_clk_gate2(dev, "gpmi_bch", "gpmi_podf", base + 0x78, 26)); + clk_dm(IMX6UL_CLK_GPMI_IO, + imx_clk_gate2(dev, "gpmi_io", "enfc_podf", base + 0x78, 28)); + clk_dm(IMX6UL_CLK_GPMI_APB, + imx_clk_gate2(dev, "gpmi_apb", "bch_podf", base + 0x78, 30)); +#endif + clk_dm(IMX6UL_CLK_IPG, + imx_clk_divider(dev, "ipg", "ahb", base + 0x14, 8, 2)); + clk_dm(IMX6UL_CLK_I2C1, + imx_clk_gate2(dev, "i2c1", "perclk", base + 0x70, 6)); + clk_dm(IMX6UL_CLK_I2C2, + imx_clk_gate2(dev, "i2c2", "perclk", base + 0x70, 8)); + clk_dm(IMX6UL_CLK_I2C3, + imx_clk_gate2(dev, "i2c3", "perclk", base + 0x70, 10)); + clk_dm(IMX6UL_CLK_PWM1, + imx_clk_gate2(dev, "pwm1", "perclk", base + 0x78, 16)); + + clk_dm(IMX6UL_CLK_ENET, + imx_clk_gate2(dev, "enet", "ipg", base + 0x6c, 10)); + clk_dm(IMX6UL_CLK_ENET_REF, + imx_clk_fixed_factor(dev, "enet_ref", "pll6_enet", 1, 1)); + + struct clk *clk, *clk1; + + clk_get_by_id(IMX6UL_CLK_ENFC_SEL, &clk); + clk_get_by_id(IMX6UL_CLK_PLL2_PFD2, &clk1); + + clk_set_parent(clk, clk1); + + return 0; +} + +static const struct udevice_id imx6ul_clk_ids[] = { + {.compatible = "fsl,imx6ul-ccm" }, + { }, +}; + +U_BOOT_DRIVER(imx6ul_clk) = { + .name = "clk_imx6ul", + .id = UCLASS_CLK, + .of_match = imx6ul_clk_ids, + .ops = &imx6ul_clk_ops, + .probe = imx6ul_clk_probe, + .flags = DM_FLAG_PRE_RELOC, +}; From patchwork Thu May 29 05:10:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Trimarchi X-Patchwork-Id: 4069 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f72.google.com (mail-ed1-f72.google.com [209.85.208.72]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id AC6D33F0E8 for ; Thu, 29 May 2025 07:10:37 +0200 (CEST) Received: by mail-ed1-f72.google.com with SMTP id 4fb4d7f45d1cf-601f2502663sf80683a12.2 for ; Wed, 28 May 2025 22:10:37 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1748495437; cv=pass; d=google.com; s=arc-20240605; b=cfAFjBaWI+nM/tAxqSLq0y9DKCQJDZXU9YTbO3OAonAh09tDFbpvO6rhvCQkpNKpzt atbEQs/BQapCX/3yNqay5af7UcQRH0IwDfEzaBMFhprkGxi4l2uG9JY1bmgRZ1qpFhBn Ej87gEnk+yXG7hDWcFGdiZcSIrcLTBDhdmjt4iFxppp9+zC3Fjm8jdj8Vb1S/vlUVrT5 oTEwLi9JmaFUw8RT1LcTqWNG50s9+3YH1Z5Pxo1kx68QEuYUnWMkKfVyFBom5vForuQC sXOxKbIRdXQN15uJQgOAP7pVpF3xQkW0cub0nspXB9Mz/W4Iv+EJwVuSLJX+e6oE93WO lQig== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=fQL1HBQbZ0VkpyiboV37jVN+2bG3taVZs7GHmbca3TM=; fh=m8aWm8nOGoCSfTLokSgXeXDZJO6k7Som0ZTaUfFP50E=; b=X1DmSGitjRJyfzfFzFA3ru4rfKYA3jWDr9CSBOvkXWfgylKVSxt/MgKedlNUH6STmB Ia5bHX+2vBVf3k3chPGcEMZqhYdW5x9G3/PrcnXLzyHt0IFCUlgGlGBSO6NioUTTbdw3 c4PGNgk8w2iehN7uqt/b91X5Tn5TWJQ/X4qTfUuf64xhScrQonh0xTbaUWOIARXx8M9U xAPzTfrTlafaSBPxWHdX2NfRrnsEMyL2fmV+jOYrEiebFZDum1CvPbdPzEfvYb7F3wo+ 4R4LIMQbsJB3bVHaif1bOK90gi/42mo00nWwoGAQ0enlQxdu19pFsXBHIb/q8GcSQRyJ solQ==; darn=patchwork.amarulasolutions.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=RsXxqvE2; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1748495437; x=1749100237; darn=patchwork.amarulasolutions.com; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date:message-id:reply-to; bh=fQL1HBQbZ0VkpyiboV37jVN+2bG3taVZs7GHmbca3TM=; b=Vx0i/I6e0JEAFVUFx71SVhC18pk/8jCd8p+5G8Abs2RQhlrtmai1MPbGRvE+wZ3nL4 G+RKT8gbSWISIplel3kKcxcsCZPzD8TBgtCVPQN/rRiZfKJHtj0WW+i7ns69iw7PdD0C WKz4TdilCrxPXVKq1QBv1lhftHKK9hYsvnmlA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748495437; x=1749100237; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :x-beenthere:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=fQL1HBQbZ0VkpyiboV37jVN+2bG3taVZs7GHmbca3TM=; b=gCaX/fX/YkEtlztLWdnN4ynGZWJ2QCQQG0fzAfb5GRN/YpPyDmmMcZRl2W4xo5p04O sQ/z1Q1klujK8RnNFPG8xwmd+Be4hQLwdu8kXXqC2EewqDxEdrk7VPFA0Ux2L9LEKyn8 YAcezisTMEcgA8ggwv8LOUQSn1JatszQJEfl35QjdeJuoYg7eu8HpKJA79C1bFfgUw4g RWGHnH25gr5+TvReMUBOz6Su1Y8dfJv5itqSUcgvaedydzq2OVTZD8bZNu8IJpaoMbzF 4V7+1k/ZAMCAc28rMNZdSDNiKVUG/mUChwOaCZxt8/KFK873PmTxvuEBhRBvMyvMQ9lK emOQ== X-Forwarded-Encrypted: i=2; AJvYcCWR99JxmGv5W2tP0dNfJVphMAuEGfX5t6VRLXgz3gEoZ8yFRPrHr7DhSFBTpTy6bbKDxzf4A4zZTYCpyIOF@patchwork.amarulasolutions.com X-Gm-Message-State: AOJu0YywgfivaciujNqcgo2+oY8mEXpMlBNiqjb/MsegChuU3x7/1YBf jHr42HXoF2NHja/su/LqnuobegGN8xIUXF34/ul4/0sFpEY4yWJlIQMXdxWDNlESB5jAjQ== X-Google-Smtp-Source: AGHT+IHnM+6D1QgV3TXZlVjf9j2LPuAs9QCFuBBqa9xcOk5acS3PEIFYVWfa9M6zRHj7jnZDgw9oSg== X-Received: by 2002:a05:6402:2354:b0:602:3eeb:8aa9 with SMTP id 4fb4d7f45d1cf-602db3b23f8mr6225174a12.11.1748495436999; Wed, 28 May 2025 22:10:36 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com; h=AZMbMZc/SNE1AInd9GIa3zgEjCr8HNtIcYAxfBEqaJPIdz9gjA== Received: by 2002:a05:6402:3490:b0:604:f62b:4107 with SMTP id 4fb4d7f45d1cf-60538d3e9c5ls321325a12.2.-pod-prod-04-eu; Wed, 28 May 2025 22:10:34 -0700 (PDT) X-Received: by 2002:a17:906:dc8a:b0:ad4:d00f:b4ca with SMTP id a640c23a62f3a-ad85b278adcmr1809006466b.50.1748495434280; Wed, 28 May 2025 22:10:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1748495434; cv=none; d=google.com; s=arc-20240605; b=Cbmism800Fl/AR2QKNBl+0CruI+PEuqB6XxFi6xV+AR+fdNdg530K9gQ3Um6w+Di96 BR1x3TWnW6Ibff/Z1H+pTpeVnrQwCwtNV/lxlRPzw/ubQebPRmOB1Id4scAmxqnBFZh9 wk9QQGSLXgo1pfwEhCkNJu8weScAWpc3RPAUerkqjyHjAOWvclylFNnOzlFDf/OQ0Jze rwuIy4Ky/p8kwAXljGl0/hukpFK+mZxDvkvB197n5Z3He0sprKXWrx/h11Xpsu4ksvNs rdKpEocQGXVmZ8WBolSI3mj5IoGgdcPjcMHJiTvQp0CcyA8Q6Up4J5mWU2wrZy26o1/f 1yqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=ddRfdws/1ZICMkV8HKkJsnoMhfx5HcXIctmfu9mzWRc=; fh=PU0Dw4QAw7Q6DjT5ls1inFSBy7arNNXDR6b1GAukzjs=; b=faK36jEBJjwO84hqq72ePdKJbkbhJz5JQI6RBv6863S7EPK1hsoCzKd3D1+WWjviHK /6FHeEDRZgI5zMu0uaVI9/BBBGOcacCOPVEgTlZRYBCgcRTA+TCSSARmfRI99XlyJlqk O0UMK97Y8IUOaoPFuNIAULcAFNI/eDjZlgaTVIuHNdcrd671vAW3hS5hLA6zhLl9zrlb aGnMW0J4tw/O8c9icDeCGJTuAk4IQiMJ2dlGTCbBfTPo5DxhJRBa/ILWxERWW35r12Xy T50qWkZ1B9cINMQn32dfNtwmED7JvZSgAeVfw8bfMqbgNBM3qvniI53YBpzLOY83uvJr FbNA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=RsXxqvE2; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id a640c23a62f3a-ada6ad473a1sor27884666b.12.2025.05.28.22.10.34 for (Google Transport Security); Wed, 28 May 2025 22:10:34 -0700 (PDT) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Gm-Gg: ASbGncsEFFHjoCwM9hCE2ztQwhu3Rk86zs01MRwF4HecYP6jstHTzngKsMiui7o8Gxe mZ5U7Cl/YF4Rh7FzCMhE55m0YbFbf60c0I1B0r5kZZIA9Weu3KV/qt39Ann/2Hg91e5G4zK7V4/ STBn4nbwTKwVMV+cWlrDJaBlXbC33OmeZ8xmneKakBPk3m229faHwwzFL6YUdqQINyKfssxh+kS a/n656xkh7JPhtdD161696YRNDIz/BakExMzILjdhQd11rzCDyadekQbrBEibzCDachHqc5YiKq Yvo5nTL0qFSO2oUCAgfMBxsY3rNH3kl4WOQAhL1DU1HcqquhOP+tbEHdQheQO3P6IN3T+02oFqQ TVTAVn9acZOVk18k= X-Received: by 2002:a17:907:25c7:b0:ad2:1f65:8562 with SMTP id a640c23a62f3a-ad85b083bccmr2009809666b.14.1748495433638; Wed, 28 May 2025 22:10:33 -0700 (PDT) Received: from panicking.amarulasolutions.com ([2001:b07:6467:4426:71fa:236b:ca2b:119e]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ada5d82becbsm70776566b.39.2025.05.28.22.10.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 May 2025 22:10:32 -0700 (PDT) From: Michael Trimarchi To: u-boot@lists.denx.de Cc: linux-amarula@amarulasolutions.com, cniedermaier@dh-electronics.com, Michael Trimarchi , Dario Binacchi , Marek Vasut , Tom Rini Subject: [PATCH v3 2/4] mtd: mxs_nand_dt: Move from clk_get/clk_enable to clk_bulk api Date: Thu, 29 May 2025 07:10:16 +0200 Message-ID: <20250529051024.42340-2-michael@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250529051024.42340-1-michael@amarulasolutions.com> References: <20250529051024.42340-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=RsXxqvE2; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Make simple the clock registration and enable and allow later to add support for other platforms Signed-off-by: Michael Trimarchi --- Changes in v3: - None Changes in v2: - no changes drivers/mtd/nand/raw/mxs_nand_dt.c | 48 ++++-------------------------- 1 file changed, 5 insertions(+), 43 deletions(-) diff --git a/drivers/mtd/nand/raw/mxs_nand_dt.c b/drivers/mtd/nand/raw/mxs_nand_dt.c index 11dbcbbf442..b62474bc5ab 100644 --- a/drivers/mtd/nand/raw/mxs_nand_dt.c +++ b/drivers/mtd/nand/raw/mxs_nand_dt.c @@ -100,9 +100,7 @@ static int mxs_nand_dt_probe(struct udevice *dev) if (IS_ENABLED(CONFIG_CLK) && (IS_ENABLED(CONFIG_IMX8) || IS_ENABLED(CONFIG_IMX8M))) { - /* Assigned clock already set clock */ - struct clk gpmi_clk; - + struct clk_bulk clk_bulk; info->gpmi_clk = devm_clk_get(dev, "gpmi_io"); if (IS_ERR(info->gpmi_clk)) { @@ -111,47 +109,11 @@ static int mxs_nand_dt_probe(struct udevice *dev) return ret; } - ret = clk_enable(info->gpmi_clk); - if (ret < 0) { - debug("Can't enable gpmi io clk: %d\n", ret); - return ret; - } - - if (IS_ENABLED(CONFIG_IMX8)) { - ret = clk_get_by_name(dev, "gpmi_apb", &gpmi_clk); - if (ret < 0) { - debug("Can't get gpmi_apb clk: %d\n", ret); - return ret; - } - - ret = clk_enable(&gpmi_clk); - if (ret < 0) { - debug("Can't enable gpmi_apb clk: %d\n", ret); - return ret; - } - - ret = clk_get_by_name(dev, "gpmi_bch", &gpmi_clk); - if (ret < 0) { - debug("Can't get gpmi_bch clk: %d\n", ret); - return ret; - } - - ret = clk_enable(&gpmi_clk); - if (ret < 0) { - debug("Can't enable gpmi_bch clk: %d\n", ret); - return ret; - } - } - - ret = clk_get_by_name(dev, "gpmi_bch_apb", &gpmi_clk); - if (ret < 0) { - debug("Can't get gpmi_bch_apb clk: %d\n", ret); - return ret; - } - - ret = clk_enable(&gpmi_clk); + ret = clk_get_bulk(dev, &clk_bulk); + if (!ret) + ret = clk_enable_bulk(&clk_bulk); if (ret < 0) { - debug("Can't enable gpmi_bch_apb clk: %d\n", ret); + debug("Can't enable gpmi clks: %d\n", ret); return ret; } } From patchwork Thu May 29 05:10:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Trimarchi X-Patchwork-Id: 4070 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ej1-f71.google.com (mail-ej1-f71.google.com [209.85.218.71]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 7DE1D3F0E8 for ; Thu, 29 May 2025 07:10:39 +0200 (CEST) Received: by mail-ej1-f71.google.com with SMTP id a640c23a62f3a-ad51fa12728sf6537566b.0 for ; Wed, 28 May 2025 22:10:39 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1748495439; cv=pass; d=google.com; s=arc-20240605; b=KbcvHdlePowfNsinbzZ/LvsoJ5kEIsUNew2WmOJtBPrCyyH6VDrRsb0mgSmyOMMV7T SPCPlM7Z2467PkeZhlQGD3PER+Hnnwl5wtUuM37KqgQaj56VZziBGdoUzaLLtw7ZdT9+ OhdSJbA3q5veQMrp9W+mlTZjI3zPSD5PIG8oTaOylakdBTeLB9NQv58wlItsCpDFk7PK 8SLr6zGpdQeB8sazFFBCpW2TVOP9pbop8FbFclOsC0zycfmuUv4ow7WCx9HyA5BxrlC3 frFulDDcNjNHpnBgotYbTofwj7/v7K1+EtvCL88h4M+bLPvcExSJDvmW2DmH91/O6gwZ tQBg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=+OIeDkYfkRPNWcrdleVdj8NshG/ZCpS5j4YD0jL0R+o=; fh=YdtlG2PASGK1UtfMaEXdmpYRbB6ydWpPV8vJqkA0qLo=; b=aGIxPcXZpBh0Ur8dYUdHs3kAX16ImJQZjS5kLJ6YuPhbR/NbBcHEfJZqgyogOXINCI tRxA2ln70eMrTbEzgc7LFCl7TSMqRVyixnlqoAamNwoWp0LCnyT/eLNygvPF6FRVaUeA BKRLtm0cqO7c9GbynUMj5ErBK9OJaGwWqY1ezZhaMvo6WLEWR81tKhRhT1Ke7WjL434Q jppU9hZ1SiVQHgjJeDbKToNJkbl1AQyCGQCdWM3YnaWbF21/cHIv5AWP0nUrAGEkd4qx 0GV6PAfrMuGwb+sOLx5cEtFdKjsXCvYGDnDKmPIX87pOcCG485mHN6M1i9rbyVuP4QP0 GrXQ==; darn=patchwork.amarulasolutions.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=HMDM4heR; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1748495439; x=1749100239; darn=patchwork.amarulasolutions.com; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date:message-id:reply-to; bh=+OIeDkYfkRPNWcrdleVdj8NshG/ZCpS5j4YD0jL0R+o=; b=WknJ5UKZho8bz0ORHDmukHG7WDT0v4Z/AW5nKP9B1BW80ipeVeBXVDHber8v801tF9 3rigue/rUu7bjPL9+F3/EAyZHIcFfTfTIerkr1tGkJzkgBJ0xdcfzlbWiZLrZZGkQNEC XXG1Na8CHvAPho/gq63ydgk683J/oFYnpkjLI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748495439; x=1749100239; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :x-beenthere:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=+OIeDkYfkRPNWcrdleVdj8NshG/ZCpS5j4YD0jL0R+o=; b=KBqSvi9cbY4Hj2H7p6jgTWSMiizuT1EsRqKTpABTEPWbQzSH+HPwK2cv4KVpDZLdE/ I1X3mrqc4hbmEZ+GE2f/SGBHgYz4W+2GmG9+GB+awuS2WWOJtL+ZGbfEG8igSLYlhGRv tV/tSLgoStkuBB1aapviVFC/uMLw44+WHpv345zDgiljQywipYXM70us0yde62zzJnql E2Ud3t1p76PaYUe5hf6D9z93Ks0uWdmFd0mpJO497ASRx7n4UqOnpX5cp8GpYkhz/ApG Lh1n4IxZltMJigkgv2ES+Ql6jQcR9DkaavKIvbn9J1HDUFgSBLgxkFYzKhUhL7yq6WJM FZ8w== X-Forwarded-Encrypted: i=2; AJvYcCVECF7MowbTYdnjOxUJCZnSqHxHuB+E+hIsIB7+h2etySdzE1ruFk4rdqLp88WjPVEW5K2DPgAjtM1SMBos@patchwork.amarulasolutions.com X-Gm-Message-State: AOJu0YwbXiBoJBHqG5TJ/w/40EOXgH2rIM/z9kUPSi+WlFi3Kif4Kws+ z6FhD3IWFsjSqOlWcCHrr7yNu/O5+9QmTEmv4M/HNtu2msS7ZCzQ0YjsqN2r/spwjw5U4A== X-Google-Smtp-Source: AGHT+IGIe03PeF3Z/uSSqwsG0bkwG0tKYQWElVSM/k7FDzg1giWCtNeyrF143x1M1CziPvcJocLzNA== X-Received: by 2002:a05:6402:2547:b0:600:caf:51e5 with SMTP id 4fb4d7f45d1cf-602da4fc972mr6686573a12.8.1748495439031; Wed, 28 May 2025 22:10:39 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com; h=AZMbMZeUoAwBjV1FIrWmnHCGSz5S3HEPPAsJm7p1l70OQ6Z55g== Received: by 2002:a05:6402:3490:b0:604:f62b:4107 with SMTP id 4fb4d7f45d1cf-60538d3e9c5ls321340a12.2.-pod-prod-04-eu; Wed, 28 May 2025 22:10:36 -0700 (PDT) X-Received: by 2002:a17:907:7e91:b0:ad8:96d2:f38 with SMTP id a640c23a62f3a-ad896d21214mr762229066b.18.1748495435977; Wed, 28 May 2025 22:10:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1748495435; cv=none; d=google.com; s=arc-20240605; b=K/raywvKnseq4bBYZPzcUgV/fvxWYpG7ABowRL4dYGo2WpM6OnUhpalqH5g8vjMi5b BIJ8FHxK0zbgNLvxcE8Vn6PxU28uSaCK0egkjR+7P6vxouGCHpLYQ1THizEvqwJvas75 wdLU34HXLy7vXswFsMCrdccHc1SaHzfPZiNKzVMdVwuq5wXjCPm9AtmuTV0M7iLr9OWU 3PnsQh1Uzg2i4+VE4ZPthmJxptSmFcxVIOVdT9begstJ76p6NaILm5DwE6Q0biMHTaT4 Qz5enFbgSSw6Qh91KzuyI/1rCZmXRL7TgB7TTk8ygGEOhEbAt1D4/bViGatXegl5rYTR RFbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=uUnV+hfNFXkFeSGZ3gSZFM5IJaxRAjRgA8p1kH0pIy8=; fh=PU0Dw4QAw7Q6DjT5ls1inFSBy7arNNXDR6b1GAukzjs=; b=dsG22zh3rtfQ6q+MO39nOnnmZx7v2fG7iHuZ7ThjMc02uYcBAaYF0W2tRTmOFPVcDn GhJUriIMzLs7URt+1oJt5HRKLq6cIrsBE7R1zH02bevOlYM25NOJsKFWHGQvEJb1Qd3+ JaVmwgocDlchtbDQ0lQqR2jZKUbkDOSXFzTPQWnkvVQe3qmkfIIL7C5g4/Ctd9J9WI+W I7SGLULiFBE/D5I+XqbSqh5npLcOBadU25jTgjm6gK/5dWvUJic7Qxh5bVekWi7asULD OIWHJb46f541cRhSLFgH2rESotHntEYRWg1PEdVH6qYeYkq6/lLeBh1kJX+5DJg+J51b qpzw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=HMDM4heR; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id a640c23a62f3a-ada5d866872sor36879666b.6.2025.05.28.22.10.35 for (Google Transport Security); Wed, 28 May 2025 22:10:35 -0700 (PDT) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Gm-Gg: ASbGnctQYewIwXEgTJ7XongDesypL3KWWEf5x/Gh6M52tEM4rpCDnnyvuVqi8r6yfZl CycuxN1aVpwSOU0DYZjG9ziKTGGgrGUCjPlgKrtAxTUtzi9rcUhug+qXpWL74sdhyQvDd0jRhbS dJpvQNB5OGKfROIXdRkd2y4aGFAvn6DnPZwpbttcD8Nv65m4zWI4iccHGWqXnnB3qpj2zb5sKPn 2qrtIUUQyqjISGdwvdX5frjpbBLMP1n/R+/CiIdH0cXIc16yFuVVBhYP6NR4jE5UV2SWh3RyJBN 8Z+XR9R3WljtamZBaf+OAJECLikoDNwcOn4AL3mEvdeaHOodYOTQ9zMMv9B6WvG0Uk70p5ZTUuc r/1m0SKD4iJ1N86o= X-Received: by 2002:a17:907:724e:b0:ad8:9c97:c2dc with SMTP id a640c23a62f3a-ad89c97c636mr645663966b.15.1748495435624; Wed, 28 May 2025 22:10:35 -0700 (PDT) Received: from panicking.amarulasolutions.com ([2001:b07:6467:4426:71fa:236b:ca2b:119e]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ada5d82becbsm70776566b.39.2025.05.28.22.10.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 May 2025 22:10:34 -0700 (PDT) From: Michael Trimarchi To: u-boot@lists.denx.de Cc: linux-amarula@amarulasolutions.com, cniedermaier@dh-electronics.com, Michael Trimarchi , Dario Binacchi , Marek Vasut , Tom Rini Subject: [PATCH v3 3/4] mtd: nand: Add support for EDO mode 1-5 to IMX6ULL platform Date: Thu, 29 May 2025 07:10:17 +0200 Message-ID: <20250529051024.42340-3-michael@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250529051024.42340-1-michael@amarulasolutions.com> References: <20250529051024.42340-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=HMDM4heR; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The clock driver allows to boost the NAND performance controller. Make changes to let it use the new clock driver => time nand read ${loadaddr} kernel NAND read: device 0 offset 0x500000, size 0x800000 8388608 bytes read: OK time: 0.488 seconds Signed-off-by: Michael Trimarchi --- Changes in v3: - None Changes in v2: - Adjust commit message and include speed test result - remove not needed { } drivers/mtd/nand/raw/mxs_nand.c | 10 ++++++++++ drivers/mtd/nand/raw/mxs_nand_dt.c | 2 +- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index 80d9307cdd1..ba67466069b 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -1507,8 +1507,18 @@ static void mxs_compute_timings(struct nand_chip *chip, writel(GPMI_CTRL1_CLEAR_MASK, &nand_info->gpmi_regs->hw_gpmi_ctrl1_clr); writel(ctrl1n, &nand_info->gpmi_regs->hw_gpmi_ctrl1_set); + /* Clock dividers do NOT guarantee a clean clock signal on its output + * during the change of the divide factor on i.MX6Q/UL/SX. On i.MX7/8, + * all clock dividers provide these guarantee. + */ + if (IS_ENABLED(CONFIG_MX6ULL)) + clk_disable(nand_info->gpmi_clk); + clk_set_rate(nand_info->gpmi_clk, clk_rate); + if (IS_ENABLED(CONFIG_MX6ULL)) + clk_enable(nand_info->gpmi_clk); + /* Wait 64 clock cycles before using the GPMI after enabling the DLL */ dll_wait_time_us = USEC_PER_SEC / clk_rate * 64; if (!dll_wait_time_us) diff --git a/drivers/mtd/nand/raw/mxs_nand_dt.c b/drivers/mtd/nand/raw/mxs_nand_dt.c index b62474bc5ab..90eefa2558d 100644 --- a/drivers/mtd/nand/raw/mxs_nand_dt.c +++ b/drivers/mtd/nand/raw/mxs_nand_dt.c @@ -99,7 +99,7 @@ static int mxs_nand_dt_probe(struct udevice *dev) info->use_minimum_ecc = dev_read_bool(dev, "fsl,use-minimum-ecc"); if (IS_ENABLED(CONFIG_CLK) && - (IS_ENABLED(CONFIG_IMX8) || IS_ENABLED(CONFIG_IMX8M))) { + (IS_ENABLED(CONFIG_IMX8) || IS_ENABLED(CONFIG_IMX8M) || IS_ENABLED(CONFIG_MX6ULL))) { struct clk_bulk clk_bulk; info->gpmi_clk = devm_clk_get(dev, "gpmi_io"); From patchwork Thu May 29 05:10:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Trimarchi X-Patchwork-Id: 4072 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ej1-f69.google.com (mail-ej1-f69.google.com [209.85.218.69]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 57BC83F0F4 for ; Thu, 29 May 2025 07:10:42 +0200 (CEST) Received: by mail-ej1-f69.google.com with SMTP id a640c23a62f3a-ace942ab877sf42209566b.1 for ; Wed, 28 May 2025 22:10:42 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1748495442; cv=pass; d=google.com; s=arc-20240605; b=hErhk9bzUD7YsNP4JpaQ7+njWU1CDW4EBkBncnO/xAQZ4vaVgnFHSrPWhfEu3MymPm l2idqaXfvBrYPCOM2//alowJlErmqKaWuIIfc13yfv5TFj5EGj+/Py29K0oZoZ7Yv9wK 33pw22d1OtqzR6NZtnSglarmdR+JUTvzf834gsIrUoUbg3RpzwYGtWnFVJVfBoMWuORn GfrkbNgStO0DXk/oiQr5rv8ArAxfg6dZtg7Uaumflt6YpIZjfSmRNch1c6VhDvQ28XSG tqHvV7kCB/DtY7lcFfP0R5YgS3P2Fr2UnnnLZxwiVlLNT4UwVhBiUFlx1KXAGLE0gVUh EbgA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=4CJ0Su+Vx4Dz+FBkJ1wpGiyyFZdwxkpcYfhk4OgfQqg=; fh=skgcjUETlDr+4fu8ppycUi9uGCq/gJZ90ZMtnJaKwxA=; b=WJrr+jbKD2Amr3sQu4wz3mqrKamQyQUnICFCLCfNh/29+OEqGnctFEd3evnbsdi0CA 7p3KyiRcsZ7f74Gv5j2VZhRJo7LigooqncpiGmdKPupzzKZ6srZhuZvvJV8sWZNyGRiT RZpJ+cOBum+bN36H4nKHchcktzZf3v1/Ogj0JTBLfhIQhwKr4PUQil3JqAWd6hRbANlm uTjqC9pH6hpPjPl71ljPEHkMLyKAQMKfuPSJu5Y1oKF0QzCKQcC21F3US/1nDFrEVmmD aOmfiVR+cWKazvn4ijy0iCdPjQlR7k+m/B3GWCjDQB/p6NB9j0TB0HgS3YmPY6Vp0fQ2 0QQg==; darn=patchwork.amarulasolutions.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=FVJL3O+z; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1748495442; x=1749100242; darn=patchwork.amarulasolutions.com; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date:message-id:reply-to; bh=4CJ0Su+Vx4Dz+FBkJ1wpGiyyFZdwxkpcYfhk4OgfQqg=; b=joVYJW8oLu/ckZ1llVe43EcCUYzCdy0C9ZAt5F/bTzfr4NxACnYZSXuZ29fGWZwW1c kVtusfbLGBIKXVWJmn48MQN4V8QpR0gc37rtDGJIi1rbW0TVWS6gD0WOB1eQLoMyVwDn Lrcjd8Y5d4ov0M3EXh+RewZ484mI9JphATxTw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748495442; x=1749100242; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :x-beenthere:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=4CJ0Su+Vx4Dz+FBkJ1wpGiyyFZdwxkpcYfhk4OgfQqg=; b=EKIqe0mmWqLEdYRef4CYxKK9HStQYc/o2F5bmPT+rT5zzE0Xd8gyGESprO0nVGd7+O lOoJ1l/bQ5hcnBimPVEEs3cuSE5EcWJchPUc9qPWb3vzFaA5E1VB04KC8OdEiDneSLCn lHuw+4AtFocJN8CzmvFrTS4vknfdkSPTg5Z3oxbFoArJT+j68owV2axpNkMzjd7J23O9 BmncH3C+ZE4Br1N//5BxycuF1umbJApXTerF8Qw0SLlhQ1Mk8RQXM81gfuUIfOZC0y2r omUUupnHtkGjzCfnR8Xr7IRip4RHaIn1XZApjy8cmYsbkta6xQQ+oLHbY9vFpOgJ0XPt QSZQ== X-Forwarded-Encrypted: i=2; AJvYcCULDS7RoVNhhqoBs+EbZgLWI+brBkjSCS4FaizSw+sCOjIqUXmM1A71+2E5sfOg+qwvg/WydUQXN9xHagds@patchwork.amarulasolutions.com X-Gm-Message-State: AOJu0YxT/anRvaNsreLxRrzPYHT6NM6dyICuDaROumbZngK7OYHyBEWl ETKkIs9nis75N6I28AMWUkrzbG54o3GKwpM6obj7eaLE0vqw4M3e4+qX9vA+tgA9cB+4bQ== X-Google-Smtp-Source: AGHT+IHYlx5l1Ipr6R+zXSmOHRddCNDlneAbycyisTSHXDRfqcw0MBye/ZXXaN329klr5x5WBLg4DQ== X-Received: by 2002:a05:6402:3509:b0:5fb:f708:2641 with SMTP id 4fb4d7f45d1cf-602da5f83ecmr18432670a12.27.1748495441886; Wed, 28 May 2025 22:10:41 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com; h=AZMbMZd6c0wuwdsftb13bk2uLXLH3iCji5NJJ1EmR2UAvRFfVg== Received: by 2002:a05:6402:13c5:b0:601:956f:a0cf with SMTP id 4fb4d7f45d1cf-60538d2c221ls393061a12.1.-pod-prod-04-eu; Wed, 28 May 2025 22:10:39 -0700 (PDT) X-Received: by 2002:a17:907:7288:b0:ad8:9e80:6ba3 with SMTP id a640c23a62f3a-ad89e807c46mr460953166b.7.1748495439199; Wed, 28 May 2025 22:10:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1748495439; cv=none; d=google.com; s=arc-20240605; b=QR7oN7DWC1A9Isdt9s5gJma+uNu6h2vvX+FKFh2hUUFHq1/x/A+X3oKt4AJzsp+Uut wCx8rA0jDtrpyT6Twsm9JcPo6H0lj9yFprB4uRDR8ej1Z6j0msT7pA77yEbUSOc0Itjc bQXA1atAuAw9YfkHrEztHTfEtbQhs9j+dCLPYfP6E7RIRAXlJ+KZV2+gHj14+VZ41akm +zx+O7avYw1Riq2HcDA/7bTw6aBf88kDVbTixZvQzoRxI5kitftj9/fv1THYDcldG2oR nu8kAwbV3A5CdIib1RfxhTszejiAtLy1TC1ySHrNaDk94USREk75+tUHsKd+boyeobUC GvqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=sYhMbj1+fZ01f+uZlfBq4NpnPga0rE7deIF6dDtULmU=; fh=im1cjflQyNOR++W70RBldTD4Y2v8izBE9P/D3MhOB3U=; b=BPoRcx73EuXk3v2arKq1ZIV9wgrYrzdPix0Vsb8T015GOMTup1z+APYQifvZdTSx8+ k1gpb9VOZsGMwYmy0s3//GjYQTJM0fcbMr3wpvhIBLIDF4qMiFbtGRs2aszi+2z28LBH DzigbolzzsTLMwuu/B8VaScpUTTvQPJS3nFk3eOpwBiic1WeF7W23iG96JEuQ6H9i3vp P+s+t9hdrvNa4oUMukb8T0+sr5f549k5n5ntJ03rSE/TljrRhU4vm4ChtyPGMLR+HRy1 VOBgUckP5c3x3I/f6rsP/5+p1EcMggFnXcCxEhsbMIZRdBDME6778c4fOqRng1rgOPy3 PYzw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=FVJL3O+z; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id a640c23a62f3a-ada4b688352sor33717666b.0.2025.05.28.22.10.39 for (Google Transport Security); Wed, 28 May 2025 22:10:39 -0700 (PDT) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Gm-Gg: ASbGncvNOKgviD6y9CJ0xlo564nkUH0rURVAL3Z2hzjgy7ltUECIAPeQT7ZwTbj2ahf XQ/QnQdpu2oLQU+xJ4dx9eRMAkxf7yTAScPVRYncXJscSX7FzH3xu63URk+y4nXiUF/rOEv064d WkOtkxEApa5Yj9en+OhoD2hYi4pfn5jEVmy0gHqsx6GgpEqPIRJP7zwL8PvE78zKIidXJpQ7Grz mL4uZOAIM4Jxy8+NmSvHE2OVhZOsDOMElipq2prnE7Fzsgq6fI87DISS9AH0Nsw70UJRXSfl0AQ PWj086KZrBIOiL1mWJxnuRhYgadUXHpHlt2oMPcCdG0qVObM6ltzCGsoNjV8EnejeBeWlgu7js6 4Qbjr/Rg1VGqyh1k= X-Received: by 2002:a17:907:9488:b0:ad8:a935:b8f6 with SMTP id a640c23a62f3a-ad8a935c964mr268716166b.0.1748495438786; Wed, 28 May 2025 22:10:38 -0700 (PDT) Received: from panicking.amarulasolutions.com ([2001:b07:6467:4426:71fa:236b:ca2b:119e]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ada5d82becbsm70776566b.39.2025.05.28.22.10.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 May 2025 22:10:38 -0700 (PDT) From: Michael Trimarchi To: u-boot@lists.denx.de Cc: linux-amarula@amarulasolutions.com, cniedermaier@dh-electronics.com, Michael Trimarchi , Ilias Apalodimas , Jerome Forissier , Marek Vasut , Patrick Barsanti , Tom Rini Subject: [PATCH v3 4/4] configs/imx6ulz_smm_m2_defconfig: Enable clock framework Date: Thu, 29 May 2025 07:10:18 +0200 Message-ID: <20250529051024.42340-4-michael@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250529051024.42340-1-michael@amarulasolutions.com> References: <20250529051024.42340-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=FVJL3O+z; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Enable the clock framework on the m2 platform. This helps to increase the NAND controller performance. Signed-off-by: Michael Trimarchi --- Changes in v3: - None Changes in v2: - Ajust commit message - drop CONFIG_DM_MTD selected already by MXS_NAND_DT configs/imx6ulz_smm_m2_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/imx6ulz_smm_m2_defconfig b/configs/imx6ulz_smm_m2_defconfig index 436bfb78cc2..6e425d6e52d 100644 --- a/configs/imx6ulz_smm_m2_defconfig +++ b/configs/imx6ulz_smm_m2_defconfig @@ -43,6 +43,8 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_BOUNCE_BUFFER=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX6UL=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x82000000 CONFIG_FASTBOOT_FLASH=y