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[188.217.53.154]) by smtp.gmail.com with ESMTPSA id j11-20020adfb30b000000b0020c5253d8fdsm300457wrd.73.2022.05.19.11.50.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 May 2022 11:50:59 -0700 (PDT) From: Tommaso Merciai <tommaso.merciai@amarulasolutions.com> To: Cc: tommaso.merciai@amarulasolutions.com, michael@amarulasolutions.com, alberto.bianchi@amarulasolutions.com, linux-amarula@amarulasolutions.com, linuxfancy@googlegroups.com, Andrew Lunn <andrew@lunn.ch>, Heiner Kallweit <hkallweit1@gmail.com>, Russell King <linux@armlinux.org.uk>, "David S. Miller" <davem@davemloft.net>, Eric Dumazet <edumazet@google.com>, Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2] net: phy: DP83822: enable rgmii mode if phy_interface_is_rgmii Date: Thu, 19 May 2022 20:50:56 +0200 Message-Id: <20220519185057.1657115-1-tommaso.merciai@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Original-Sender: tommaso.merciai@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=TAeL8EKa; spf=pass (google.com: domain of tommaso.merciai@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=tommaso.merciai@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: <linux-amarula.amarulasolutions.com> X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: <https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/post>, <mailto:linux-amarula@amarulasolutions.com> List-Help: <https://support.google.com/a/amarulasolutions.com/bin/topic.py?topic=25838>, <mailto:linux-amarula+help@amarulasolutions.com> List-Archive: <https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/> List-Unsubscribe: <mailto:googlegroups-manage+476853432473+unsubscribe@googlegroups.com>, <https://groups.google.com/a/amarulasolutions.com/group/linux-amarula/subscribe> |
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[v2] net: phy: DP83822: enable rgmii mode if phy_interface_is_rgmii
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Commit Message
Tommaso Merciai
May 19, 2022, 6:50 p.m. UTC
RGMII mode can be enable from dp83822 straps, and also writing bit 9 of register 0x17 - RMII and Status Register (RCSR). When phy_interface_is_rgmii rgmii mode must be enabled, same for contrary, this prevents malconfigurations of hw straps References: - https://www.ti.com/lit/gpn/dp83822i p66 Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com> Co-developed-by: Michael Trimarchi <michael@amarulasolutions.com> Suggested-by: Alberto Bianchi <alberto.bianchi@amarulasolutions.com> Tested-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com> --- Changes since v1: - Improve commit msg - Add definition of bit 9 reg rcsr (rgmii mode en) - Handle case: phy_interface_is_rgmii is false drivers/net/phy/dp83822.c | 9 +++++++++ 1 file changed, 9 insertions(+)
Comments
Hi Tommaso On Thu, May 19, 2022 at 8:50 PM Tommaso Merciai <tommaso.merciai@amarulasolutions.com> wrote: > > RGMII mode can be enable from dp83822 straps, and also writing bit 9 > of register 0x17 - RMII and Status Register (RCSR). > When phy_interface_is_rgmii rgmii mode must be enabled, same for > contrary, this prevents malconfigurations of hw straps > > References: > - https://www.ti.com/lit/gpn/dp83822i p66 > > Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com> > Co-developed-by: Michael Trimarchi <michael@amarulasolutions.com> > Suggested-by: Alberto Bianchi <alberto.bianchi@amarulasolutions.com> > Tested-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com> > --- > Changes since v1: > - Improve commit msg > - Add definition of bit 9 reg rcsr (rgmii mode en) > - Handle case: phy_interface_is_rgmii is false > > drivers/net/phy/dp83822.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c > index ce17b2af3218..7cb9d084707b 100644 > --- a/drivers/net/phy/dp83822.c > +++ b/drivers/net/phy/dp83822.c > @@ -94,6 +94,9 @@ > #define DP83822_WOL_INDICATION_SEL BIT(8) > #define DP83822_WOL_CLR_INDICATION BIT(11) > > +/* RCSR bits */ > +#define DP83822_RGMII_MODE_EN BIT(9) > + > /* RSCR bits */ > #define DP83822_RX_CLK_SHIFT BIT(12) > #define DP83822_TX_CLK_SHIFT BIT(11) BIT(9) should go here #define DP83822_RGMII_MODE_EN BIT(9) #define DP83822_RX_CLK_SHIFT BIT(12) #define DP83822_TX_CLK_SHIFT BIT(11) You duplicate the comments up. > @@ -408,6 +411,12 @@ static int dp83822_config_init(struct phy_device *phydev) > if (err) > return err; > } > + > + phy_set_bits_mmd(phydev, DP83822_DEVADDR, > + MII_DP83822_RCSR, DP83822_RGMII_MODE_EN); > + } else { > + phy_clear_bits_mmd(phydev, DP83822_DEVADDR, > + MII_DP83822_RCSR, DP83822_RGMII_MODE_EN); > } > > if (dp83822->fx_enabled) { > -- > 2.25.1 > Michael
On Thu, May 19, 2022 at 08:50:56PM +0200, Tommaso Merciai wrote: > RGMII mode can be enable from dp83822 straps, and also writing bit 9 > of register 0x17 - RMII and Status Register (RCSR). > When phy_interface_is_rgmii rgmii mode must be enabled, same for > contrary, this prevents malconfigurations of hw straps > > References: > - https://www.ti.com/lit/gpn/dp83822i p66 > > Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com> > Co-developed-by: Michael Trimarchi <michael@amarulasolutions.com> > Suggested-by: Alberto Bianchi <alberto.bianchi@amarulasolutions.com> > Tested-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com> > --- > Changes since v1: > - Improve commit msg > - Add definition of bit 9 reg rcsr (rgmii mode en) > - Handle case: phy_interface_is_rgmii is false Please don't post a new version for at least 24 hours. Give people time to review the code and make comments. Andrew
diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c index ce17b2af3218..7cb9d084707b 100644 --- a/drivers/net/phy/dp83822.c +++ b/drivers/net/phy/dp83822.c @@ -94,6 +94,9 @@ #define DP83822_WOL_INDICATION_SEL BIT(8) #define DP83822_WOL_CLR_INDICATION BIT(11) +/* RCSR bits */ +#define DP83822_RGMII_MODE_EN BIT(9) + /* RSCR bits */ #define DP83822_RX_CLK_SHIFT BIT(12) #define DP83822_TX_CLK_SHIFT BIT(11) @@ -408,6 +411,12 @@ static int dp83822_config_init(struct phy_device *phydev) if (err) return err; } + + phy_set_bits_mmd(phydev, DP83822_DEVADDR, + MII_DP83822_RCSR, DP83822_RGMII_MODE_EN); + } else { + phy_clear_bits_mmd(phydev, DP83822_DEVADDR, + MII_DP83822_RCSR, DP83822_RGMII_MODE_EN); } if (dp83822->fx_enabled) {