| Message ID | 20250424062154.2999219-12-dario.binacchi@amarulasolutions.com |
|---|---|
| State | New |
| Headers | show |
| Series |
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| Related | show |
On Thu, Apr 24, 2025 at 08:21:41AM +0200, Dario Binacchi wrote: > Support NXP i.MX8M anatop PLL module which generates PLLs to CCM root. > By doing so, we also simplify the CCM driver code. The changes are > backward compatible. This patch, which has been in -next for the past few days as 3cbc38cf42ca42d2, breaks boot on i.MX8MP platforms (I have the EVK and Verdin). We die with: [ 1.439320] i.MX clk 1: register failed with -2 [ 1.441014] i.MX clk 2: register failed with -2 [ 1.445610] imx8mm-anatop 30360000.clock-controller: NXP i.MX8MM anatop clock driver probed [ 1.455068] Unable to handle kernel paging request at virtual address fffffffffffffffe ... [ 1.634650] Call trace: [ 1.637102] __clk_get_hw+0x4/0x18 (P) [ 1.640862] imx8mp_clocks_probe+0xdc/0x2f50 [ 1.645152] platform_probe+0x68/0xc4 [ 1.648827] really_probe+0xbc/0x298 [ 1.652413] __driver_probe_device+0x78/0x12c Full log at: https://lava.sirena.org.uk/scheduler/job/1371067 bisect data (not the actual bisetion as it'd run previously but I didn't get a chance to check the results, has all the commits and their test results though): # bad: [f48887a98b78880b7711aca311fbbbcaad6c4e3b] Add linux-next specific files for 20250508 # good: [4ea0e68600c61f7d18b218d9af98c5c3bd23e856] Merge branch 'for-linux-next-fixes' of https://gitlab.freedesktop.org/drm/misc/kernel.git # good: [d75d38dc460452cc8bbca483dee65839e11c71fe] ASoC: tas2781: Add a debugfs node for acoustic tuning # good: [5bf5bdfd007e07f2ec5b3e07aa02616f4eebef67] ASoC: codec: cs42l52: Convert to GPIO descriptors # good: [7b400c9ab879a86aa4b9bf5d9fdd3df558eed9b5] ASoC: SOF: add disable_function_topology module parameter # good: [9f7cd1bcb6363368abc954ff4e727b579813c697] spi: nxp-fspi: use devm instead of remove for driver detach # good: [ad6d689e776478113aeef7bfb0e4222b1ff2a986] ASoC: amd: sof_amd_sdw: add logic to get cpu_pin_id for ACP7.0/ACP7.1 platforms # good: [406fbc4d0fb34c16718551bb8f4c776710f63b55] ASoC: cs35l56: Read Silicon ID from DIE_STS registers for CS35L63 # good: [a71b261c19a455f7f8e560b4ddfac44d3150ae39] ASoC: SOF: imx8m: Use reset controller API to control the DSP # good: [6c965d39af98a8b79668898b3a2af40d11179ff4] ASoC: Intel: sof_sdw: Avoid NULL check fail when re-probing # good: [222a87f6b94f6f177e896d6fcdc7881480344e34] spi: cadence-quadspi: Assume device could match via platform # good: [14a3fd030c033453d436233f4c422b4903786ed3] ASoC: intel: atom: Return -ENOMEM if pcim_iomap() fails # good: [17e3c1a272d97e49b4f3fbfe1f1b889e120d2be8] clk: imx: add hw API imx_anatop_get_clk_hw # good: [e68074c63fded9468c513f65734ffb4c80dc2a6d] ASoC: SOF: amd: add build support for soundwire # good: [233d740e3a819829ccd6d21319015a94349d64eb] spi: loopback-test: Simplify strange loopback value check # good: [63e5784d640a5c61a828d33bee24fea4244e479c] Merge branch 'ti-k3-dts-next' into ti-next # good: [2dbe74c63cb73829be0aab0d0e7e68b87071b5fa] spi: dt-bindings: spi-qpic-snand: Add IPQ5018 compatible # good: [f1471bc435afa31c8c0c58551922830dc8f4b06b] regulator: tps65219: Add TI TPS65214 Regulator Support # good: [2056d7a7df5d9a08144671afccb6970ccd595b89] ASoC: fsl_rpmsg: Allocate a smaller buffer size for capture stream # good: [fed0805ffd76161ed8c056ea30b36550eda8e106] ASoC: mediatek: mt8195: use snd_soc_dlc_is_dummy() # good: [178c169a30b011971cbbf9c79032b5898b1b07de] ASoC: codec: twl4030: Convert to GPIO descriptors # good: [d20df86b056b95845f6ed52da1010059202a0c23] ASoC: Intel: avs: Fix kcalloc() sizes # good: [e6702c44c2adb28b62f81de498e9b1e4562ce660] spi: axi-spi-engine: omit SYNC from offload instructions # good: [94602d84163c127ec2374fba0fcb6587a07785ce] ASoC: wm_adsp: Don't use no_free_ptr() when passing to PTR_ERR() # good: [d30e845b0ae63400738709ca624a4a7bb69c4ba2] regcache: Use sort()'s default swap() implementation # good: [64c05a1d66193b3a40ad1f29c3d8ba5483e4e0dc] spi: spi-qpic-snand: remove unused 'wlen' member of 'struct qpic_spi_nand' # good: [c61caec22820f24bb155929f5cee8c1ccfe92f77] ASoC: renesas: add MSIOF sound support # good: [0787a08ae785366b9473905fc8bf23f165a08b8d] ASoC: starfive: Use max() to simplify code in jh7110_tdm_syncdiv() # good: [18197e98353d931fc7bb2bb9ec671d3aa407831d] spi: meson-spicc: add DMA support # good: [f198b6b256aabe6d136401505e974ef2eb2df4af] ASoC: codec: tpa6130a2: Convert to GPIO descriptors # good: [cce73cf7cc56a04cf0dd1e1f93b4002c00751ebe] MAINTAINERS: ASoC: Simplify references to Cirrus Logic include files # good: [e358e012a69a3d553803cbe62d9f6eeea57726fc] ASoC: codecs: wcd938x: drop unnecessary mux flag assignment # good: [cf0668184d1d2f9ad3f98dd5bbe0ed4d9d090eaa] spi: sh-msiof: ignore driver probing if it was MSIOF Sound # good: [c283fcdc4e2b89678c171691fd26f576139fc256] spi: tegra210-quad: Update dummy sequence configuration # good: [b50a1e1f3c4630f729629a787d891d7b4348007f] spi: intel: Improve resource mapping # good: [5410aa3aa7f7dfcbdfcf94034595765d7e69ead3] regulator: pf9453: convert to use maple tree register cache # good: [6d7ee6de75010ed5d70f1c496070c4a7cd1968b5] ASoC: adau7118: Allow dsp_a mode # good: [e8ac7336dd62f0443a675ed80b17f0f0e6846e20] regulator: max20086: Change enable gpio to optional # good: [0c9f82446123635cfbb8ceeca074f2dce6a0ccae] ASoC: dt-bindings: fsl,mqs: Document audio graph port # good: [cc78d1eaabad3caf3c425c83037cd8ba1c9f2bc6] ASoC: rockchip: add Serial Audio Interface (SAI) driver # good: [9ef24511d29f0300fc7e9d4a5ea38d78e9eef73e] ASoC: wm8998: Add Kconfig prompt # good: [296e8d289bdd7eb0d832683ebd3e847fbb4c1b12] spi: offload: remove unnecessary check on trigger->ops # good: [4cc9cf2f437ccf6915100c2f38f63cfb1abad6f9] spi: dt-bindings: Fix description mentioning a removed property # good: [e30b7a75666b3f444abfabed6a144642fa9994d8] spi: dw: Use spi_bpw_to_bytes() helper # good: [5b974f53424d16165b606e2e2f9208d450a5723c] ASoC: dt-bindings: mt8195: add missing audio routing and link-name # good: [d981e7b3f25fbabca9cdd02aa2a8f16d6f235fc2] spi: pci1xxxx: Use non-hybrid PCI devres API # good: [4308487b29f98785ef50dd82fdfca382134b33e7] firmware: cs_dsp: Add some sanity-checking to test harness # good: [7ed50dc550b0a3bad82f675aaefd8cd00362672d] ASoC: cs48l32: Fix spelling mistake "exceeeds" -> "exceeds" # good: [51f04358d8c887c5d117440335c7f94285a403f2] ASoC: cs-amp-lib-test: Use flex_array_size() # good: [e2bcbf99d045f6ae3826e39d1ed25978de17cbfe] ASoC: cs48l32: Add driver for Cirrus Logic CS48L32 audio DSP # good: [fcdf212fd9b36c299d90229e9546c077db2215ce] ASoC: cs-amp-lib: Annotate struct cirrus_amp_efi_data with __counted_by() # good: [2b4ce994afca0690ab79b7860045e6883e8706db] ASoC: simple-card-utils: fixup dlc->xxx handling for error case # good: [46e7ea05bf5d9fe4d05e173c824ae173c956cb5f] ASoC: cs-amp-lib: Replace offsetof() with struct_size() # good: [4f8ef33dd44a3d1136d3934609b8a43e62aaaa0d] ASoC: soc_sdw_utils: skip the endpoint that doesn't present # good: [7762fdab23100514e5cb612331c96bd65126ada5] regulator: adp5055: Remove unneeded semicolon # good: [38c2585c7439cc678ae105dd826f10321db29552] ASoC: codecs: Add support for Richtek rt9123p # good: [8d2e914482311f7746fe7b0e520bd42794d6aed8] ALSA: hda: cirrus_scodec_test: use new GPIO line value setter callbacks # good: [436a3cc8afbf34bb68166c2c5c19ca5113c0c756] ASoC: ac97: Add DT support # good: [186dfc85f9a824e3f8383322747ca75e988486e9] ASoC: tas2764: expose die temp to hwmon # good: [279b418f477fd6c1c21b1cf212837622c774f15f] spi: fsl-qspi: Optimize fsl_qspi struct # good: [e78e7856d233010e6afef62f15567a8e7777c8bc] ASoC: test-component: add set_tdm_slot stub implementation # good: [7a978d8fcf57b283cb8c88dd4c9431502bd36ea8] spi: amd: add CONFIG_PCI dependency # good: [28cce24d6596a3d8a34689031f2a8a5ac918cde5] regulator: adp5055: remove duplicate device table # good: [b5d057a86e2086af0b1e6d0ca8b306be1c73a627] ASoC: wm_adsp: Use vmemdup_user() instead of open-coding # good: [3f7b48efb79d91883d98dd7e33dc2a0abfa9f923] spi: fsl-qspi: Simplify probe error handling using managed API # good: [aaf6223ea2a1ff9316a81bf851fd5a0e82635b60] regulator: don't compare raw GPIO descriptor pointers # good: [e686365c0411275474527c2055ac133f2eb47526] spi: spi_amd: Fix an IS_ERR() vs NULL check in probe # good: [147b2a96f24e0cfcc476378f9356b30662045c7e] regulator: adp5055: Add driver for adp5055 # good: [265daffe788aa1cc5925d0afcde4fe6e99c66638] gpio: provide gpiod_is_equal() # good: [5e21900ef64244fadeddc9015e8b8307d116764a] spi: xcomm: use new GPIO line value setter callbacks # good: [936df52c29b0d422665c5e84b0cffae61611411b] regulator: rpi-panel-attiny: use new GPIO line value setter callbacks # good: [4c035fab9f42071c4024495afb2cec1409280eed] ASoC: tas2781-i2c: Remove unnecessary NULL check before release_firmware() # good: [8d18e67abbdf380cd1cfd2c313aac625092d7777] ASoC: Intel: avs: Support 16 TDMs in dynamic assignment # good: [93fa44f84704dfedc4fe06b89bebc8cfaa5f525b] ASoC: Intel: avs: boards: Change ssm4567 card name # good: [ce2eadc6f99263dd200e52f692dc7a22698c99f3] regulator: s5m8767: Convert to GPIO descriptors # good: [b3d9e96c96b0076a11aa1001d55b3dc189b8cd1c] regulator: pf9453: Improve documentation for pf9453_regulator_set_ramp_delay_regmap # good: [387ddbc7d474967589de15043b47a441f95a50f2] ALSA: hda: Select avs-driver by default on FCL # good: [4e310626eb4df52a31a142c1360fead0fcbd3793] gpiolib: of: Add polarity quirk for s5m8767 # good: [b644c2776652671256edcd7a8e71161e212b59ac] spi: spi_amd: Add PCI-based driver for AMD HID2 SPI controller # good: [69e3433fa5e24edc94e94b4f34e3dbb754bdedbf] spi: spi-stm32-ospi: Make "resets" a required property # good: [ea61f39b38bdbb7c77ba2c70e130acdb808c8d68] ASoC: sta32x: Remove unnecessary NULL check before clk_disable_unprepare() # good: [eec611d26f84800852a9badbeafa76db3cdc9118] ASoC: codecs: wcd938x: add mux control support for hp audio mux # good: [d5099bc1b56417733f4cccf10c61ee74dadd5562] ASoC: codec: wcd9335: Convert to GPIO descriptors # good: [1d9119794c10023ebd7c901aa9aa2c74eb833177] ASoC: fsl_sai: separate set_tdm_slot() for tx and rx git bisect start 'f48887a98b78880b7711aca311fbbbcaad6c4e3b' '4ea0e68600c61f7d18b218d9af98c5c3bd23e856' 'd75d38dc460452cc8bbca483dee65839e11c71fe' '5bf5bdfd007e07f2ec5b3e07aa02616f4eebef67' '7b400c9ab879a86aa4b9bf5d9fdd3df558eed9b5' '9f7cd1bcb6363368abc954ff4e727b579813c697' 'ad6d689e776478113aeef7bfb0e4222b1ff2a986' '406fbc4d0fb34c16718551bb8f4c776710f63b55' 'a71b261c19a455f7f8e560b4ddfac44d3150ae39' '6c965d39af98a8b79668898b3a2af40d11179ff4' '222a87f6b94f6f177e896d6fcdc7881480344e34' '14a3fd030c033453d436233f4c422b4903786ed3' '17e3c1a272d97e49b4f3fbfe1f1b889e120d2be8' 'e68074c63fded9468c513f65734ffb4c80dc2a6d' '233d740e3a819829ccd6d21319015a94349d64eb' '63e5784d640a5c61a828d33bee24fea4244e479c' '2dbe74c63cb73829be0aab0d0e7e68b87071b5fa' 'f1471bc435afa31c8c0c58551922830dc8f4b06b' '2056d7a7df5d9a08144671afccb6970ccd595b89' 'fed0805ffd76161ed8c056ea30b36550eda8e106' '178c169a30b011971cbbf9c79032b5898b1b07de' 'd20df86b056b95845f6ed52da1010059202a0c23' 'e6702c44c2adb28b62f81de498e9b1e4562ce660' '94602d84163c127ec2374fba0fcb6587a07785ce' 'd30e845b0ae63400738709ca624a4a7bb69c4ba2' '64c05a1d66193b3a40ad1f29c3d8ba5483e4e0dc' 'c61caec22820f24bb155929f5cee8c1ccfe92f77' '0787a08ae785366b9473905fc8bf23f165a08b8d' '18197e98353d931fc7bb2bb9ec671d3aa407831d' 'f198b6b256aabe6d136401505e974ef2eb2df4af' 'cce73cf7cc56a04cf0dd1e1f93b4002c00751ebe' 'e358e012a69a3d553803cbe62d9f6eeea57726fc' 'cf0668184d1d2f9ad3f98dd5bbe0ed4d9d090eaa' 'c283fcdc4e2b89678c171691fd26f576139fc256' 'b50a1e1f3c4630f729629a787d891d7b4348007f' '5410aa3aa7f7dfcbdfcf94034595765d7e69ead3' '6d7ee6de75010ed5d70f1c496070c4a7cd1968b5' 'e8ac7336dd62f0443a675ed80b17f0f0e6846e20' '0c9f82446123635cfbb8ceeca074f2dce6a0ccae' 'cc78d1eaabad3caf3c425c83037cd8ba1c9f2bc6' '9ef24511d29f0300fc7e9d4a5ea38d78e9eef73e' '296e8d289bdd7eb0d832683ebd3e847fbb4c1b12' '4cc9cf2f437ccf6915100c2f38f63cfb1abad6f9' 'e30b7a75666b3f444abfabed6a144642fa9994d8' '5b974f53424d16165b606e2e2f9208d450a5723c' 'd981e7b3f25fbabca9cdd02aa2a8f16d6f235fc2' '4308487b29f98785ef50dd82fdfca382134b33e7' '7ed50dc550b0a3bad82f675aaefd8cd00362672d' '51f04358d8c887c5d117440335c7f94285a403f2' 'e2bcbf99d045f6ae3826e39d1ed25978de17cbfe' 'fcdf212fd9b36c299d90229e9546c077db2215ce' '2b4ce994afca0690ab79b7860045e6883e8706db' '46e7ea05bf5d9fe4d05e173c824ae173c956cb5f' '4f8ef33dd44a3d1136d3934609b8a43e62aaaa0d' '7762fdab23100514e5cb612331c96bd65126ada5' '38c2585c7439cc678ae105dd826f10321db29552' '8d2e914482311f7746fe7b0e520bd42794d6aed8' '436a3cc8afbf34bb68166c2c5c19ca5113c0c756' '186dfc85f9a824e3f8383322747ca75e988486e9' '279b418f477fd6c1c21b1cf212837622c774f15f' 'e78e7856d233010e6afef62f15567a8e7777c8bc' '7a978d8fcf57b283cb8c88dd4c9431502bd36ea8' '28cce24d6596a3d8a34689031f2a8a5ac918cde5' 'b5d057a86e2086af0b1e6d0ca8b306be1c73a627' '3f7b48efb79d91883d98dd7e33dc2a0abfa9f923' 'aaf6223ea2a1ff9316a81bf851fd5a0e82635b60' 'e686365c0411275474527c2055ac133f2eb47526' '147b2a96f24e0cfcc476378f9356b30662045c7e' '265daffe788aa1cc5925d0afcde4fe6e99c66638' '5e21900ef64244fadeddc9015e8b8307d116764a' '936df52c29b0d422665c5e84b0cffae61611411b' '4c035fab9f42071c4024495afb2cec1409280eed' '8d18e67abbdf380cd1cfd2c313aac625092d7777' '93fa44f84704dfedc4fe06b89bebc8cfaa5f525b' 'ce2eadc6f99263dd200e52f692dc7a22698c99f3' 'b3d9e96c96b0076a11aa1001d55b3dc189b8cd1c' '387ddbc7d474967589de15043b47a441f95a50f2' '4e310626eb4df52a31a142c1360fead0fcbd3793' 'b644c2776652671256edcd7a8e71161e212b59ac' '69e3433fa5e24edc94e94b4f34e3dbb754bdedbf' 'ea61f39b38bdbb7c77ba2c70e130acdb808c8d68' 'eec611d26f84800852a9badbeafa76db3cdc9118' 'd5099bc1b56417733f4cccf10c61ee74dadd5562' '1d9119794c10023ebd7c901aa9aa2c74eb833177' # test job: [d75d38dc460452cc8bbca483dee65839e11c71fe] https://lava.sirena.org.uk/scheduler/job/1365900 # test job: [5bf5bdfd007e07f2ec5b3e07aa02616f4eebef67] https://lava.sirena.org.uk/scheduler/job/1362764 # test job: [7b400c9ab879a86aa4b9bf5d9fdd3df558eed9b5] https://lava.sirena.org.uk/scheduler/job/1362945 # test job: [9f7cd1bcb6363368abc954ff4e727b579813c697] https://lava.sirena.org.uk/scheduler/job/1362536 # test job: [ad6d689e776478113aeef7bfb0e4222b1ff2a986] https://lava.sirena.org.uk/scheduler/job/1363414 # test job: [406fbc4d0fb34c16718551bb8f4c776710f63b55] https://lava.sirena.org.uk/scheduler/job/1359624 # test job: [a71b261c19a455f7f8e560b4ddfac44d3150ae39] https://lava.sirena.org.uk/scheduler/job/1359531 # test job: [6c965d39af98a8b79668898b3a2af40d11179ff4] https://lava.sirena.org.uk/scheduler/job/1358498 # test job: [222a87f6b94f6f177e896d6fcdc7881480344e34] https://lava.sirena.org.uk/scheduler/job/1357704 # test job: [14a3fd030c033453d436233f4c422b4903786ed3] https://lava.sirena.org.uk/scheduler/job/1356472 # test job: [17e3c1a272d97e49b4f3fbfe1f1b889e120d2be8] https://lava.sirena.org.uk/scheduler/job/1364266 # test job: [e68074c63fded9468c513f65734ffb4c80dc2a6d] https://lava.sirena.org.uk/scheduler/job/1351535 # test job: [233d740e3a819829ccd6d21319015a94349d64eb] https://lava.sirena.org.uk/scheduler/job/1351736 # test job: [63e5784d640a5c61a828d33bee24fea4244e479c] https://lava.sirena.org.uk/scheduler/job/1363498 # test job: [2dbe74c63cb73829be0aab0d0e7e68b87071b5fa] https://lava.sirena.org.uk/scheduler/job/1347311 # test job: [f1471bc435afa31c8c0c58551922830dc8f4b06b] https://lava.sirena.org.uk/scheduler/job/1347249 # test job: [2056d7a7df5d9a08144671afccb6970ccd595b89] https://lava.sirena.org.uk/scheduler/job/1347094 # test job: [fed0805ffd76161ed8c056ea30b36550eda8e106] https://lava.sirena.org.uk/scheduler/job/1347380 # test job: [178c169a30b011971cbbf9c79032b5898b1b07de] https://lava.sirena.org.uk/scheduler/job/1343363 # test job: [d20df86b056b95845f6ed52da1010059202a0c23] https://lava.sirena.org.uk/scheduler/job/1343570 # test job: [e6702c44c2adb28b62f81de498e9b1e4562ce660] https://lava.sirena.org.uk/scheduler/job/1339740 # test job: [94602d84163c127ec2374fba0fcb6587a07785ce] https://lava.sirena.org.uk/scheduler/job/1339879 # test job: [d30e845b0ae63400738709ca624a4a7bb69c4ba2] https://lava.sirena.org.uk/scheduler/job/1339607 # test job: [64c05a1d66193b3a40ad1f29c3d8ba5483e4e0dc] https://lava.sirena.org.uk/scheduler/job/1328048 # test job: [c61caec22820f24bb155929f5cee8c1ccfe92f77] https://lava.sirena.org.uk/scheduler/job/1329660 # test job: [0787a08ae785366b9473905fc8bf23f165a08b8d] https://lava.sirena.org.uk/scheduler/job/1327109 # test job: [18197e98353d931fc7bb2bb9ec671d3aa407831d] https://lava.sirena.org.uk/scheduler/job/1326906 # test job: [f198b6b256aabe6d136401505e974ef2eb2df4af] https://lava.sirena.org.uk/scheduler/job/1323377 # test job: [cce73cf7cc56a04cf0dd1e1f93b4002c00751ebe] https://lava.sirena.org.uk/scheduler/job/1323545 # test job: [e358e012a69a3d553803cbe62d9f6eeea57726fc] https://lava.sirena.org.uk/scheduler/job/1322956 # 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test job: [d5099bc1b56417733f4cccf10c61ee74dadd5562] https://lava.sirena.org.uk/scheduler/job/1265077 # test job: [1d9119794c10023ebd7c901aa9aa2c74eb833177] https://lava.sirena.org.uk/scheduler/job/1265333 # test job: [f48887a98b78880b7711aca311fbbbcaad6c4e3b] https://lava.sirena.org.uk/scheduler/job/1371067 # bad: [f48887a98b78880b7711aca311fbbbcaad6c4e3b] Add linux-next specific files for 20250508 git bisect bad f48887a98b78880b7711aca311fbbbcaad6c4e3b # test job: [80badb1d7264e83b512475898e7459f464a009c9] https://lava.sirena.org.uk/scheduler/job/1364772 # bad: [80badb1d7264e83b512475898e7459f464a009c9] clk: imx: add support for i.MX8MN anatop clock driver git bisect bad 80badb1d7264e83b512475898e7459f464a009c9 # test job: [3cbc38cf42ca42d2dc9a93c949e0381ff919df71] https://lava.sirena.org.uk/scheduler/job/1365096 # bad: [3cbc38cf42ca42d2dc9a93c949e0381ff919df71] clk: imx: add support for i.MX8MM anatop clock driver git bisect bad 3cbc38cf42ca42d2dc9a93c949e0381ff919df71 # first bad commit: [3cbc38cf42ca42d2dc9a93c949e0381ff919df71] clk: imx: add support for i.MX8MM anatop clock driver # test job: [4c82bbe8b5437c7f16b2891ce33210c0f1410597] https://lava.sirena.org.uk/scheduler/job/1364509 # bad: [4c82bbe8b5437c7f16b2891ce33210c0f1410597] clk: imx: add support for i.MX8MP anatop clock driver git bisect bad 4c82bbe8b5437c7f16b2891ce33210c0f1410597 # test job: [80badb1d7264e83b512475898e7459f464a009c9] https://lava.sirena.org.uk/scheduler/job/1364772 # bad: [80badb1d7264e83b512475898e7459f464a009c9] clk: imx: add support for i.MX8MN anatop clock driver git bisect bad 80badb1d7264e83b512475898e7459f464a009c9 # test job: [3cbc38cf42ca42d2dc9a93c949e0381ff919df71] https://lava.sirena.org.uk/scheduler/job/1365096 # bad: [3cbc38cf42ca42d2dc9a93c949e0381ff919df71] clk: imx: add support for i.MX8MM anatop clock driver git bisect bad 3cbc38cf42ca42d2dc9a93c949e0381ff919df71 # first bad commit: [3cbc38cf42ca42d2dc9a93c949e0381ff919df71] clk: imx: add support for i.MX8MM anatop clock driver To unsubscribe from this group and stop receiving emails from it, send an email to linux-amarula+unsubscribe@amarulasolutions.com.
On Fri, May 9, 2025 at 3:52 AM Mark Brown <broonie@kernel.org> wrote: > > On Thu, Apr 24, 2025 at 08:21:41AM +0200, Dario Binacchi wrote: > > Support NXP i.MX8M anatop PLL module which generates PLLs to CCM root. > > By doing so, we also simplify the CCM driver code. The changes are > > backward compatible. > > This patch, which has been in -next for the past few days as > 3cbc38cf42ca42d2, breaks boot on i.MX8MP platforms (I have the EVK and > Verdin). We die with: > > [ 1.439320] i.MX clk 1: register failed with -2 > [ 1.441014] i.MX clk 2: register failed with -2 > [ 1.445610] imx8mm-anatop 30360000.clock-controller: NXP i.MX8MM anatop clock driver probed > [ 1.455068] Unable to handle kernel paging request at virtual address fffffffffffffffe From the log I see that you are testing a board with i.MX8MP, but it's probing the anatop for i.MX8MM. Is it possible that you have the CONFIG_CLK_IMX8MM option enabled? In the imx8mp.dtsi device tree, the anatop compatible is: compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop"; So I believe you might have CONFIG_CLK_IMX8MM enabled. One could also consider modifying the anatop compatibles in imx8mn.dtsi and imx8mp.dtsi, removing "fsl,imx8mm-anatop" from them. If you agree and it fixes the issue, I can add the patches that remove that string to version v13. The series has been partially merged, but not the patches that modify the DTS. I have personally tested the patches on i.MX8MN and i.MX8MP architectures, with only CONFIG_CLK_IMX8MN and CONFIG_CLK_IMX8MP enabled respectively, and I didn't encounter any issues. Thanks and regards, Dario > > ... > > [ 1.634650] Call trace: > [ 1.637102] __clk_get_hw+0x4/0x18 (P) > [ 1.640862] imx8mp_clocks_probe+0xdc/0x2f50 > [ 1.645152] platform_probe+0x68/0xc4 > [ 1.648827] really_probe+0xbc/0x298 > [ 1.652413] __driver_probe_device+0x78/0x12c > > Full log at: > > https://lava.sirena.org.uk/scheduler/job/1371067 > > bisect data (not the actual bisetion as it'd run previously but I didn't > get a chance to check the results, has all the commits and their test > results though): > > # bad: [f48887a98b78880b7711aca311fbbbcaad6c4e3b] Add linux-next specific files for 20250508 > # good: [4ea0e68600c61f7d18b218d9af98c5c3bd23e856] Merge branch 'for-linux-next-fixes' of https://gitlab.freedesktop.org/drm/misc/kernel.git > # good: [d75d38dc460452cc8bbca483dee65839e11c71fe] ASoC: tas2781: Add a debugfs node for acoustic tuning > # good: [5bf5bdfd007e07f2ec5b3e07aa02616f4eebef67] ASoC: codec: cs42l52: Convert to GPIO descriptors > # good: [7b400c9ab879a86aa4b9bf5d9fdd3df558eed9b5] ASoC: SOF: add disable_function_topology module parameter > # good: [9f7cd1bcb6363368abc954ff4e727b579813c697] spi: nxp-fspi: use devm instead of remove for driver detach > # good: [ad6d689e776478113aeef7bfb0e4222b1ff2a986] ASoC: amd: sof_amd_sdw: add logic to get cpu_pin_id for ACP7.0/ACP7.1 platforms > # good: [406fbc4d0fb34c16718551bb8f4c776710f63b55] ASoC: cs35l56: Read Silicon ID from DIE_STS registers for CS35L63 > # good: [a71b261c19a455f7f8e560b4ddfac44d3150ae39] ASoC: SOF: imx8m: Use reset controller API to control the DSP > # good: [6c965d39af98a8b79668898b3a2af40d11179ff4] ASoC: Intel: sof_sdw: Avoid NULL check fail when re-probing > # good: [222a87f6b94f6f177e896d6fcdc7881480344e34] spi: cadence-quadspi: Assume device could match via platform > # good: [14a3fd030c033453d436233f4c422b4903786ed3] ASoC: intel: atom: Return -ENOMEM if pcim_iomap() fails > # good: [17e3c1a272d97e49b4f3fbfe1f1b889e120d2be8] clk: imx: add hw API imx_anatop_get_clk_hw > # good: [e68074c63fded9468c513f65734ffb4c80dc2a6d] ASoC: SOF: amd: add build support for soundwire > # good: [233d740e3a819829ccd6d21319015a94349d64eb] spi: loopback-test: Simplify strange loopback value check > # good: [63e5784d640a5c61a828d33bee24fea4244e479c] Merge branch 'ti-k3-dts-next' into ti-next > # good: [2dbe74c63cb73829be0aab0d0e7e68b87071b5fa] spi: dt-bindings: spi-qpic-snand: Add IPQ5018 compatible > # good: [f1471bc435afa31c8c0c58551922830dc8f4b06b] regulator: tps65219: Add TI TPS65214 Regulator Support > # good: [2056d7a7df5d9a08144671afccb6970ccd595b89] ASoC: fsl_rpmsg: Allocate a smaller buffer size for capture stream > # good: [fed0805ffd76161ed8c056ea30b36550eda8e106] ASoC: mediatek: mt8195: use snd_soc_dlc_is_dummy() > # good: [178c169a30b011971cbbf9c79032b5898b1b07de] ASoC: codec: twl4030: Convert to GPIO descriptors > # good: [d20df86b056b95845f6ed52da1010059202a0c23] ASoC: Intel: avs: Fix kcalloc() sizes > # good: [e6702c44c2adb28b62f81de498e9b1e4562ce660] spi: axi-spi-engine: omit SYNC from offload instructions > # good: [94602d84163c127ec2374fba0fcb6587a07785ce] ASoC: wm_adsp: Don't use no_free_ptr() when passing to PTR_ERR() > # good: [d30e845b0ae63400738709ca624a4a7bb69c4ba2] regcache: Use sort()'s default swap() implementation > # good: [64c05a1d66193b3a40ad1f29c3d8ba5483e4e0dc] spi: spi-qpic-snand: remove unused 'wlen' member of 'struct qpic_spi_nand' > # good: [c61caec22820f24bb155929f5cee8c1ccfe92f77] ASoC: renesas: add MSIOF sound support > # good: [0787a08ae785366b9473905fc8bf23f165a08b8d] ASoC: starfive: Use max() to simplify code in jh7110_tdm_syncdiv() > # good: [18197e98353d931fc7bb2bb9ec671d3aa407831d] spi: meson-spicc: add DMA support > # good: [f198b6b256aabe6d136401505e974ef2eb2df4af] ASoC: codec: tpa6130a2: Convert to GPIO descriptors > # good: [cce73cf7cc56a04cf0dd1e1f93b4002c00751ebe] MAINTAINERS: ASoC: Simplify references to Cirrus Logic include files > # good: [e358e012a69a3d553803cbe62d9f6eeea57726fc] ASoC: codecs: wcd938x: drop unnecessary mux flag assignment > # good: [cf0668184d1d2f9ad3f98dd5bbe0ed4d9d090eaa] spi: sh-msiof: ignore driver probing if it was MSIOF Sound > # good: [c283fcdc4e2b89678c171691fd26f576139fc256] spi: tegra210-quad: Update dummy sequence configuration > # good: [b50a1e1f3c4630f729629a787d891d7b4348007f] spi: intel: Improve resource mapping > # good: [5410aa3aa7f7dfcbdfcf94034595765d7e69ead3] regulator: pf9453: convert to use maple tree register cache > # good: [6d7ee6de75010ed5d70f1c496070c4a7cd1968b5] ASoC: adau7118: Allow dsp_a mode > # good: [e8ac7336dd62f0443a675ed80b17f0f0e6846e20] regulator: max20086: Change enable gpio to optional > # good: [0c9f82446123635cfbb8ceeca074f2dce6a0ccae] ASoC: dt-bindings: fsl,mqs: Document audio graph port > # good: [cc78d1eaabad3caf3c425c83037cd8ba1c9f2bc6] ASoC: rockchip: add Serial Audio Interface (SAI) driver > # good: [9ef24511d29f0300fc7e9d4a5ea38d78e9eef73e] ASoC: wm8998: Add Kconfig prompt > # good: [296e8d289bdd7eb0d832683ebd3e847fbb4c1b12] spi: offload: remove unnecessary check on trigger->ops > # good: [4cc9cf2f437ccf6915100c2f38f63cfb1abad6f9] spi: dt-bindings: Fix description mentioning a removed property > # good: [e30b7a75666b3f444abfabed6a144642fa9994d8] spi: dw: Use spi_bpw_to_bytes() helper > # good: [5b974f53424d16165b606e2e2f9208d450a5723c] ASoC: dt-bindings: mt8195: add missing audio routing and link-name > # good: [d981e7b3f25fbabca9cdd02aa2a8f16d6f235fc2] spi: pci1xxxx: Use non-hybrid PCI devres API > # good: [4308487b29f98785ef50dd82fdfca382134b33e7] firmware: cs_dsp: Add some sanity-checking to test harness > # good: [7ed50dc550b0a3bad82f675aaefd8cd00362672d] ASoC: cs48l32: Fix spelling mistake "exceeeds" -> "exceeds" > # good: [51f04358d8c887c5d117440335c7f94285a403f2] ASoC: cs-amp-lib-test: Use flex_array_size() > # good: [e2bcbf99d045f6ae3826e39d1ed25978de17cbfe] ASoC: cs48l32: Add driver for Cirrus Logic CS48L32 audio DSP > # good: [fcdf212fd9b36c299d90229e9546c077db2215ce] ASoC: cs-amp-lib: Annotate struct cirrus_amp_efi_data with __counted_by() > # good: [2b4ce994afca0690ab79b7860045e6883e8706db] ASoC: simple-card-utils: fixup dlc->xxx handling for error case > # good: [46e7ea05bf5d9fe4d05e173c824ae173c956cb5f] ASoC: cs-amp-lib: Replace offsetof() with struct_size() > # good: [4f8ef33dd44a3d1136d3934609b8a43e62aaaa0d] ASoC: soc_sdw_utils: skip the endpoint that doesn't present > # good: [7762fdab23100514e5cb612331c96bd65126ada5] regulator: adp5055: Remove unneeded semicolon > # good: [38c2585c7439cc678ae105dd826f10321db29552] ASoC: codecs: Add support for Richtek rt9123p > # good: [8d2e914482311f7746fe7b0e520bd42794d6aed8] ALSA: hda: cirrus_scodec_test: use new GPIO line value setter callbacks > # good: [436a3cc8afbf34bb68166c2c5c19ca5113c0c756] ASoC: ac97: Add DT support > # good: [186dfc85f9a824e3f8383322747ca75e988486e9] ASoC: tas2764: expose die temp to hwmon > # good: [279b418f477fd6c1c21b1cf212837622c774f15f] spi: fsl-qspi: Optimize fsl_qspi struct > # good: [e78e7856d233010e6afef62f15567a8e7777c8bc] ASoC: test-component: add set_tdm_slot stub implementation > # good: [7a978d8fcf57b283cb8c88dd4c9431502bd36ea8] spi: amd: add CONFIG_PCI dependency > # good: [28cce24d6596a3d8a34689031f2a8a5ac918cde5] regulator: adp5055: remove duplicate device table > # good: [b5d057a86e2086af0b1e6d0ca8b306be1c73a627] ASoC: wm_adsp: Use vmemdup_user() instead of open-coding > # good: [3f7b48efb79d91883d98dd7e33dc2a0abfa9f923] spi: fsl-qspi: Simplify probe error handling using managed API > # good: [aaf6223ea2a1ff9316a81bf851fd5a0e82635b60] regulator: don't compare raw GPIO descriptor pointers > # good: [e686365c0411275474527c2055ac133f2eb47526] spi: spi_amd: Fix an IS_ERR() vs NULL check in probe > # good: [147b2a96f24e0cfcc476378f9356b30662045c7e] regulator: adp5055: Add driver for adp5055 > # good: [265daffe788aa1cc5925d0afcde4fe6e99c66638] gpio: provide gpiod_is_equal() > # good: [5e21900ef64244fadeddc9015e8b8307d116764a] spi: xcomm: use new GPIO line value setter callbacks > # good: [936df52c29b0d422665c5e84b0cffae61611411b] regulator: rpi-panel-attiny: use new GPIO line value setter callbacks > # good: [4c035fab9f42071c4024495afb2cec1409280eed] ASoC: tas2781-i2c: Remove unnecessary NULL check before release_firmware() > # good: [8d18e67abbdf380cd1cfd2c313aac625092d7777] ASoC: Intel: avs: Support 16 TDMs in dynamic assignment > # good: [93fa44f84704dfedc4fe06b89bebc8cfaa5f525b] ASoC: Intel: avs: boards: Change ssm4567 card name > # good: [ce2eadc6f99263dd200e52f692dc7a22698c99f3] regulator: s5m8767: Convert to GPIO descriptors > # good: [b3d9e96c96b0076a11aa1001d55b3dc189b8cd1c] regulator: pf9453: Improve documentation for pf9453_regulator_set_ramp_delay_regmap > # good: [387ddbc7d474967589de15043b47a441f95a50f2] ALSA: hda: Select avs-driver by default on FCL > # good: [4e310626eb4df52a31a142c1360fead0fcbd3793] gpiolib: of: Add polarity quirk for s5m8767 > # good: [b644c2776652671256edcd7a8e71161e212b59ac] spi: spi_amd: Add PCI-based driver for AMD HID2 SPI controller > # good: [69e3433fa5e24edc94e94b4f34e3dbb754bdedbf] spi: spi-stm32-ospi: Make "resets" a required property > # good: [ea61f39b38bdbb7c77ba2c70e130acdb808c8d68] ASoC: sta32x: Remove unnecessary NULL check before clk_disable_unprepare() > # good: [eec611d26f84800852a9badbeafa76db3cdc9118] ASoC: codecs: wcd938x: add mux control support for hp audio mux > # good: [d5099bc1b56417733f4cccf10c61ee74dadd5562] ASoC: codec: wcd9335: Convert to GPIO descriptors > # good: [1d9119794c10023ebd7c901aa9aa2c74eb833177] ASoC: fsl_sai: separate set_tdm_slot() for tx and rx > git bisect start 'f48887a98b78880b7711aca311fbbbcaad6c4e3b' '4ea0e68600c61f7d18b218d9af98c5c3bd23e856' 'd75d38dc460452cc8bbca483dee65839e11c71fe' '5bf5bdfd007e07f2ec5b3e07aa02616f4eebef67' '7b400c9ab879a86aa4b9bf5d9fdd3df558eed9b5' '9f7cd1bcb6363368abc954ff4e727b579813c697' 'ad6d689e776478113aeef7bfb0e4222b1ff2a986' '406fbc4d0fb34c16718551bb8f4c776710f63b55' 'a71b261c19a455f7f8e560b4ddfac44d3150ae39' '6c965d39af98a8b79668898b3a2af40d11179ff4' '222a87f6b94f6f177e896d6fcdc7881480344e34' '14a3fd030c033453d436233f4c422b4903786ed3' '17e3c1a272d97e49b4f3fbfe1f1b889e120d2be8' 'e68074c63fded9468c513f65734ffb4c80dc2a6d' '233d740e3a819829ccd6d21319015a94349d64eb' '63e5784d640a5c61a828d33bee24fea4244e479c' '2dbe74c63cb73829be0aab0d0e7e68b87071b5fa' 'f1471bc435afa31c8c0c58551922830dc8f4b06b' '2056d7a7df5d9a08144671afccb6970ccd595b89' 'fed0805ffd76161ed8c056ea30b36550eda8e106' '178c169a30b011971cbbf9c79032b5898b1b07de' 'd20df86b056b95845f6ed52da1010059202a0c23' 'e6702c44c2adb28b62f81de498e9b1e4562ce660' '94602d84163c127ec2374fba0fcb6587a07785ce' 'd30e845b0ae63400738709ca624a4a7bb69c4ba2' '64c05a1d66193b3a40ad1f29c3d8ba5483e4e0dc' 'c61caec22820f24bb155929f5cee8c1ccfe92f77' '0787a08ae785366b9473905fc8bf23f165a08b8d' '18197e98353d931fc7bb2bb9ec671d3aa407831d' 'f198b6b256aabe6d136401505e974ef2eb2df4af' 'cce73cf7cc56a04cf0dd1e1f93b4002c00751ebe' 'e358e012a69a3d553803cbe62d9f6eeea57726fc' 'cf0668184d1d2f9ad3f98dd5bbe0ed4d9d090eaa' 'c283fcdc4e2b89678c171691fd26f576139fc256' 'b50a1e1f3c4630f729629a787d891d7b4348007f' '5410aa3aa7f7dfcbdfcf94034595765d7e69ead3' '6d7ee6de75010ed5d70f1c496070c4a7cd1968b5' 'e8ac7336dd62f0443a675ed80b17f0f0e6846e20' '0c9f82446123635cfbb8ceeca074f2dce6a0ccae' 'cc78d1eaabad3caf3c425c83037cd8ba1c9f2bc6' '9ef24511d29f0300fc7e9d4a5ea38d78e9eef73e' '296e8d289bdd7eb0d832683ebd3e847fbb4c1b12' '4cc9cf2f437ccf6915100c2f38f63cfb1abad6f9' 'e30b7a75666b3f444abfabed6a144642fa9994d8' '5b974f53424d16165b606e2e2f9208d450a5723c' 'd981e7b3f25fbabca9cdd02aa2a8f16d6f235fc2' '4308487b29f98785ef50dd82fdfca382134b33e7' '7ed50dc550b0a3bad82f675aaefd8cd00362672d' '51f04358d8c887c5d117440335c7f94285a403f2' 'e2bcbf99d045f6ae3826e39d1ed25978de17cbfe' 'fcdf212fd9b36c299d90229e9546c077db2215ce' '2b4ce994afca0690ab79b7860045e6883e8706db' '46e7ea05bf5d9fe4d05e173c824ae173c956cb5f' '4f8ef33dd44a3d1136d3934609b8a43e62aaaa0d' '7762fdab23100514e5cb612331c96bd65126ada5' '38c2585c7439cc678ae105dd826f10321db29552' '8d2e914482311f7746fe7b0e520bd42794d6aed8' '436a3cc8afbf34bb68166c2c5c19ca5113c0c756' '186dfc85f9a824e3f8383322747ca75e988486e9' '279b418f477fd6c1c21b1cf212837622c774f15f' 'e78e7856d233010e6afef62f15567a8e7777c8bc' '7a978d8fcf57b283cb8c88dd4c9431502bd36ea8' '28cce24d6596a3d8a34689031f2a8a5ac918cde5' 'b5d057a86e2086af0b1e6d0ca8b306be1c73a627' '3f7b48efb79d91883d98dd7e33dc2a0abfa9f923' 'aaf6223ea2a1ff9316a81bf851fd5a0e82635b60' 'e686365c0411275474527c2055ac133f2eb47526' '147b2a96f24e0cfcc476378f9356b30662045c7e' '265daffe788aa1cc5925d0afcde4fe6e99c66638' '5e21900ef64244fadeddc9015e8b8307d116764a' '936df52c29b0d422665c5e84b0cffae61611411b' '4c035fab9f42071c4024495afb2cec1409280eed' '8d18e67abbdf380cd1cfd2c313aac625092d7777' '93fa44f84704dfedc4fe06b89bebc8cfaa5f525b' 'ce2eadc6f99263dd200e52f692dc7a22698c99f3' 'b3d9e96c96b0076a11aa1001d55b3dc189b8cd1c' '387ddbc7d474967589de15043b47a441f95a50f2' '4e310626eb4df52a31a142c1360fead0fcbd3793' 'b644c2776652671256edcd7a8e71161e212b59ac' '69e3433fa5e24edc94e94b4f34e3dbb754bdedbf' 'ea61f39b38bdbb7c77ba2c70e130acdb808c8d68' 'eec611d26f84800852a9badbeafa76db3cdc9118' 'd5099bc1b56417733f4cccf10c61ee74dadd5562' '1d9119794c10023ebd7c901aa9aa2c74eb833177' > # test job: [d75d38dc460452cc8bbca483dee65839e11c71fe] https://lava.sirena.org.uk/scheduler/job/1365900 > # test job: [5bf5bdfd007e07f2ec5b3e07aa02616f4eebef67] https://lava.sirena.org.uk/scheduler/job/1362764 > # test job: [7b400c9ab879a86aa4b9bf5d9fdd3df558eed9b5] https://lava.sirena.org.uk/scheduler/job/1362945 > # test job: [9f7cd1bcb6363368abc954ff4e727b579813c697] https://lava.sirena.org.uk/scheduler/job/1362536 > # test job: [ad6d689e776478113aeef7bfb0e4222b1ff2a986] https://lava.sirena.org.uk/scheduler/job/1363414 > # test job: [406fbc4d0fb34c16718551bb8f4c776710f63b55] https://lava.sirena.org.uk/scheduler/job/1359624 > # test job: [a71b261c19a455f7f8e560b4ddfac44d3150ae39] https://lava.sirena.org.uk/scheduler/job/1359531 > # test job: [6c965d39af98a8b79668898b3a2af40d11179ff4] https://lava.sirena.org.uk/scheduler/job/1358498 > # test job: [222a87f6b94f6f177e896d6fcdc7881480344e34] https://lava.sirena.org.uk/scheduler/job/1357704 > # test job: [14a3fd030c033453d436233f4c422b4903786ed3] https://lava.sirena.org.uk/scheduler/job/1356472 > # test job: [17e3c1a272d97e49b4f3fbfe1f1b889e120d2be8] https://lava.sirena.org.uk/scheduler/job/1364266 > # test job: [e68074c63fded9468c513f65734ffb4c80dc2a6d] https://lava.sirena.org.uk/scheduler/job/1351535 > # test job: [233d740e3a819829ccd6d21319015a94349d64eb] https://lava.sirena.org.uk/scheduler/job/1351736 > # test job: [63e5784d640a5c61a828d33bee24fea4244e479c] https://lava.sirena.org.uk/scheduler/job/1363498 > # test job: [2dbe74c63cb73829be0aab0d0e7e68b87071b5fa] https://lava.sirena.org.uk/scheduler/job/1347311 > # test job: [f1471bc435afa31c8c0c58551922830dc8f4b06b] https://lava.sirena.org.uk/scheduler/job/1347249 > # test job: [2056d7a7df5d9a08144671afccb6970ccd595b89] https://lava.sirena.org.uk/scheduler/job/1347094 > # test job: [fed0805ffd76161ed8c056ea30b36550eda8e106] https://lava.sirena.org.uk/scheduler/job/1347380 > # test job: [178c169a30b011971cbbf9c79032b5898b1b07de] https://lava.sirena.org.uk/scheduler/job/1343363 > # test job: [d20df86b056b95845f6ed52da1010059202a0c23] https://lava.sirena.org.uk/scheduler/job/1343570 > # test job: [e6702c44c2adb28b62f81de498e9b1e4562ce660] https://lava.sirena.org.uk/scheduler/job/1339740 > # test job: [94602d84163c127ec2374fba0fcb6587a07785ce] https://lava.sirena.org.uk/scheduler/job/1339879 > # test job: [d30e845b0ae63400738709ca624a4a7bb69c4ba2] https://lava.sirena.org.uk/scheduler/job/1339607 > # test job: [64c05a1d66193b3a40ad1f29c3d8ba5483e4e0dc] https://lava.sirena.org.uk/scheduler/job/1328048 > # test job: [c61caec22820f24bb155929f5cee8c1ccfe92f77] https://lava.sirena.org.uk/scheduler/job/1329660 > # test job: [0787a08ae785366b9473905fc8bf23f165a08b8d] https://lava.sirena.org.uk/scheduler/job/1327109 > # test job: [18197e98353d931fc7bb2bb9ec671d3aa407831d] https://lava.sirena.org.uk/scheduler/job/1326906 > # test job: [f198b6b256aabe6d136401505e974ef2eb2df4af] https://lava.sirena.org.uk/scheduler/job/1323377 > # test job: [cce73cf7cc56a04cf0dd1e1f93b4002c00751ebe] https://lava.sirena.org.uk/scheduler/job/1323545 > # test job: [e358e012a69a3d553803cbe62d9f6eeea57726fc] https://lava.sirena.org.uk/scheduler/job/1322956 > # test job: [cf0668184d1d2f9ad3f98dd5bbe0ed4d9d090eaa] https://lava.sirena.org.uk/scheduler/job/1323325 > # test job: [c283fcdc4e2b89678c171691fd26f576139fc256] https://lava.sirena.org.uk/scheduler/job/1323757 > # test job: [b50a1e1f3c4630f729629a787d891d7b4348007f] https://lava.sirena.org.uk/scheduler/job/1323222 > # test job: [5410aa3aa7f7dfcbdfcf94034595765d7e69ead3] https://lava.sirena.org.uk/scheduler/job/1323393 > # test job: [6d7ee6de75010ed5d70f1c496070c4a7cd1968b5] https://lava.sirena.org.uk/scheduler/job/1315774 > # test job: [e8ac7336dd62f0443a675ed80b17f0f0e6846e20] https://lava.sirena.org.uk/scheduler/job/1314126 > # test job: [0c9f82446123635cfbb8ceeca074f2dce6a0ccae] https://lava.sirena.org.uk/scheduler/job/1314081 > # test job: [cc78d1eaabad3caf3c425c83037cd8ba1c9f2bc6] https://lava.sirena.org.uk/scheduler/job/1314240 > # test job: [9ef24511d29f0300fc7e9d4a5ea38d78e9eef73e] https://lava.sirena.org.uk/scheduler/job/1312532 > # test job: [296e8d289bdd7eb0d832683ebd3e847fbb4c1b12] https://lava.sirena.org.uk/scheduler/job/1312439 > # test job: [4cc9cf2f437ccf6915100c2f38f63cfb1abad6f9] https://lava.sirena.org.uk/scheduler/job/1305280 > # test job: [e30b7a75666b3f444abfabed6a144642fa9994d8] https://lava.sirena.org.uk/scheduler/job/1303190 > # test job: [5b974f53424d16165b606e2e2f9208d450a5723c] https://lava.sirena.org.uk/scheduler/job/1302208 > # test job: [d981e7b3f25fbabca9cdd02aa2a8f16d6f235fc2] https://lava.sirena.org.uk/scheduler/job/1302522 > # test job: [4308487b29f98785ef50dd82fdfca382134b33e7] https://lava.sirena.org.uk/scheduler/job/1300513 > # test job: [7ed50dc550b0a3bad82f675aaefd8cd00362672d] https://lava.sirena.org.uk/scheduler/job/1298919 > # test job: [51f04358d8c887c5d117440335c7f94285a403f2] https://lava.sirena.org.uk/scheduler/job/1295719 > # test job: [e2bcbf99d045f6ae3826e39d1ed25978de17cbfe] https://lava.sirena.org.uk/scheduler/job/1295274 > # test job: [fcdf212fd9b36c299d90229e9546c077db2215ce] https://lava.sirena.org.uk/scheduler/job/1294990 > # test job: [2b4ce994afca0690ab79b7860045e6883e8706db] https://lava.sirena.org.uk/scheduler/job/1291891 > # test job: [46e7ea05bf5d9fe4d05e173c824ae173c956cb5f] https://lava.sirena.org.uk/scheduler/job/1292754 > # test job: [4f8ef33dd44a3d1136d3934609b8a43e62aaaa0d] https://lava.sirena.org.uk/scheduler/job/1291553 > # test job: [7762fdab23100514e5cb612331c96bd65126ada5] https://lava.sirena.org.uk/scheduler/job/1291202 > # test job: [38c2585c7439cc678ae105dd826f10321db29552] https://lava.sirena.org.uk/scheduler/job/1288605 > # test job: [8d2e914482311f7746fe7b0e520bd42794d6aed8] https://lava.sirena.org.uk/scheduler/job/1289528 > # test job: [436a3cc8afbf34bb68166c2c5c19ca5113c0c756] https://lava.sirena.org.uk/scheduler/job/1289106 > # test job: [186dfc85f9a824e3f8383322747ca75e988486e9] https://lava.sirena.org.uk/scheduler/job/1289043 > # test job: [279b418f477fd6c1c21b1cf212837622c774f15f] https://lava.sirena.org.uk/scheduler/job/1288843 > # test job: [e78e7856d233010e6afef62f15567a8e7777c8bc] https://lava.sirena.org.uk/scheduler/job/1285079 > # test job: [7a978d8fcf57b283cb8c88dd4c9431502bd36ea8] https://lava.sirena.org.uk/scheduler/job/1280819 > # test job: [28cce24d6596a3d8a34689031f2a8a5ac918cde5] https://lava.sirena.org.uk/scheduler/job/1280765 > # test job: [b5d057a86e2086af0b1e6d0ca8b306be1c73a627] https://lava.sirena.org.uk/scheduler/job/1280149 > # test job: [3f7b48efb79d91883d98dd7e33dc2a0abfa9f923] https://lava.sirena.org.uk/scheduler/job/1280239 > # test job: [aaf6223ea2a1ff9316a81bf851fd5a0e82635b60] https://lava.sirena.org.uk/scheduler/job/1276161 > # test job: [e686365c0411275474527c2055ac133f2eb47526] https://lava.sirena.org.uk/scheduler/job/1276125 > # test job: [147b2a96f24e0cfcc476378f9356b30662045c7e] https://lava.sirena.org.uk/scheduler/job/1276191 > # test job: [265daffe788aa1cc5925d0afcde4fe6e99c66638] https://lava.sirena.org.uk/scheduler/job/1276066 > # test job: [5e21900ef64244fadeddc9015e8b8307d116764a] https://lava.sirena.org.uk/scheduler/job/1270805 > # test job: [936df52c29b0d422665c5e84b0cffae61611411b] https://lava.sirena.org.uk/scheduler/job/1270769 > # test job: [4c035fab9f42071c4024495afb2cec1409280eed] https://lava.sirena.org.uk/scheduler/job/1269332 > # test job: [8d18e67abbdf380cd1cfd2c313aac625092d7777] https://lava.sirena.org.uk/scheduler/job/1267373 > # test job: [93fa44f84704dfedc4fe06b89bebc8cfaa5f525b] https://lava.sirena.org.uk/scheduler/job/1267470 > # test job: [ce2eadc6f99263dd200e52f692dc7a22698c99f3] https://lava.sirena.org.uk/scheduler/job/1266916 > # test job: [b3d9e96c96b0076a11aa1001d55b3dc189b8cd1c] https://lava.sirena.org.uk/scheduler/job/1266978 > # test job: [387ddbc7d474967589de15043b47a441f95a50f2] https://lava.sirena.org.uk/scheduler/job/1267136 > # test job: [4e310626eb4df52a31a142c1360fead0fcbd3793] https://lava.sirena.org.uk/scheduler/job/1268838 > # test job: [b644c2776652671256edcd7a8e71161e212b59ac] https://lava.sirena.org.uk/scheduler/job/1264609 > # test job: [69e3433fa5e24edc94e94b4f34e3dbb754bdedbf] https://lava.sirena.org.uk/scheduler/job/1264874 > # test job: [ea61f39b38bdbb7c77ba2c70e130acdb808c8d68] https://lava.sirena.org.uk/scheduler/job/1265272 > # test job: [eec611d26f84800852a9badbeafa76db3cdc9118] https://lava.sirena.org.uk/scheduler/job/1265133 > # test job: [d5099bc1b56417733f4cccf10c61ee74dadd5562] https://lava.sirena.org.uk/scheduler/job/1265077 > # test job: [1d9119794c10023ebd7c901aa9aa2c74eb833177] https://lava.sirena.org.uk/scheduler/job/1265333 > # test job: [f48887a98b78880b7711aca311fbbbcaad6c4e3b] https://lava.sirena.org.uk/scheduler/job/1371067 > # bad: [f48887a98b78880b7711aca311fbbbcaad6c4e3b] Add linux-next specific files for 20250508 > git bisect bad f48887a98b78880b7711aca311fbbbcaad6c4e3b > # test job: [80badb1d7264e83b512475898e7459f464a009c9] https://lava.sirena.org.uk/scheduler/job/1364772 > # bad: [80badb1d7264e83b512475898e7459f464a009c9] clk: imx: add support for i.MX8MN anatop clock driver > git bisect bad 80badb1d7264e83b512475898e7459f464a009c9 > # test job: [3cbc38cf42ca42d2dc9a93c949e0381ff919df71] https://lava.sirena.org.uk/scheduler/job/1365096 > # bad: [3cbc38cf42ca42d2dc9a93c949e0381ff919df71] clk: imx: add support for i.MX8MM anatop clock driver > git bisect bad 3cbc38cf42ca42d2dc9a93c949e0381ff919df71 > # first bad commit: [3cbc38cf42ca42d2dc9a93c949e0381ff919df71] clk: imx: add support for i.MX8MM anatop clock driver > # test job: [4c82bbe8b5437c7f16b2891ce33210c0f1410597] https://lava.sirena.org.uk/scheduler/job/1364509 > # bad: [4c82bbe8b5437c7f16b2891ce33210c0f1410597] clk: imx: add support for i.MX8MP anatop clock driver > git bisect bad 4c82bbe8b5437c7f16b2891ce33210c0f1410597 > # test job: [80badb1d7264e83b512475898e7459f464a009c9] https://lava.sirena.org.uk/scheduler/job/1364772 > # bad: [80badb1d7264e83b512475898e7459f464a009c9] clk: imx: add support for i.MX8MN anatop clock driver > git bisect bad 80badb1d7264e83b512475898e7459f464a009c9 > # test job: [3cbc38cf42ca42d2dc9a93c949e0381ff919df71] https://lava.sirena.org.uk/scheduler/job/1365096 > # bad: [3cbc38cf42ca42d2dc9a93c949e0381ff919df71] clk: imx: add support for i.MX8MM anatop clock driver > git bisect bad 3cbc38cf42ca42d2dc9a93c949e0381ff919df71 > # first bad commit: [3cbc38cf42ca42d2dc9a93c949e0381ff919df71] clk: imx: add support for i.MX8MM anatop clock driver
On Fri, May 09, 2025 at 10:34:38AM +0200, Dario Binacchi wrote: > From the log I see that you are testing a board with i.MX8MP, but it's > probing the anatop for i.MX8MM. > Is it possible that you have the CONFIG_CLK_IMX8MM option enabled? This is an arm64 defconfig so whatever that has set, including the above. Note that arm64 is supposed to be single kernel build for all platforms so we shouldn't explode due to config options for other platforms. Current -next defconfig: https://builds.sirena.org.uk/f48887a98b78880b7711aca311fbbbcaad6c4e3b/arm64/defconfig/config > I have personally tested the patches on i.MX8MN and i.MX8MP > architectures, with only > CONFIG_CLK_IMX8MN and CONFIG_CLK_IMX8MP enabled respectively, and I > didn't encounter any issues. Given it's wide use for CI the defconfig really needs covering, any random combination of options that can be set ought to work though. To unsubscribe from this group and stop receiving emails from it, send an email to linux-amarula+unsubscribe@amarulasolutions.com.
On Fri, May 9, 2025 at 11:00 AM Mark Brown <broonie@kernel.org> wrote: > > On Fri, May 09, 2025 at 10:34:38AM +0200, Dario Binacchi wrote: > > > From the log I see that you are testing a board with i.MX8MP, but it's > > probing the anatop for i.MX8MM. > > Is it possible that you have the CONFIG_CLK_IMX8MM option enabled? > > This is an arm64 defconfig so whatever that has set, including the > above. Note that arm64 is supposed to be single kernel build for all > platforms so we shouldn't explode due to config options for other > platforms. Ok. I'll fix it asap. Thanks and regards, Dario > > Current -next defconfig: > > https://builds.sirena.org.uk/f48887a98b78880b7711aca311fbbbcaad6c4e3b/arm64/defconfig/config > > > I have personally tested the patches on i.MX8MN and i.MX8MP > > architectures, with only > > CONFIG_CLK_IMX8MN and CONFIG_CLK_IMX8MP enabled respectively, and I > > didn't encounter any issues. > > Given it's wide use for CI the defconfig really needs covering, any > random combination of options that can be set ought to work though.
On Fri, May 09, 2025 at 10:52:51AM +0900, Mark Brown wrote: > On Thu, Apr 24, 2025 at 08:21:41AM +0200, Dario Binacchi wrote: > > Support NXP i.MX8M anatop PLL module which generates PLLs to CCM root. > > By doing so, we also simplify the CCM driver code. The changes are > > backward compatible. > > This patch, which has been in -next for the past few days as > 3cbc38cf42ca42d2, breaks boot on i.MX8MP platforms (I have the EVK and > Verdin). We die with: This boot break is still present in -next, and I've not seen a fix posted yet. Should we just revert the relevant patches until a fix is available? To unsubscribe from this group and stop receiving emails from it, send an email to linux-amarula+unsubscribe@amarulasolutions.com.
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 03f2b2a1ab63..bf35b1236591 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -25,7 +25,7 @@ mxc-clk-objs += clk-sscg-pll.o mxc-clk-objs += clk-gpr-mux.o obj-$(CONFIG_MXC_CLK) += mxc-clk.o -obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o +obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm-anatop.o clk-imx8mm.o obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o clk-imx8mp-audiomix.o obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o diff --git a/drivers/clk/imx/clk-imx8mm-anatop.c b/drivers/clk/imx/clk-imx8mm-anatop.c new file mode 100644 index 000000000000..4ac870df6370 --- /dev/null +++ b/drivers/clk/imx/clk-imx8mm-anatop.c @@ -0,0 +1,287 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * clk-imx8mm-anatop.c - NXP i.MX8MM anatop clock driver + * + * Copyright (c) 2025 Dario Binacchi <dario.binacchi@amarulasolutions.com> + */ + +#include <dt-bindings/clock/imx8mm-clock.h> + +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/of_platform.h> + +#include "clk.h" + +#define IMX8MM_ANATOP_CLK_END (IMX8MM_ANATOP_CLK_CLKOUT2 + 1) + +static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", }; +static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", }; +static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", }; +static const char * const video_pll_bypass_sels[] = {"video_pll", "video_pll_ref_sel", }; +static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", }; +static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", }; +static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", }; +static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; +static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", }; +static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll_out", + "dummy", "dummy", "gpu_pll_out", "vpu_pll_out", + "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3", + "dummy", "dummy", "osc_24m", "dummy", "osc_32k"}; + +static struct clk_hw_onecell_data *clk_hw_data; +static struct clk_hw **hws; + +static int imx8mm_anatop_clocks_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + void __iomem *base; + int ret; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) { + dev_err(dev, "failed to get base address\n"); + return PTR_ERR(base); + } + + clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, + IMX8MM_ANATOP_CLK_END), + GFP_KERNEL); + if (WARN_ON(!clk_hw_data)) + return -ENOMEM; + + clk_hw_data->num = IMX8MM_ANATOP_CLK_END; + hws = clk_hw_data->hws; + + hws[IMX8MM_ANATOP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); + hws[IMX8MM_ANATOP_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k"); + hws[IMX8MM_ANATOP_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m"); + + hws[IMX8MM_ANATOP_AUDIO_PLL1_REF_SEL] = + imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MM_ANATOP_AUDIO_PLL2_REF_SEL] = + imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MM_ANATOP_VIDEO_PLL_REF_SEL] = + imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MM_ANATOP_DRAM_PLL_REF_SEL] = + imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MM_ANATOP_GPU_PLL_REF_SEL] = + imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MM_ANATOP_VPU_PLL_REF_SEL] = + imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MM_ANATOP_ARM_PLL_REF_SEL] = + imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MM_ANATOP_SYS_PLL3_REF_SEL] = + imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + + hws[IMX8MM_ANATOP_AUDIO_PLL1] = + imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", + base, &imx_1443x_pll); + hws[IMX8MM_ANATOP_AUDIO_PLL2] = + imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", + base + 0x14, &imx_1443x_pll); + hws[IMX8MM_ANATOP_VIDEO_PLL] = + imx_clk_hw_pll14xx("video_pll", "video_pll_ref_sel", + base + 0x28, &imx_1443x_pll); + hws[IMX8MM_ANATOP_DRAM_PLL] = + imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", + base + 0x50, &imx_1443x_dram_pll); + hws[IMX8MM_ANATOP_GPU_PLL] = + imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", + base + 0x64, &imx_1416x_pll); + hws[IMX8MM_ANATOP_VPU_PLL] = + imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", + base + 0x74, &imx_1416x_pll); + hws[IMX8MM_ANATOP_ARM_PLL] = + imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", + base + 0x84, &imx_1416x_pll); + hws[IMX8MM_ANATOP_SYS_PLL1] = imx_clk_hw_fixed("sys_pll1", 800000000); + hws[IMX8MM_ANATOP_SYS_PLL2] = imx_clk_hw_fixed("sys_pll2", 1000000000); + hws[IMX8MM_ANATOP_SYS_PLL3] = + imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel", + base + 0x114, &imx_1416x_pll); + + /* PLL bypass out */ + hws[IMX8MM_ANATOP_AUDIO_PLL1_BYPASS] = + imx_clk_hw_mux_flags("audio_pll1_bypass", base, 16, 1, + audio_pll1_bypass_sels, + ARRAY_SIZE(audio_pll1_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MM_ANATOP_AUDIO_PLL2_BYPASS] = + imx_clk_hw_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1, + audio_pll2_bypass_sels, + ARRAY_SIZE(audio_pll2_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MM_ANATOP_VIDEO_PLL_BYPASS] = + imx_clk_hw_mux_flags("video_pll_bypass", base + 0x28, 16, 1, + video_pll_bypass_sels, + ARRAY_SIZE(video_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MM_ANATOP_DRAM_PLL_BYPASS] = + imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, + dram_pll_bypass_sels, + ARRAY_SIZE(dram_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MM_ANATOP_GPU_PLL_BYPASS] = + imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, + gpu_pll_bypass_sels, + ARRAY_SIZE(gpu_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MM_ANATOP_VPU_PLL_BYPASS] = + imx_clk_hw_mux_flags("vpu_pll_bypass", base + 0x74, 28, 1, + vpu_pll_bypass_sels, + ARRAY_SIZE(vpu_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MM_ANATOP_ARM_PLL_BYPASS] = + imx_clk_hw_mux_flags("arm_pll_bypass", base + 0x84, 28, 1, + arm_pll_bypass_sels, + ARRAY_SIZE(arm_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MM_ANATOP_SYS_PLL3_BYPASS] = + imx_clk_hw_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1, + sys_pll3_bypass_sels, + ARRAY_SIZE(sys_pll3_bypass_sels), + CLK_SET_RATE_PARENT); + + /* PLL out gate */ + hws[IMX8MM_ANATOP_AUDIO_PLL1_OUT] = + imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", + base, 13); + hws[IMX8MM_ANATOP_AUDIO_PLL2_OUT] = + imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", + base + 0x14, 13); + hws[IMX8MM_ANATOP_VIDEO_PLL_OUT] = + imx_clk_hw_gate("video_pll_out", "video_pll_bypass", + base + 0x28, 13); + hws[IMX8MM_ANATOP_DRAM_PLL_OUT] = + imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", + base + 0x50, 13); + hws[IMX8MM_ANATOP_GPU_PLL_OUT] = + imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", + base + 0x64, 11); + hws[IMX8MM_ANATOP_VPU_PLL_OUT] = + imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypass", + base + 0x74, 11); + hws[IMX8MM_ANATOP_ARM_PLL_OUT] = + imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", + base + 0x84, 11); + hws[IMX8MM_ANATOP_SYS_PLL3_OUT] = + imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", + base + 0x114, 11); + + /* SYS PLL1 fixed output */ + hws[IMX8MM_ANATOP_SYS_PLL1_OUT] = + imx_clk_hw_gate("sys_pll1_out", "sys_pll1", + base + 0x94, 11); + + hws[IMX8MM_ANATOP_SYS_PLL1_40M] = + imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20); + hws[IMX8MM_ANATOP_SYS_PLL1_80M] = + imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10); + hws[IMX8MM_ANATOP_SYS_PLL1_100M] = + imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8); + hws[IMX8MM_ANATOP_SYS_PLL1_133M] = + imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6); + hws[IMX8MM_ANATOP_SYS_PLL1_160M] = + imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5); + hws[IMX8MM_ANATOP_SYS_PLL1_200M] = + imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4); + hws[IMX8MM_ANATOP_SYS_PLL1_266M] = + imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3); + hws[IMX8MM_ANATOP_SYS_PLL1_400M] = + imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2); + hws[IMX8MM_ANATOP_SYS_PLL1_800M] = + imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1); + + /* SYS PLL2 fixed output */ + hws[IMX8MM_ANATOP_SYS_PLL2_OUT] = + imx_clk_hw_gate("sys_pll2_out", "sys_pll2", + base + 0x104, 11); + + hws[IMX8MM_ANATOP_SYS_PLL2_50M] = + imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20); + hws[IMX8MM_ANATOP_SYS_PLL2_100M] = + imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10); + hws[IMX8MM_ANATOP_SYS_PLL2_125M] = + imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8); + hws[IMX8MM_ANATOP_SYS_PLL2_166M] = + imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6); + hws[IMX8MM_ANATOP_SYS_PLL2_200M] = + imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5); + hws[IMX8MM_ANATOP_SYS_PLL2_250M] = + imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4); + hws[IMX8MM_ANATOP_SYS_PLL2_333M] = + imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3); + hws[IMX8MM_ANATOP_SYS_PLL2_500M] = + imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2); + hws[IMX8MM_ANATOP_SYS_PLL2_1000M] = + imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1); + + hws[IMX8MM_ANATOP_CLK_CLKOUT1_SEL] = + imx_clk_hw_mux2("clkout1_sel", base + 0x128, 4, 4, + clkout_sels, ARRAY_SIZE(clkout_sels)); + hws[IMX8MM_ANATOP_CLK_CLKOUT1_DIV] = + imx_clk_hw_divider("clkout1_div", "clkout1_sel", + base + 0x128, 0, 4); + hws[IMX8MM_ANATOP_CLK_CLKOUT1] = + imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8); + hws[IMX8MM_ANATOP_CLK_CLKOUT2_SEL] = + imx_clk_hw_mux2("clkout2_sel", base + 0x128, 20, 4, + clkout_sels, ARRAY_SIZE(clkout_sels)); + hws[IMX8MM_ANATOP_CLK_CLKOUT2_DIV] = + imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, + 16, 4); + hws[IMX8MM_ANATOP_CLK_CLKOUT2] = + imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24); + + imx_check_clk_hws(hws, IMX8MM_ANATOP_CLK_END); + + ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); + if (ret < 0) { + imx_unregister_hw_clocks(hws, IMX8MM_ANATOP_CLK_END); + return dev_err_probe(dev, ret, + "failed to register anatop clock provider\n"); + } + + dev_info(dev, "NXP i.MX8MM anatop clock driver probed\n"); + return 0; +} + +static const struct of_device_id imx8mm_anatop_clk_of_match[] = { + { .compatible = "fsl,imx8mm-anatop" }, + { /* Sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, imx8mm_anatop_clk_of_match); + +static struct platform_driver imx8mm_anatop_clk_driver = { + .probe = imx8mm_anatop_clocks_probe, + .driver = { + .name = "imx8mm-anatop", + /* + * Disable bind attributes: clocks are not removed and + * reloading the driver will crash or break devices. + */ + .suppress_bind_attrs = true, + .of_match_table = imx8mm_anatop_clk_of_match, + }, +}; + +module_platform_driver(imx8mm_anatop_clk_driver); + +MODULE_AUTHOR("Dario Binacchi <dario.binacchi@amarulasolutions.com>"); +MODULE_DESCRIPTION("NXP i.MX8MM anatop clock driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 8a1fc7e17ba2..d39de0a81a6f 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -25,16 +25,6 @@ static u32 share_count_disp; static u32 share_count_pdm; static u32 share_count_nand; -static const char *pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", }; -static const char *audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", }; -static const char *audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", }; -static const char *video_pll_bypass_sels[] = {"video_pll", "video_pll_ref_sel", }; -static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", }; -static const char *gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", }; -static const char *vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", }; -static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; -static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", }; - /* CCM ROOT */ static const char *imx8mm_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", }; @@ -288,21 +278,20 @@ static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "dummy", " static const char *imx8mm_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m", "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", "osc_32k", }; -static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll_out", - "dummy", "dummy", "gpu_pll_out", "vpu_pll_out", - "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3", - "dummy", "dummy", "osc_24m", "dummy", "osc_32k"}; - static struct clk_hw_onecell_data *clk_hw_data; static struct clk_hw **hws; static int imx8mm_clocks_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - struct device_node *np = dev->of_node; + struct device_node *np = dev->of_node, *anp; void __iomem *base; int ret; + base = devm_platform_ioremap_resource(pdev, 0); + if (WARN_ON(IS_ERR(base))) + return PTR_ERR(base); + clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, IMX8MM_CLK_END), GFP_KERNEL); if (WARN_ON(!clk_hw_data)) @@ -311,96 +300,92 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) clk_hw_data->num = IMX8MM_CLK_END; hws = clk_hw_data->hws; - hws[IMX8MM_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); - hws[IMX8MM_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m"); - hws[IMX8MM_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k"); + anp = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop"); + if (!anp) + return dev_err_probe(dev, -ENODEV, "missing anatop\n"); + + of_node_put(anp); + + hws[IMX8MM_CLK_DUMMY] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_CLK_DUMMY); + hws[IMX8MM_CLK_24M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_CLK_24M); + hws[IMX8MM_CLK_32K] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_CLK_32K); hws[IMX8MM_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1"); hws[IMX8MM_CLK_EXT2] = imx_get_clk_hw_by_name(np, "clk_ext2"); hws[IMX8MM_CLK_EXT3] = imx_get_clk_hw_by_name(np, "clk_ext3"); hws[IMX8MM_CLK_EXT4] = imx_get_clk_hw_by_name(np, "clk_ext4"); - np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop"); - base = of_iomap(np, 0); - of_node_put(np); - if (WARN_ON(!base)) - return -ENOMEM; - - hws[IMX8MM_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MM_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MM_VIDEO_PLL_REF_SEL] = imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MM_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MM_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MM_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MM_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MM_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - - hws[IMX8MM_AUDIO_PLL1] = imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx_1443x_pll); - hws[IMX8MM_AUDIO_PLL2] = imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx_1443x_pll); - hws[IMX8MM_VIDEO_PLL] = imx_clk_hw_pll14xx("video_pll", "video_pll_ref_sel", base + 0x28, &imx_1443x_pll); - hws[IMX8MM_DRAM_PLL] = imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_dram_pll); - hws[IMX8MM_GPU_PLL] = imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx_1416x_pll); - hws[IMX8MM_VPU_PLL] = imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx_1416x_pll); - hws[IMX8MM_ARM_PLL] = imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx_1416x_pll); - hws[IMX8MM_SYS_PLL1] = imx_clk_hw_fixed("sys_pll1", 800000000); - hws[IMX8MM_SYS_PLL2] = imx_clk_hw_fixed("sys_pll2", 1000000000); - hws[IMX8MM_SYS_PLL3] = imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx_1416x_pll); + hws[IMX8MM_AUDIO_PLL1_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_AUDIO_PLL1_REF_SEL); + hws[IMX8MM_AUDIO_PLL2_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_AUDIO_PLL2_REF_SEL); + hws[IMX8MM_VIDEO_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_VIDEO_PLL_REF_SEL); + hws[IMX8MM_DRAM_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_DRAM_PLL_REF_SEL); + hws[IMX8MM_GPU_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_GPU_PLL_REF_SEL); + hws[IMX8MM_VPU_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_VPU_PLL_REF_SEL); + hws[IMX8MM_ARM_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_ARM_PLL_REF_SEL); + hws[IMX8MM_SYS_PLL3_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL3_REF_SEL); + + hws[IMX8MM_AUDIO_PLL1] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_AUDIO_PLL1); + hws[IMX8MM_AUDIO_PLL2] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_AUDIO_PLL2); + hws[IMX8MM_VIDEO_PLL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_VIDEO_PLL); + hws[IMX8MM_DRAM_PLL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_DRAM_PLL); + hws[IMX8MM_GPU_PLL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_GPU_PLL); + hws[IMX8MM_VPU_PLL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_VPU_PLL); + hws[IMX8MM_ARM_PLL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_ARM_PLL); + hws[IMX8MM_SYS_PLL1] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL1); + hws[IMX8MM_SYS_PLL2] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL2); + hws[IMX8MM_SYS_PLL3] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL3); /* PLL bypass out */ - hws[IMX8MM_AUDIO_PLL1_BYPASS] = imx_clk_hw_mux_flags("audio_pll1_bypass", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT); - hws[IMX8MM_AUDIO_PLL2_BYPASS] = imx_clk_hw_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT); - hws[IMX8MM_VIDEO_PLL_BYPASS] = imx_clk_hw_mux_flags("video_pll_bypass", base + 0x28, 16, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_bypass_sels), CLK_SET_RATE_PARENT); - hws[IMX8MM_DRAM_PLL_BYPASS] = imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT); - hws[IMX8MM_GPU_PLL_BYPASS] = imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT); - hws[IMX8MM_VPU_PLL_BYPASS] = imx_clk_hw_mux_flags("vpu_pll_bypass", base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT); - hws[IMX8MM_ARM_PLL_BYPASS] = imx_clk_hw_mux_flags("arm_pll_bypass", base + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT); - hws[IMX8MM_SYS_PLL3_BYPASS] = imx_clk_hw_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT); + hws[IMX8MM_AUDIO_PLL1_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_AUDIO_PLL1_BYPASS); + hws[IMX8MM_AUDIO_PLL2_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_AUDIO_PLL2_BYPASS); + hws[IMX8MM_VIDEO_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_VIDEO_PLL_BYPASS); + hws[IMX8MM_DRAM_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_DRAM_PLL_BYPASS); + hws[IMX8MM_GPU_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_GPU_PLL_BYPASS); + hws[IMX8MM_VPU_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_VPU_PLL_BYPASS); + hws[IMX8MM_ARM_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_ARM_PLL_BYPASS); + hws[IMX8MM_SYS_PLL3_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL3_BYPASS); /* PLL out gate */ - hws[IMX8MM_AUDIO_PLL1_OUT] = imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", base, 13); - hws[IMX8MM_AUDIO_PLL2_OUT] = imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x14, 13); - hws[IMX8MM_VIDEO_PLL_OUT] = imx_clk_hw_gate("video_pll_out", "video_pll_bypass", base + 0x28, 13); - hws[IMX8MM_DRAM_PLL_OUT] = imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13); - hws[IMX8MM_GPU_PLL_OUT] = imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 11); - hws[IMX8MM_VPU_PLL_OUT] = imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x74, 11); - hws[IMX8MM_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11); - hws[IMX8MM_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11); + hws[IMX8MM_AUDIO_PLL1_OUT] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_AUDIO_PLL1_OUT); + hws[IMX8MM_AUDIO_PLL2_OUT] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_AUDIO_PLL2_OUT); + hws[IMX8MM_VIDEO_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_VIDEO_PLL_OUT); + hws[IMX8MM_DRAM_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_DRAM_PLL_OUT); + hws[IMX8MM_GPU_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_GPU_PLL_OUT); + hws[IMX8MM_VPU_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_VPU_PLL_OUT); + hws[IMX8MM_ARM_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_ARM_PLL_OUT); + hws[IMX8MM_SYS_PLL3_OUT] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL3_OUT); /* SYS PLL1 fixed output */ - hws[IMX8MM_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out", "sys_pll1", base + 0x94, 11); - - hws[IMX8MM_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20); - hws[IMX8MM_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10); - hws[IMX8MM_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8); - hws[IMX8MM_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6); - hws[IMX8MM_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5); - hws[IMX8MM_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4); - hws[IMX8MM_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3); - hws[IMX8MM_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2); - hws[IMX8MM_SYS_PLL1_800M] = imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1); + hws[IMX8MM_SYS_PLL1_OUT] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL1_OUT); + + hws[IMX8MM_SYS_PLL1_40M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL1_40M); + hws[IMX8MM_SYS_PLL1_80M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL1_80M); + hws[IMX8MM_SYS_PLL1_100M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL1_100M); + hws[IMX8MM_SYS_PLL1_133M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL1_133M); + hws[IMX8MM_SYS_PLL1_160M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL1_160M); + hws[IMX8MM_SYS_PLL1_200M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL1_200M); + hws[IMX8MM_SYS_PLL1_266M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL1_266M); + hws[IMX8MM_SYS_PLL1_400M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL1_400M); + hws[IMX8MM_SYS_PLL1_800M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL1_800M); /* SYS PLL2 fixed output */ - hws[IMX8MM_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2", base + 0x104, 11); - hws[IMX8MM_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20); - hws[IMX8MM_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10); - hws[IMX8MM_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8); - hws[IMX8MM_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6); - hws[IMX8MM_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5); - hws[IMX8MM_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4); - hws[IMX8MM_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3); - hws[IMX8MM_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2); - hws[IMX8MM_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1); - - hws[IMX8MM_CLK_CLKOUT1_SEL] = imx_clk_hw_mux2("clkout1_sel", base + 0x128, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels)); - hws[IMX8MM_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128, 0, 4); - hws[IMX8MM_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8); - hws[IMX8MM_CLK_CLKOUT2_SEL] = imx_clk_hw_mux2("clkout2_sel", base + 0x128, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels)); - hws[IMX8MM_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, 16, 4); - hws[IMX8MM_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24); - - np = dev->of_node; - base = devm_platform_ioremap_resource(pdev, 0); - if (WARN_ON(IS_ERR(base))) - return PTR_ERR(base); + hws[IMX8MM_SYS_PLL2_OUT] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL2_OUT); + + hws[IMX8MM_SYS_PLL2_50M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL2_50M); + hws[IMX8MM_SYS_PLL2_100M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL2_100M); + hws[IMX8MM_SYS_PLL2_125M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL2_125M); + hws[IMX8MM_SYS_PLL2_166M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL2_166M); + hws[IMX8MM_SYS_PLL2_200M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL2_200M); + hws[IMX8MM_SYS_PLL2_250M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL2_250M); + hws[IMX8MM_SYS_PLL2_333M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL2_333M); + hws[IMX8MM_SYS_PLL2_500M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL2_500M); + hws[IMX8MM_SYS_PLL2_1000M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL2_1000M); + + hws[IMX8MM_CLK_CLKOUT1_SEL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_CLK_CLKOUT1_SEL); + hws[IMX8MM_CLK_CLKOUT1_DIV] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_CLK_CLKOUT1_DIV); + hws[IMX8MM_CLK_CLKOUT1] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_CLK_CLKOUT1); + hws[IMX8MM_CLK_CLKOUT2_SEL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_CLK_CLKOUT2_SEL); + hws[IMX8MM_CLK_CLKOUT2_DIV] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_CLK_CLKOUT2_DIV); + hws[IMX8MM_CLK_CLKOUT2] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_CLK_CLKOUT2); /* Core Slice */ hws[IMX8MM_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mm_a53_sels, base + 0x8000); @@ -611,6 +596,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) imx_register_uart_clocks(); + dev_info(dev, "NXP i.MX8MM ccm clock driver probed\n"); return 0; unregister_hws: