[v4,14/14] mtd: decommission the NAND museum
diff mbox series

Message ID 20220722161009.2686504-15-dario.binacchi@amarulasolutions.com
State New
Headers show
Series
  • Port manufacturer specific initialization
Related show

Commit Message

Dario Binacchi July 22, 2022, 4:10 p.m. UTC 
From: Michael Trimarchi <michael@amarulasolutions.com>

Upstream linux commit f7025a43a9da26.

The MTD subsystem has its own small museum of ancient NANDs in a form of
the CONFIG_MTD_NAND_MUSEUM_IDS configuration option. The museum contains
stone age NANDs with 256 bytes pages, as well as iron age NANDs with 512
bytes per page and up to 8MiB page size.

It is with great sorrow that I inform you that the museum is being
decommissioned. The MTD subsystem is out of budget for Kconfig options and
already has too many of them, and there is a general kernel trend to
simplify the configuration menu.

We remove the stone age exhibits along with closing the museum

REMARK Don't apply this part from upstream:

Some of the iron age ones are transferred to the regular NAND depot.
Namely, only those which have unique device IDs are transferred, and the
ones which have conflicting device IDs are removed.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---

(no changes since v3)

Changes in v3:
- Use commit sha1 with 13 digits.
- Wrap commit description to a maximum of 75 chars.

Changes in v2:
- Use short-commit form.
- Remove linux info. Uboot seems that backport without add this
  extra information.

 drivers/mtd/nand/raw/nand_ids.c | 10 ----------
 1 file changed, 10 deletions(-)

Patch
diff mbox series 

diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c
index 7602dd30f169..4dece1b20676 100644
--- a/drivers/mtd/nand/raw/nand_ids.c
+++ b/drivers/mtd/nand/raw/nand_ids.c
@@ -24,16 +24,6 @@ 
  * extended chip ID.
  */
 struct nand_flash_dev nand_flash_ids[] = {
-#ifdef CONFIG_MTD_NAND_MUSEUM_IDS
-	LEGACY_ID_NAND("NAND 1MiB 5V 8-bit",	0x6e, 1, SZ_4K, SP_OPTIONS),
-	LEGACY_ID_NAND("NAND 2MiB 5V 8-bit",	0x64, 2, SZ_4K, SP_OPTIONS),
-	LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit",	0xe8, 1, SZ_4K, SP_OPTIONS),
-	LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit",	0xec, 1, SZ_4K, SP_OPTIONS),
-	LEGACY_ID_NAND("NAND 2MiB 3,3V 8-bit",	0xea, 2, SZ_4K, SP_OPTIONS),
-	LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit",	0xd5, 4, SZ_8K, SP_OPTIONS),
-
-	LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit",	0xe6, 8, SZ_8K, SP_OPTIONS),
-#endif
 	/*
 	 * Some incompatible NAND chips share device ID's and so must be
 	 * listed by full ID. We list them first so that we can easily identify