[RFC,8/8] arm64: dts: imx8mn: add imx8mn-clocks.dtsi
diff mbox series

Message ID 20221019172019.2303223-9-dario.binacchi@amarulasolutions.com
State New
Headers show
Series
  • clk: imx8mn: setup clocks by device tree
Related show

Commit Message

Dario Binacchi Oct. 19, 2022, 5:20 p.m. UTC 
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>

---

 .../boot/dts/freescale/imx8mn-clocks.dtsi     | 581 ++++++++++++++++++
 arch/arm64/boot/dts/freescale/imx8mn.dtsi     |  51 +-
 drivers/clk/imx/clk-imx8mn.c                  | 126 ++--
 3 files changed, 641 insertions(+), 117 deletions(-)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-clocks.dtsi

Patch
diff mbox series 

diff --git a/arch/arm64/boot/dts/freescale/imx8mn-clocks.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-clocks.dtsi
new file mode 100644
index 000000000000..70ca66f24325
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mn-clocks.dtsi
@@ -0,0 +1,581 @@ 
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Device Tree Source for imx8mn clock data
+ *
+ * Copyright (c) 2022 Amarula Solutions
+ *
+ * Dario Binacchi <dario.binacchi@amarulasolutions.com>
+ */
+
+/ {
+	osc_32k: clock-osc-32k {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "osc_32k";
+	};
+
+	osc_24m: clock-osc-24m {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24000000>;
+		clock-output-names = "osc_24m";
+	};
+
+	clk_ext1: clock-ext1 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <133000000>;
+		clock-output-names = "clk_ext1";
+	};
+
+	clk_ext2: clock-ext2 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <133000000>;
+		clock-output-names = "clk_ext2";
+	};
+
+	clk_ext3: clock-ext3 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <133000000>;
+		clock-output-names = "clk_ext3";
+	};
+
+	clk_ext4: clock-ext4 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency= <133000000>;
+		clock-output-names = "clk_ext4";
+	};
+
+	clk_dummy: clock-dummy {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+		clock-output-names = "dummy";
+	};
+};
+
+&anatop {
+	clk_sys_pll1: clock-sys-pll1 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <800000000>;
+		clock-output-names = "sys_pll1";
+	};
+
+	clk_sys_pll2: clock-sys-pll2 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1000000000>;
+		clock-output-names = "sys_pll2";
+	};
+
+	clk_sys_pll1_40m: clock-sys-pll1-40m {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_sys_pll1_out>;
+		clock-mult = <1>;
+		clock-div = <20>;
+		clock-output-names = "sys_pll1_40m";
+	};
+
+	clk_sys_pll1_80m: clock-sys-pll1-80m {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_sys_pll1_out>;
+		clock-mult = <1>;
+		clock-div = <10>;
+		clock-output-names = "sys_pll1_80m";
+	};
+
+	clk_sys_pll1_100m: clock-sys-pll1-100m {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_sys_pll1_out>;
+		clock-mult = <1>;
+		clock-div = <8>;
+		clock-output-names = "sys_pll1_100m";
+	};
+
+	clk_sys_pll1_133m: clock-sys-pll1-133m {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_sys_pll1_out>;
+		clock-mult = <1>;
+		clock-div = <6>;
+		clock-output-names = "sys_pll1_133m";
+	};
+
+	clk_sys_pll1_160m: clock-sys-pll1-160m {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_sys_pll1_out>;
+		clock-mult = <1>;
+		clock-div = <5>;
+	};
+
+	clk_sys_pll1_200m: clock-sys-pll1-200m {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_sys_pll1_out>;
+		clock-mult = <1>;
+		clock-div = <4>;
+		clock-output-names = "sys_pll1_200m";
+	};
+
+	clk_sys_pll1_266m: clock-sys-pll1-266m {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_sys_pll1_out>;
+		clock-mult = <1>;
+		clock-div = <3>;
+		clock-output-names = "sys_pll1_266m";
+	};
+
+	clk_sys_pll1_400m: clock-sys-pll1-400m {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_sys_pll1_out>;
+		clock-mult = <1>;
+		clock-div = <2>;
+		clock-output-names = "sys_pll1_400m";
+	};
+
+	clk_sys_pll1_800m: clock-sys-pll1-800m {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_sys_pll1_out>;
+		clock-mult = <1>;
+		clock-div = <1>;
+		clock-output-names = "sys_pll1_800m";
+	};
+
+	clk_sys_pll2_out: clock-sys-pll2-out@104 {
+		compatible = "fsl,imx8mn-gate-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_sys_pll2>;
+		fsl,regmap-offset = <0x104>;
+		fsl,bit-shift = <11>;
+		clock-output-names = "sys_pll2_out";
+	};
+
+	clk_sys_pll2_50m: clock-sys-pll2-50m {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_sys_pll2_out>;
+		clock-mult = <1>;
+		clock-div = <20>;
+		clock-output-names = "sys_pll2_50m";
+	};
+
+	clk_sys_pll2_100m: clock-sys-pll2-100m {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_sys_pll2_out>;
+		clock-mult = <1>;
+		clock-div = <10>;
+		clock-output-names = "sys_pll2_100m";
+	};
+
+	clk_sys_pll2_125m: clock-sys-pll2-125m {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_sys_pll2_out>;
+		clock-mult = <1>;
+		clock-div = <8>;
+		clock-output-names = "sys_pll2_125m";
+	};
+
+	clk_sys_pll2_166m: clock-sys-pll2-166m {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_sys_pll2_out>;
+		clock-mult = <1>;
+		clock-div = <6>;
+		clock-output-names = "sys_pll2_166m";
+	};
+
+	clk_sys_pll2_200m: clock-sys-pll2-200m {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_sys_pll2_out>;
+		clock-mult = <1>;
+		clock-div = <5>;
+		clock-output-names = "sys_pll2_200m";
+	};
+
+	clk_sys_pll2_250m: clock-sys-pll2-250m {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_sys_pll2_out>;
+		clock-mult = <1>;
+		clock-div = <4>;
+		clock-output-names = "sys_pll2_250m";
+	};
+
+	clk_sys_pll2_333m: clock-sys-pll2-333m {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_sys_pll2_out>;
+		clock-mult = <1>;
+		clock-div = <3>;
+		clock-output-names = "sys_pll2_333m";
+	};
+
+	clk_sys_pll2_500m: clock-sys-pll2-500m {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_sys_pll2_out>;
+		clock-mult = <1>;
+		clock-div = <2>;
+		clock-output-names = "sys_pll2_500m";
+	};
+
+	clk_sys_pll2_1000m: clock-sys-pll2-1000m {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_sys_pll2_out>;
+		clock-mult = <1>;
+		clock-div = <1>;
+		clock-output-names = "sys_pll2_1000m";
+	};
+
+	clk_audio_pll1_ref_sel: clock-audio-pll1-ref-sel@0 {
+		compatible = "fsl,imx8mn-mux-clock";
+		#clock-cells = <0>;
+		clocks = <&osc_24m>, <&clk_dummy>, <&clk_dummy>, <&clk_dummy>;
+		fsl,regmap-offset = <0x0>;
+		fsl,bit-shift = <0>;
+		clock-output-names = "audio_pll1_ref_sel";
+	};
+
+	clk_audio_pll1: clock-audio-pll1@0 {
+		compatible = "fsl,pll14xx-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_audio_pll1_ref_sel>;
+		fsl,regmap-offset = <0x0>;
+		fsl,type = "1443x";
+		clock-output-names = "audio_pll1";
+	};
+
+	clk_audio_pll1_bypass: clock-audio-pll1-bypass@0 {
+		compatible = "fsl,imx8mn-mux-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_audio_pll1>, <&clk_audio_pll1_ref_sel>;
+		fsl,regmap-offset = <0x0>;
+		fsl,bit-shift = <16>;
+		fsl,set-rate-parent;
+		clock-output-names = "audio_pll1_bypass";
+	};
+
+	clk_audio_pll1_out: clock-audio-pll1-out@0 {
+		compatible = "fsl,imx8mn-gate-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_audio_pll1_bypass>;
+		fsl,regmap-offset = <0x0>;
+		fsl,bit-shift = <13>;
+		clock-output-names = "audio_pll1_out";
+	};
+
+	clk_audio_pll2_ref_sel: clock-audio-pll2-ref-sel@14 {
+		compatible = "fsl,imx8mn-mux-clock";
+		#clock-cells = <0>;
+		clocks = <&osc_24m>, <&clk_dummy>, <&clk_dummy>, <&clk_dummy>;
+		fsl,regmap-offset = <0x14>;
+		fsl,bit-shift = <0>;
+		clock-output-names = "audio_pll2_ref_sel";
+	};
+
+	clk_audio_pll2: clock-audio-pll2@14 {
+		compatible = "fsl,pll14xx-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_audio_pll2_ref_sel>;
+		fsl,regmap-offset = <0x14>;
+		fsl,type = "1443x";
+		clock-output-names = "audio_pll2";
+	};
+
+	clk_audio_pll2_bypass: clock-audio-pll2-bypass@14 {
+		compatible = "fsl,imx8mn-mux-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_audio_pll2>, <&clk_audio_pll2_ref_sel>;
+		fsl,regmap-offset = <0x14>;
+		fsl,bit-shift = <16>;
+		fsl,set-rate-parent;
+		clock-output-names = "audio_pll2_bypass";
+	};
+
+	clk_audio_pll2_out: clock-audio-pll2-out@14 {
+		compatible = "fsl,imx8mn-gate-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_audio_pll2_bypass>;
+		fsl,regmap-offset = <0x14>;
+		fsl,bit-shift = <13>;
+		clock-output-names = "audio_pll2_out";
+	};
+
+	clk_video_pll1_ref_sel: clock-video-pll1-ref-sel@28 {
+		compatible = "fsl,imx8mn-mux-clock";
+		#clock-cells = <0>;
+		clocks = <&osc_24m>, <&clk_dummy>, <&clk_dummy>, <&clk_dummy>;
+		fsl,regmap-offset = <0x28>;
+		fsl,bit-shift = <0>;
+		clock-output-names = "video_pll1_ref_sel";
+	};
+
+	clk_video_pll1: clock-video-pll1@28 {
+		compatible = "fsl,pll14xx-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_video_pll1_ref_sel>;
+		fsl,regmap-offset = <0x28>;
+		fsl,type = "1443x";
+		clock-output-names = "video_pll1";
+	};
+
+	clk_video_pll1_bypass: clock-video-pll1-bypass@28 {
+		compatible = "fsl,imx8mn-mux-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_video_pll1>, <&clk_video_pll1_ref_sel>;
+		fsl,regmap-offset = <0x28>;
+		fsl,bit-shift = <16>;
+		fsl,set-rate-parent;
+		clock-output-names = "video_pll1_bypass";
+	};
+
+	clk_video_pll1_out: clock-video-pll1-out@28 {
+		compatible = "fsl,imx8mn-gate-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_video_pll1_bypass>;
+		fsl,regmap-offset = <0x28>;
+		fsl,bit-shift = <13>;
+		clock-output-names = "video_pll1_out";
+	};
+
+	clk_dram_pll_ref_sel: clock-dram-pll-ref-sel@50 {
+		compatible = "fsl,imx8mn-mux-clock";
+		#clock-cells = <0>;
+		clocks = <&osc_24m>, <&clk_dummy>, <&clk_dummy>, <&clk_dummy>;
+		fsl,regmap-offset = <0x50>;
+		fsl,bit-shift = <0>;
+		clock-output-names = "dram_pll_ref_sel";
+	};
+
+	clk_dram_pll: clock-dram-pll@50 {
+		compatible = "fsl,pll14xx-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_dram_pll_ref_sel>;
+		fsl,regmap-offset = <0x50>;
+		fsl,get-rate-nocache;
+		fsl,type = "1443x";
+		clock-output-names = "dram_pll";
+	};
+
+	clk_dram_pll_bypass: clock-dram-pll-bypass@50 {
+		compatible = "fsl,imx8mn-mux-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_dram_pll>, <&clk_dram_pll_ref_sel>;
+		fsl,regmap-offset = <0x50>;
+		fsl,bit-shift = <16>;
+		fsl,set-rate-parent;
+		clock-output-names = "dram_pll_bypass";
+	};
+
+	clk_dram_pll_out: clock-dram-pll-out@50 {
+		compatible = "fsl,imx8mn-gate-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_dram_pll_bypass>;
+		fsl,regmap-offset = <0x50>;
+		fsl,bit-shift = <13>;
+		clock-output-names = "dram_pll_out";
+	};
+
+	clk_gpu_pll_ref_sel: clock-gpu-pll-ref-sel@64 {
+		compatible = "fsl,imx8mn-mux-clock";
+		#clock-cells = <0>;
+		clocks = <&osc_24m>, <&clk_dummy>, <&clk_dummy>, <&clk_dummy>;
+		fsl,regmap-offset = <0x64>;
+		fsl,bit-shift = <0>;
+		clock-output-names = "gpu_pll_ref_sel";
+	};
+
+	clk_gpu_pll: clock-gpu-pll@64 {
+		compatible = "fsl,pll14xx-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_gpu_pll_ref_sel>;
+		fsl,regmap-offset = <0x64>;
+		fsl,type = "1416x";
+		clock-output-names = "gpu_pll";
+	};
+
+	clk_gpu_pll_bypass: clock-gpu-pll-bypass@64 {
+		compatible = "fsl,imx8mn-mux-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_gpu_pll>, <&clk_gpu_pll_ref_sel>;
+		fsl,regmap-offset = <0x64>;
+		fsl,bit-shift = <28>;
+		fsl,set-rate-parent;
+		clock-output-names = "gpu_pll_bypass";
+	};
+
+	clk_gpu_pll_out: clock-gpu-pll-out@64 {
+		compatible = "fsl,imx8mn-gate-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_gpu_pll_bypass>;
+		fsl,regmap-offset = <0x64>;
+		fsl,bit-shift = <11>;
+		clock-output-names = "gpu_pll_out";
+	};
+
+	clk_vpu_pll_ref_sel: clock-vpu-pll-ref-sel@74 {
+		compatible = "fsl,imx8mn-mux-clock";
+		#clock-cells = <0>;
+		clocks = <&osc_24m>, <&clk_dummy>, <&clk_dummy>, <&clk_dummy>;
+		fsl,regmap-offset = <0x74>;
+		fsl,bit-shift = <0>;
+		clock-output-names = "vpu_pll_ref_sel";
+	};
+
+	clk_vpu_pll: clock-vpu-pll@74 {
+		compatible = "fsl,pll14xx-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_vpu_pll_ref_sel>;
+		fsl,regmap-offset = <0x74>;
+		fsl,type = "1416x";
+		clock-output-names = "vpu_pll";
+	};
+
+	clk_vpu_pll_bypass: clock-vpu-pll-bypass@74 {
+		compatible = "fsl,imx8mn-mux-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_vpu_pll>, <&clk_vpu_pll_ref_sel>;
+		fsl,regmap-offset = <0x74>;
+		fsl,bit-shift = <28>;
+		fsl,set-rate-parent;
+		clock-output-names = "vpu_pll_bypass";
+	};
+
+	clk_vpu_pll_out: clock-vpu-pll-out@74 {
+		compatible = "fsl,imx8mn-gate-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_vpu_pll_bypass>;
+		fsl,regmap-offset = <0x74>;
+		fsl,bit-shift = <11>;
+		clock-output-names = "vpu_pll_out";
+	};
+
+	clk_arm_pll_ref_sel: clock-arm-pll-ref-sel@84 {
+		compatible = "fsl,imx8mn-mux-clock";
+		#clock-cells = <0>;
+		clocks = <&osc_24m>, <&clk_dummy>, <&clk_dummy>, <&clk_dummy>;
+		fsl,regmap-offset = <0x84>;
+		fsl,bit-shift = <0>;
+		clock-output-names = "arm_pll_ref_sel";
+	};
+
+	clk_arm_pll: clock-arm-pll@84 {
+		compatible = "fsl,pll14xx-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_arm_pll_ref_sel>;
+		fsl,regmap-offset = <0x84>;
+		fsl,type = "1416x";
+		clock-output-names = "arm_pll";
+	};
+
+	clk_arm_pll_bypass: clock-arm-pll-bypass@84 {
+		compatible = "fsl,imx8mn-mux-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_arm_pll>, <&clk_arm_pll_ref_sel>;
+		fsl,regmap-offset = <0x84>;
+		fsl,bit-shift = <28>;
+		fsl,set-rate-parent;
+		clock-output-names = "arm_pll_bypass";
+	};
+
+	clk_arm_pll_out: clock-arm-pll-out@84 {
+		compatible = "fsl,imx8mn-gate-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_arm_pll_bypass>;
+		fsl,regmap-offset = <0x84>;
+		fsl,bit-shift = <11>;
+		clock-output-names = "arm_pll_out";
+	};
+
+	clk_sys_pll1_out: clock-sys-pll1-out@94 {
+		compatible = "fsl,imx8mn-gate-clock";
+		clocks = <&clk_sys_pll1>;
+		fsl,regmap-offset = <0x094>;
+		fsl,bit-shift = <11>;
+		clock-output-names = "sys_pll1_out";
+		#clock-cells = <0>;
+	};
+
+	clk_sys_pll3_ref_sel: clock-sys-pll3-ref-sel@114 {
+		compatible = "fsl,imx8mn-mux-clock";
+		#clock-cells = <0>;
+		clocks = <&osc_24m>, <&clk_dummy>, <&clk_dummy>, <&clk_dummy>;
+		fsl,regmap-offset = <0x114>;
+		fsl,bit-shift = <0>;
+		clock-output-names = "sys_pll3_ref_sel";
+	};
+
+	clk_sys_pll3: clock-sys-pll3@114 {
+		compatible = "fsl,pll14xx-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_sys_pll3_ref_sel>;
+		fsl,regmap-offset = <0x114>;
+		fsl,type = "1416x";
+		clock-output-names = "sys_pll3";
+	};
+
+	clk_sys_pll3_bypass: clock-sys-pll3-bypass@114 {
+		compatible = "fsl,imx8mn-mux-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_sys_pll3>, <&clk_sys_pll3_ref_sel>;
+		fsl,regmap-offset = <0x114>;
+		fsl,bit-shift = <28>;
+		fsl,set-rate-parent;
+		clock-output-names = "sys_pll3_bypass";
+	};
+
+	clk_sys_pll3_out: clock-sys-pll3-out@114 {
+		compatible = "fsl,imx8mn-gate-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_sys_pll3_bypass>;
+		fsl,regmap-offset = <0x114>;
+		fsl,bit-shift = <11>;
+		clock-output-names = "sys_pll3_out";
+	};
+
+	clk_out1_sel: clock-out1-sel@128 {
+		compatible = "fsl,imx8mn-mux-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_audio_pll1_out>, <&clk_audio_pll2_out>,
+			 <&clk_video_pll1_out>, <&clk_dummy>, <&clk_dummy>,
+			 <&clk_gpu_pll_out>, <&clk_dummy>, <&clk_arm_pll_out>,
+			 <&clk_sys_pll1>, <&clk_sys_pll2>, <&clk_sys_pll3>,
+			 <&clk_dummy>, <&clk_dummy>, <&osc_24m>, <&clk_dummy>,
+			 <&osc_32k>;
+		fsl,regmap-offset = <0x128>;
+		fsl,bit-shift = <4>;
+		fsl,ops-parent-enable;
+		clock-output-names = "clkout1_sel";
+	};
+
+	clk_out2_sel: clock-out2-sel@128 {
+		compatible = "fsl,imx8mn-mux-clock";
+		#clock-cells = <0>;
+		clocks = <&clk_audio_pll1_out>, <&clk_audio_pll2_out>,
+			 <&clk_video_pll1_out>, <&clk_dummy>, <&clk_dummy>,
+			 <&clk_gpu_pll_out>, <&clk_dummy>, <&clk_arm_pll_out>,
+			 <&clk_sys_pll1>, <&clk_sys_pll2>, <&clk_sys_pll3>,
+			 <&clk_dummy>, <&clk_dummy>, <&osc_24m>, <&clk_dummy>,
+			 <&osc_32k>;
+		fsl,regmap-offset = <0x128>;
+		fsl,bit-shift = <20>;
+		fsl,ops-parent-enable;
+		clock-output-names = "clkout2_sel";
+	};
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 089fa3c4a526..ab3fed912528 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -174,55 +174,6 @@  opp-1500000000 {
 		};
 	};
 
-	osc_32k: clock-osc-32k {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <32768>;
-		clock-output-names = "osc_32k";
-	};
-
-	osc_24m: clock-osc-24m {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <24000000>;
-		clock-output-names = "osc_24m";
-	};
-
-	clk_ext1: clock-ext1 {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <133000000>;
-		clock-output-names = "clk_ext1";
-	};
-
-	clk_ext2: clock-ext2 {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <133000000>;
-		clock-output-names = "clk_ext2";
-	};
-
-	clk_ext3: clock-ext3 {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <133000000>;
-		clock-output-names = "clk_ext3";
-	};
-
-	clk_ext4: clock-ext4 {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency= <133000000>;
-		clock-output-names = "clk_ext4";
-	};
-
-	clk_dummy: clock-dummy {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <0>;
-		clock-output-names = "dummy";
-	};
-
 	pmu {
 		compatible = "arm,cortex-a53-pmu";
 		interrupts = <GIC_PPI 7
@@ -1184,3 +1135,5 @@  usbphynop1: usbphynop1 {
 		clock-names = "main_clk";
 	};
 };
+
+#include "imx8mn-clocks.dtsi"
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index 6bee953a60ed..b3593c5e208d 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -24,16 +24,6 @@  static u32 share_count_disp;
 static u32 share_count_pdm;
 static u32 share_count_nand;
 
-static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
-static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
-static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
-static const char * const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", };
-static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
-static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
-static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
-static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
-static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
-
 static const char * const imx8mn_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m",
 					       "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
 					       "audio_pll1_out", "sys_pll3_out", };
@@ -323,74 +313,74 @@  static int imx8mn_clocks_probe(struct platform_device *pdev)
 		goto unregister_hws;
 	}
 
-	hws[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
-	hws[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
-	hws[IMX8MN_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
-	hws[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
-	hws[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
-	hws[IMX8MN_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
-	hws[IMX8MN_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
-	hws[IMX8MN_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
-
-	hws[IMX8MN_AUDIO_PLL1] = imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx_1443x_pll);
-	hws[IMX8MN_AUDIO_PLL2] = imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx_1443x_pll);
-	hws[IMX8MN_VIDEO_PLL1] = imx_clk_hw_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx_1443x_pll);
-	hws[IMX8MN_DRAM_PLL] = imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_dram_pll);
-	hws[IMX8MN_GPU_PLL] = imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx_1416x_pll);
-	hws[IMX8MN_VPU_PLL] = imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx_1416x_pll);
-	hws[IMX8MN_ARM_PLL] = imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx_1416x_pll);
-	hws[IMX8MN_SYS_PLL1] = imx_clk_hw_fixed("sys_pll1", 800000000);
-	hws[IMX8MN_SYS_PLL2] = imx_clk_hw_fixed("sys_pll2", 1000000000);
-	hws[IMX8MN_SYS_PLL3] = imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx_1416x_pll);
+	hws[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_get_clk_hw_from_dt(np, "clock-audio-pll1-ref-sel");
+	hws[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_get_clk_hw_from_dt(np, "clock-audio-pll2-ref-sel");
+	hws[IMX8MN_VIDEO_PLL1_REF_SEL] = imx_get_clk_hw_from_dt(np, "clock-video-pll1-ref-sel");
+	hws[IMX8MN_DRAM_PLL_REF_SEL] = imx_get_clk_hw_from_dt(np, "clock-dram-pll-ref-sel");
+	hws[IMX8MN_GPU_PLL_REF_SEL] = imx_get_clk_hw_from_dt(np, "clock-gpu-pll-ref-sel");
+	hws[IMX8MN_VPU_PLL_REF_SEL] = imx_get_clk_hw_from_dt(np, "clock-vpu-pll-ref-sel");
+	hws[IMX8MN_ARM_PLL_REF_SEL] = imx_get_clk_hw_from_dt(np, "clock-arm-pll-ref-sel");
+	hws[IMX8MN_SYS_PLL3_REF_SEL] = imx_get_clk_hw_from_dt(np, "clock-sys-pll3-ref-sel");
+
+	hws[IMX8MN_AUDIO_PLL1] = imx_get_clk_hw_from_dt(np, "clock-audio-pll1");
+	hws[IMX8MN_AUDIO_PLL2] = imx_get_clk_hw_from_dt(np, "clock-audio-pll2");
+	hws[IMX8MN_VIDEO_PLL1] = imx_get_clk_hw_from_dt(np, "clock-video-pll1");
+	hws[IMX8MN_DRAM_PLL] = imx_get_clk_hw_from_dt(np, "clock-dram-pll");
+	hws[IMX8MN_GPU_PLL] = imx_get_clk_hw_from_dt(np, "clock-gpu-pll");
+	hws[IMX8MN_VPU_PLL] = imx_get_clk_hw_from_dt(np, "clock-vpu-pll");
+	hws[IMX8MN_ARM_PLL] = imx_get_clk_hw_from_dt(np, "clock-arm-pll");
+	hws[IMX8MN_SYS_PLL1] = imx_get_clk_hw_from_dt(np, "clock-sys-pll1");
+	hws[IMX8MN_SYS_PLL2] = imx_get_clk_hw_from_dt(np, "clock-sys-pll2");
+	hws[IMX8MN_SYS_PLL3] = imx_get_clk_hw_from_dt(np, "clock-sys-pll3");
 
 	/* PLL bypass out */
-	hws[IMX8MN_AUDIO_PLL1_BYPASS] = imx_clk_hw_mux_flags("audio_pll1_bypass", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT);
-	hws[IMX8MN_AUDIO_PLL2_BYPASS] = imx_clk_hw_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT);
-	hws[IMX8MN_VIDEO_PLL1_BYPASS] = imx_clk_hw_mux_flags("video_pll1_bypass", base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT);
-	hws[IMX8MN_DRAM_PLL_BYPASS] = imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT);
-	hws[IMX8MN_GPU_PLL_BYPASS] = imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
-	hws[IMX8MN_VPU_PLL_BYPASS] = imx_clk_hw_mux_flags("vpu_pll_bypass", base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
-	hws[IMX8MN_ARM_PLL_BYPASS] = imx_clk_hw_mux_flags("arm_pll_bypass", base + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT);
-	hws[IMX8MN_SYS_PLL3_BYPASS] = imx_clk_hw_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT);
+	hws[IMX8MN_AUDIO_PLL1_BYPASS] = imx_get_clk_hw_from_dt(np, "clock-audio-pll1-bypass");
+	hws[IMX8MN_AUDIO_PLL2_BYPASS] = imx_get_clk_hw_from_dt(np, "clock-audio-pll2-bypass");
+	hws[IMX8MN_VIDEO_PLL1_BYPASS] = imx_get_clk_hw_from_dt(np, "clock-video-pll1-bypass");
+	hws[IMX8MN_DRAM_PLL_BYPASS] = imx_get_clk_hw_from_dt(np, "clock-dram-pll-bypass");
+	hws[IMX8MN_GPU_PLL_BYPASS] = imx_get_clk_hw_from_dt(np, "clock-gpu-pll-bypass");
+	hws[IMX8MN_VPU_PLL_BYPASS] = imx_get_clk_hw_from_dt(np, "clock-vpu-pll-bypass");
+	hws[IMX8MN_ARM_PLL_BYPASS] = imx_get_clk_hw_from_dt(np, "clock-arm-pll-bypass");
+	hws[IMX8MN_SYS_PLL3_BYPASS] = imx_get_clk_hw_from_dt(np, "clock-sys-pll3-bypass");
 
 	/* PLL out gate */
-	hws[IMX8MN_AUDIO_PLL1_OUT] = imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", base, 13);
-	hws[IMX8MN_AUDIO_PLL2_OUT] = imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x14, 13);
-	hws[IMX8MN_VIDEO_PLL1_OUT] = imx_clk_hw_gate("video_pll1_out", "video_pll1_bypass", base + 0x28, 13);
-	hws[IMX8MN_DRAM_PLL_OUT] = imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13);
-	hws[IMX8MN_GPU_PLL_OUT] = imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 11);
-	hws[IMX8MN_VPU_PLL_OUT] = imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x74, 11);
-	hws[IMX8MN_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11);
-	hws[IMX8MN_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11);
+	hws[IMX8MN_AUDIO_PLL1_OUT] = imx_get_clk_hw_from_dt(np, "clock-audio-pll1-out");
+	hws[IMX8MN_AUDIO_PLL2_OUT] = imx_get_clk_hw_from_dt(np, "clock-audio-pll2-out");
+	hws[IMX8MN_VIDEO_PLL1_OUT] = imx_get_clk_hw_from_dt(np, "clock-video-pll1-out");
+	hws[IMX8MN_DRAM_PLL_OUT] = imx_get_clk_hw_from_dt(np, "clock-dram-pll-out");
+	hws[IMX8MN_GPU_PLL_OUT] = imx_get_clk_hw_from_dt(np, "clock-gpu-pll-out");
+	hws[IMX8MN_VPU_PLL_OUT] = imx_get_clk_hw_from_dt(np, "clock-vpu-pll-out");
+	hws[IMX8MN_ARM_PLL_OUT] = imx_get_clk_hw_from_dt(np, "clock-arm-pll-out");
+	hws[IMX8MN_SYS_PLL3_OUT] = imx_get_clk_hw_from_dt(np, "clock-sys-pll3-out");
 
 	/* SYS PLL1 fixed output */
-	hws[IMX8MN_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out", "sys_pll1", base + 0x94, 11);
-	hws[IMX8MN_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20);
-	hws[IMX8MN_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10);
-	hws[IMX8MN_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8);
-	hws[IMX8MN_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6);
-	hws[IMX8MN_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5);
-	hws[IMX8MN_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4);
-	hws[IMX8MN_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3);
-	hws[IMX8MN_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2);
-	hws[IMX8MN_SYS_PLL1_800M] = imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1);
+	hws[IMX8MN_SYS_PLL1_OUT] = imx_get_clk_hw_from_dt(np, "clock-sys-pll1-out");
+	hws[IMX8MN_SYS_PLL1_40M] = imx_get_clk_hw_from_dt(np, "clock-sys-pll1-40m");
+	hws[IMX8MN_SYS_PLL1_80M] = imx_get_clk_hw_from_dt(np, "clock-sys-pll1-80m");
+	hws[IMX8MN_SYS_PLL1_100M] = imx_get_clk_hw_from_dt(np, "clock-sys-pll1-100m");
+	hws[IMX8MN_SYS_PLL1_133M] = imx_get_clk_hw_from_dt(np, "clock-sys-pll1-133m");
+	hws[IMX8MN_SYS_PLL1_160M] = imx_get_clk_hw_from_dt(np, "clock-sys-pll1-160m");
+	hws[IMX8MN_SYS_PLL1_200M] = imx_get_clk_hw_from_dt(np, "clock-sys-pll1-200m");
+	hws[IMX8MN_SYS_PLL1_266M] = imx_get_clk_hw_from_dt(np, "clock-sys-pll1-266m");
+	hws[IMX8MN_SYS_PLL1_400M] = imx_get_clk_hw_from_dt(np, "clock-sys-pll1-400m");
+	hws[IMX8MN_SYS_PLL1_800M] = imx_get_clk_hw_from_dt(np, "clock-sys-pll1-800m");
 
 	/* SYS PLL2 fixed output */
-	hws[IMX8MN_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2", base + 0x104, 11);
-	hws[IMX8MN_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20);
-	hws[IMX8MN_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10);
-	hws[IMX8MN_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8);
-	hws[IMX8MN_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6);
-	hws[IMX8MN_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5);
-	hws[IMX8MN_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4);
-	hws[IMX8MN_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3);
-	hws[IMX8MN_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2);
-	hws[IMX8MN_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
-
-	hws[IMX8MN_CLK_CLKOUT1_SEL] = imx_clk_hw_mux2("clkout1_sel", base + 0x128, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
+	hws[IMX8MN_SYS_PLL2_OUT] = imx_get_clk_hw_from_dt(np, "clock-sys-pll2-out");
+	hws[IMX8MN_SYS_PLL2_50M] = imx_get_clk_hw_from_dt(np, "clock-sys-pll2-50m");
+	hws[IMX8MN_SYS_PLL2_100M] = imx_get_clk_hw_from_dt(np, "clock-sys-pll2-100m");
+	hws[IMX8MN_SYS_PLL2_125M] = imx_get_clk_hw_from_dt(np, "clock-sys-pll2-125m");
+	hws[IMX8MN_SYS_PLL2_166M] = imx_get_clk_hw_from_dt(np, "clock-sys-pll2-166m");
+	hws[IMX8MN_SYS_PLL2_200M] = imx_get_clk_hw_from_dt(np, "clock-sys-pll2-200m");
+	hws[IMX8MN_SYS_PLL2_250M] = imx_get_clk_hw_from_dt(np, "clock-sys-pll2-250m");
+	hws[IMX8MN_SYS_PLL2_333M] = imx_get_clk_hw_from_dt(np, "clock-sys-pll2-333m");
+	hws[IMX8MN_SYS_PLL2_500M] = imx_get_clk_hw_from_dt(np, "clock-sys-pll2-500m");
+	hws[IMX8MN_SYS_PLL2_1000M] = imx_get_clk_hw_from_dt(np, "clock-sys-pll2-1000m");
+
+	hws[IMX8MN_CLK_CLKOUT1_SEL] = imx_get_clk_hw_from_dt(np, "clock-out1-sel");
 	hws[IMX8MN_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128, 0, 4);
 	hws[IMX8MN_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8);
-	hws[IMX8MN_CLK_CLKOUT2_SEL] = imx_clk_hw_mux2("clkout2_sel", base + 0x128, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
+	hws[IMX8MN_CLK_CLKOUT2_SEL] = imx_get_clk_hw_from_dt(np, "clock-out2-sel");
 	hws[IMX8MN_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, 16, 4);
 	hws[IMX8MN_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24);