| Message ID | 20221117113637.1978703-5-dario.binacchi@amarulasolutions.com |
|---|---|
| State | New |
| Headers | show |
| Series |
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| Related | show |
On 22-11-17 12:36:36, Dario Binacchi wrote: > According to the "Clock Root" table of the reference manual (document > IMX8MNRM Rev 2, 07/2022): > > Clock Root offset Source Select (CCM_TARGET_ROOTn[MUX]) > ... ... ... > SAI2_CLK_ROOT 0xA600 000 - 24M_REF_CLK > 001 - AUDIO_PLL1_CLK > 010 - AUDIO_PLL2_CLK > 011 - VIDEO_PLL_CLK > 100 - SYSTEM_PLL1_DIV6 > 110 - EXT_CLK_2 > 111 - EXT_CLK_3 > ... ... ... > > while the imx8mn_sai2_sels list contained clk_ext3 and clk_ext4 for > source select bits 110b and 111b. > > Fixes: 96d6392b54dbb ("clk: imx: Add support for i.MX8MN clock driver") > Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> > --- > > (no changes since v1) > > drivers/clk/imx/clk-imx8mn.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c > index b80af5d1ef46..37128c35198d 100644 > --- a/drivers/clk/imx/clk-imx8mn.c > +++ b/drivers/clk/imx/clk-imx8mn.c > @@ -109,7 +109,7 @@ static const char * const imx8mn_disp_pixel_sels[] = {"osc_24m", "video_pll_out" > > static const char * const imx8mn_sai2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", > "video_pll_out", "sys_pll1_133m", "dummy", > - "clk_ext3", "clk_ext4", }; > + "clk_ext2", "clk_ext3", }; > > static const char * const imx8mn_sai3_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", > "video_pll_out", "sys_pll1_133m", "dummy", > -- > 2.32.0 >
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index b80af5d1ef46..37128c35198d 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -109,7 +109,7 @@ static const char * const imx8mn_disp_pixel_sels[] = {"osc_24m", "video_pll_out" static const char * const imx8mn_sai2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll_out", "sys_pll1_133m", "dummy", - "clk_ext3", "clk_ext4", }; + "clk_ext2", "clk_ext3", }; static const char * const imx8mn_sai3_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll_out", "sys_pll1_133m", "dummy",
According to the "Clock Root" table of the reference manual (document IMX8MNRM Rev 2, 07/2022): Clock Root offset Source Select (CCM_TARGET_ROOTn[MUX]) ... ... ... SAI2_CLK_ROOT 0xA600 000 - 24M_REF_CLK 001 - AUDIO_PLL1_CLK 010 - AUDIO_PLL2_CLK 011 - VIDEO_PLL_CLK 100 - SYSTEM_PLL1_DIV6 110 - EXT_CLK_2 111 - EXT_CLK_3 ... ... ... while the imx8mn_sai2_sels list contained clk_ext3 and clk_ext4 for source select bits 110b and 111b. Fixes: 96d6392b54dbb ("clk: imx: Add support for i.MX8MN clock driver") Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> --- (no changes since v1) drivers/clk/imx/clk-imx8mn.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)