@@ -7,6 +7,8 @@
#include <linux/errno.h>
#include <linux/export.h>
#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
#include <linux/slab.h>
#include "clk.h"
@@ -25,6 +27,9 @@
#define PCG_CGC_SHIFT 28
+#undef pr_fmt
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
@@ -250,3 +255,82 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name,
return ERR_CAST(hw);
}
EXPORT_SYMBOL_GPL(__imx8m_clk_hw_composite);
+
+static void __init _of_imx_composite_clk_setup(struct device_node *node,
+ u32 type)
+{
+ void __iomem *reg;
+ struct clk_hw *hw;
+ const char *name = node->name;
+ unsigned int num_parents;
+ const char **parent_names;
+ unsigned long flags = IMX_COMPOSITE_CLK_FLAGS_DEFAULT;
+
+ reg = of_iomap(node, 0);
+ if (IS_ERR(reg)) {
+ pr_err("failed to get reg address for %pOFn\n", node);
+ return;
+ }
+
+ num_parents = of_clk_get_parent_count(node);
+ if (num_parents < 2) {
+ pr_err("%pOFn must have parents\n", node);
+ return;
+ }
+
+ parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
+ if (!parent_names)
+ return;
+
+ of_clk_parent_fill(node, parent_names, num_parents);
+ of_property_read_string(node, "clock-output-names", &name);
+
+ if (of_property_read_bool(node, "fsl,get-rate-nocache"))
+ flags |= CLK_GET_RATE_NOCACHE;
+
+ if (of_property_read_bool(node, "fsl,is-critical"))
+ flags |= CLK_IS_CRITICAL;
+
+ hw = __imx8m_clk_hw_composite(name, parent_names, num_parents, reg,
+ type, flags);
+ if (!IS_ERR(hw))
+ of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
+
+ kfree(parent_names);
+}
+
+/**
+ * of_imx_composite_clk_setup() - Setup function for imx composite clock
+ * @node: device node for the clock
+ */
+static void __init of_imx_composite_clk_setup(struct device_node *node)
+{
+ _of_imx_composite_clk_setup(node, IMX_COMPOSITE_CORE);
+}
+CLK_OF_DECLARE(fsl_composite_8m_clk, "fsl,imx8m-composite-clock",
+ of_imx_composite_clk_setup);
+
+/**
+ * of_imx_composite_bus_clk_setup() - Setup function for imx composite clock
+ * @node: device node for the clock
+ */
+static void __init of_imx_composite_bus_clk_setup(struct device_node *node)
+{
+ _of_imx_composite_clk_setup(node, IMX_COMPOSITE_BUS);
+}
+CLK_OF_DECLARE(fsl_composite_bus_8m_clk, "fsl,imx8m-composite-bus-clock",
+ of_imx_composite_bus_clk_setup);
+
+/**
+ * of_imx_composite_fw_managed_clk_setup() - Setup function for imx
+ * composite fw managed clock
+ * @node: device node for the clock
+ */
+static void __init
+of_imx_composite_fw_managed_clk_setup(struct device_node *node)
+{
+ _of_imx_composite_clk_setup(node, IMX_COMPOSITE_FW_MANAGED);
+}
+CLK_OF_DECLARE(fsl_composite_fw_managed_8m_clk,
+ "fsl,imx8m-composite-fw-managed-clock",
+ of_imx_composite_fw_managed_clk_setup);
The patch, backwards compatible, extends the driver to initialize the clock directly from the device tree. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reported-by: kernel test robot <lkp@intel.com> --- Changes in v2: - Fix compiler warnings reported by kernel test robot. drivers/clk/imx/clk-composite-8m.c | 84 ++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+)