[1/2] clk: stm32f: fix setting of division factor for LCD_CLK

Message ID 20231111104625.137511-1-dario.binacchi@amarulasolutions.com
State New
Headers show
Series
  • [1/2] clk: stm32f: fix setting of division factor for LCD_CLK
Related show

Commit Message

Dario Binacchi Nov. 11, 2023, 10:46 a.m. UTC
The value to be written to the register must be appropriately shifted,
as is correctly done in other parts of the code.

Fixes: 5e993508cb25 ("clk: clk_stm32f: Add set_rate for LTDC clock")
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---

 drivers/clk/stm32/clk-stm32f.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Comments

Patrice CHOTARD Nov. 13, 2023, 8:59 a.m. UTC | #1
On 11/11/23 11:46, Dario Binacchi wrote:
> The value to be written to the register must be appropriately shifted,
> as is correctly done in other parts of the code.
> 
> Fixes: 5e993508cb25 ("clk: clk_stm32f: Add set_rate for LTDC clock")
> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
> ---
> 
>  drivers/clk/stm32/clk-stm32f.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/stm32/clk-stm32f.c b/drivers/clk/stm32/clk-stm32f.c
> index ed7660196ef0..4c1864193357 100644
> --- a/drivers/clk/stm32/clk-stm32f.c
> +++ b/drivers/clk/stm32/clk-stm32f.c
> @@ -530,7 +530,8 @@ static ulong stm32_set_rate(struct clk *clk, ulong rate)
>  			/* set pll_saidivr with found value */
>  			clrsetbits_le32(&regs->dckcfgr,
>  					RCC_DCKCFGR_PLLSAIDIVR_MASK,
> -					pllsaidivr_table[i]);
> +					pllsaidivr_table[i] <<
> +					RCC_DCKCFGR_PLLSAIDIVR_SHIFT);
>  			return rate;
>  		}
>  

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>

Thanks 
Patrice

Patch

diff --git a/drivers/clk/stm32/clk-stm32f.c b/drivers/clk/stm32/clk-stm32f.c
index ed7660196ef0..4c1864193357 100644
--- a/drivers/clk/stm32/clk-stm32f.c
+++ b/drivers/clk/stm32/clk-stm32f.c
@@ -530,7 +530,8 @@  static ulong stm32_set_rate(struct clk *clk, ulong rate)
 			/* set pll_saidivr with found value */
 			clrsetbits_le32(&regs->dckcfgr,
 					RCC_DCKCFGR_PLLSAIDIVR_MASK,
-					pllsaidivr_table[i]);
+					pllsaidivr_table[i] <<
+					RCC_DCKCFGR_PLLSAIDIVR_SHIFT);
 			return rate;
 		}