@@ -30,6 +30,7 @@
#include <imx8m_ccm.h>
#include <imx8m_csu.h>
#include <imx8m_snvs.h>
+
#include <plat_imx8.h>
#define TRUSTY_PARAMS_LEN_BYTES (4096*2)
@@ -66,8 +67,8 @@ static const struct imx_rdc_cfg rdc[] = {
RDC_MDAn(RDC_MDA_M4, DID1),
/* peripherals domain permission */
- RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W),
- RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W),
+ RDC_PDAPn(RDC_PDAP_UART4, PDAPn_UART_DOMAIN(UART4_BASE_ADDR, D1R | D1W)),
+ RDC_PDAPn(RDC_PDAP_UART2, PDAPn_UART_DOMAIN(UART2_BASE_ADDR, D1R | D1W)),
/* memory region */
@@ -28,6 +28,7 @@
#include <imx8m_ccm.h>
#include <imx8m_csu.h>
#include <imx8m_snvs.h>
+#include <imx8m_uart.h>
#include <platform_def.h>
#include <plat_imx8.h>
@@ -52,8 +53,8 @@ static const struct imx_rdc_cfg rdc[] = {
RDC_MDAn(RDC_MDA_M7, DID1),
/* peripherals domain permission */
- RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W),
- RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W),
+ RDC_PDAPn(RDC_PDAP_UART4, PDAPn_UART_DOMAIN(UART4_BASE_ADDR, D1R | D1W)),
+ RDC_PDAPn(RDC_PDAP_UART2, PDAPn_UART_DOMAIN(UART2_BASE_ADDR, D1R | D1W)),
/* memory region */
RDC_MEM_REGIONn(16, 0x0, 0x0, 0xff),
new file mode 100644
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2024, Amarula Solutions B.V.
+ *
+ * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+ */
+
+#ifndef IMX8M_UART_H
+#define IMX8M_UART_H
+
+#define UART1_BASE_ADDR 0x30860000
+#define UART2_BASE_ADDR 0x30890000
+#define UART3_BASE_ADDR 0x30880000
+#define UART4_BASE_ADDR 0x30A60000
+
+#endif /*IMX8M_UART_H */
@@ -36,6 +36,9 @@
#define D0R BIT(1)
#define D0W BIT(0)
+#define PDAPn_UART_DOMAIN(base, def_domain) \
+ (IMX_BOOT_UART_BASE == base ? D0R | D0W : def_domain)
+
union rdc_setting {
uint32_t rdc_mda; /* Master Domain Assignment */
uint32_t rdc_pdap; /* Peripheral Domain Access Permissions */
The commit d76f012ea8fc0 ("refactor(imx8m): replace magic number with enum type") also hardcodes the domain permissions for the UARTs, without considering that read/write rights for domain 0 must be enabled for the boot UART. This creates a regression. Indeed, previously, the RDC_PDAP_UARTn registers were set to the reset value (0xff), meaning all domains were enabled for read and write access. The patch fixes this issue by assigning read/write rights for domain 0 to the boot UART. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> --- plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c | 5 +++-- plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c | 5 +++-- plat/imx/imx8m/include/imx8m_uart.h | 15 +++++++++++++++ plat/imx/imx8m/include/imx_rdc.h | 3 +++ 4 files changed, 24 insertions(+), 4 deletions(-) create mode 100644 plat/imx/imx8m/include/imx8m_uart.h