[07/29] clk: imx8mn: Mark IMX8MN_SYS_PLL2 and IMX8MN_SYS_PLL3 as enabled
diff mbox series

Message ID 20240903153100.918077-7-dario.binacchi@amarulasolutions.com
State New
Headers show
Series
  • [01/29] clk: Propagate clk_set_rate() if CLK_SET_PARENT_RATE present for gate and mux
Related show

Commit Message

Dario Binacchi Sept. 3, 2024, 3:30 p.m. UTC 
From: Michael Trimarchi <michael@amarulasolutions.com>

Both clock are enabled by the bootloader and we need to increase their
reference count to avoid disable during reparent operation.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
---
 drivers/clk/imx/clk-imx8mn.c | 8 ++++++++
 1 file changed, 8 insertions(+)

Patch
diff mbox series 

diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index e089012477a6..31d2faa97a3e 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -151,6 +151,7 @@  static const char * const imx8mn_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_10
 static int imx8mn_clk_probe(struct udevice *dev)
 {
 	struct clk osc_24m_clk;
+	struct clk *clk;
 	void __iomem *base;
 	int ret;
 
@@ -417,6 +418,13 @@  static int imx8mn_clk_probe(struct udevice *dev)
 	clk_dm(IMX8MN_CLK_ECSPI3_ROOT,
 	       imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
 #endif
+	ret = clk_get_by_id(IMX8MN_SYS_PLL2, &clk);
+	if (!ret)
+		clk_enable(clk);
+
+	ret = clk_get_by_id(IMX8MN_SYS_PLL3, &clk);
+	if (!ret)
+		clk_enable(clk);
 
 	return 0;
 }