[v2,06/27] clk: imx8mm: Mark IMX8MM_SYS_PLL2 and IMX8MM_SYS_PLL3 as enabled
diff mbox series

Message ID 20240911151039.2914886-6-dario.binacchi@amarulasolutions.com
State New
Headers show
Series
  • [v2,01/27] clk: Propagate clk_set_rate() if CLK_SET_PARENT_RATE present for gate and mux
Related show

Commit Message

Dario Binacchi Sept. 11, 2024, 3:10 p.m. UTC 
From: Michael Trimarchi <michael@amarulasolutions.com>

Both clock are enabled by the bootloader and we need to increase their
reference count to avoid disable during reparent operation.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
---
 drivers/clk/imx/clk-imx8mm.c | 9 +++++++++
 1 file changed, 9 insertions(+)

Patch
diff mbox series 

diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 685e7df0e568..275f1196865b 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -170,6 +170,8 @@  static const char * const imx8mm_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200
 static int imx8mm_clk_probe(struct udevice *dev)
 {
 	void __iomem *base;
+	struct clk *clk;
+	int ret;
 
 	base = (void *)ANATOP_BASE_ADDR;
 
@@ -448,6 +450,13 @@  static int imx8mm_clk_probe(struct udevice *dev)
 	clk_dm(IMX8MM_CLK_QSPI_ROOT,
 	       imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
 #endif
+	ret = clk_get_by_id(IMX8MM_SYS_PLL2, &clk);
+	if (!ret)
+		clk_enable(clk);
+
+	ret = clk_get_by_id(IMX8MM_SYS_PLL3, &clk);
+	if (!ret)
+		clk_enable(clk);
 
 	return 0;
 }