[4/4] board: bsh: imx6ulz_smm_m2: Add delay between DRAM read access
diff mbox series

Message ID 20250513123039.1676913-4-dario.binacchi@amarulasolutions.com
State New
Headers show
Series
  • [1/4] board: bsh: imx6ulz_smm_m2: Match SPL DDR settings to DCD table
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Commit Message

Dario Binacchi May 13, 2025, 12:30 p.m. UTC 
From: Michael Bode <michael.bode@bshg.com>

A small delay between DRAM read access with wrong parameters and
reconfiguration is necessary.
Without a delay between DRAM read access and a following reconfiguration
this reconfiguration fails for certain DRAM chips (Nanya).

Signed-off-by: Michael Bode <michael.bode@bshg.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
 board/bsh/imx6ulz_smm_m2/spl.c | 3 +++
 1 file changed, 3 insertions(+)

Patch
diff mbox series 

diff --git a/board/bsh/imx6ulz_smm_m2/spl.c b/board/bsh/imx6ulz_smm_m2/spl.c
index dba5982d0865..d1d38163ec19 100644
--- a/board/bsh/imx6ulz_smm_m2/spl.c
+++ b/board/bsh/imx6ulz_smm_m2/spl.c
@@ -13,6 +13,7 @@ 
 #include <asm/gpio.h>
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm/mach-imx/boot_mode.h>
+#include <linux/delay.h>
 #include <linux/libfdt.h>
 #include <spl.h>
 #include <asm/arch/mx6-ddr.h>
@@ -65,10 +66,12 @@  static void spl_dram_init(void)
 		/* Already configured, nothing to do */
 		break;
 	case SZ_256M:
+		udelay(1);
 		ddr_cfg_write(&bsh_dram_timing_256mb);
 		break;
 	case SZ_128M:
 	default:
+		udelay(1);
 		ddr_cfg_write(&bsh_dram_timing_128mb);
 		break;
 	}