[v3,6/9] spi: stm32: add stm32_spi_is_enabled() helper

Message ID 20260225161851.2475274-7-dario.binacchi@amarulasolutions.com
State New
Headers show
Series
  • video: support Rocktech RK050HR345-CT106A panel
Related show

Commit Message

Dario Binacchi Feb. 25, 2026, 4:16 p.m. UTC
Add a helper to check the SPE (SPI Enable) bit and replace the
open-coded bitwise check in stm32_spi_stopxfer() with this helper to
improve readability and consistency.

This is also a preparatory step for future driver updates that require
checking the SPI enable state across different code paths.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---

(Added in v3)

 drivers/spi/stm32_spi.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

Comments

Patrice CHOTARD Feb. 26, 2026, 7:56 a.m. UTC | #1
On 2/25/26 17:16, Dario Binacchi wrote:
> Add a helper to check the SPE (SPI Enable) bit and replace the
> open-coded bitwise check in stm32_spi_stopxfer() with this helper to
> improve readability and consistency.
> 
> This is also a preparatory step for future driver updates that require
> checking the SPI enable state across different code paths.
> 
> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
> ---
> 
> (Added in v3)
> 
>  drivers/spi/stm32_spi.c | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/spi/stm32_spi.c b/drivers/spi/stm32_spi.c
> index adba97915cd3..70eb8735e03d 100644
> --- a/drivers/spi/stm32_spi.c
> +++ b/drivers/spi/stm32_spi.c
> @@ -192,6 +192,11 @@ static void stm32_spi_read_rxfifo(struct udevice *bus)
>  	log_debug("%d bytes left\n", priv->rx_len);
>  }
>  
> +static bool stm32_spi_is_enabled(void __iomem *base)
> +{
> +	return !!(readl(base + STM32_SPI_CR1) & SPI_CR1_SPE);
> +}
> +
>  static int stm32_spi_enable(void __iomem *base)
>  {
>  	log_debug("\n");
> @@ -245,9 +250,7 @@ static void stm32_spi_stopxfer(struct udevice *dev)
>  
>  	dev_dbg(dev, "\n");
>  
> -	cr1 = readl(base + STM32_SPI_CR1);
> -
> -	if (!(cr1 & SPI_CR1_SPE))
> +	if (!stm32_spi_is_enabled(base))
>  		return;
>  
>  	/* Wait on EOT or suspend the flow */

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>

Thanks
Patrice

To unsubscribe from this group and stop receiving emails from it, send an email to linux-amarula+unsubscribe@amarulasolutions.com.

Patch

diff --git a/drivers/spi/stm32_spi.c b/drivers/spi/stm32_spi.c
index adba97915cd3..70eb8735e03d 100644
--- a/drivers/spi/stm32_spi.c
+++ b/drivers/spi/stm32_spi.c
@@ -192,6 +192,11 @@  static void stm32_spi_read_rxfifo(struct udevice *bus)
 	log_debug("%d bytes left\n", priv->rx_len);
 }
 
+static bool stm32_spi_is_enabled(void __iomem *base)
+{
+	return !!(readl(base + STM32_SPI_CR1) & SPI_CR1_SPE);
+}
+
 static int stm32_spi_enable(void __iomem *base)
 {
 	log_debug("\n");
@@ -245,9 +250,7 @@  static void stm32_spi_stopxfer(struct udevice *dev)
 
 	dev_dbg(dev, "\n");
 
-	cr1 = readl(base + STM32_SPI_CR1);
-
-	if (!(cr1 & SPI_CR1_SPE))
+	if (!stm32_spi_is_enabled(base))
 		return;
 
 	/* Wait on EOT or suspend the flow */